Lines Matching refs:rn
648 void And(const Register& rd, const Register& rn, const Operand& operand);
649 void Ands(const Register& rd, const Register& rn, const Operand& operand);
650 void Bic(const Register& rd, const Register& rn, const Operand& operand);
651 void Bics(const Register& rd, const Register& rn, const Operand& operand);
652 void Orr(const Register& rd, const Register& rn, const Operand& operand);
653 void Orn(const Register& rd, const Register& rn, const Operand& operand);
654 void Eor(const Register& rd, const Register& rn, const Operand& operand);
655 void Eon(const Register& rd, const Register& rn, const Operand& operand);
656 void Tst(const Register& rn, const Operand& operand);
658 const Register& rn,
664 const Register& rn,
667 void Adds(const Register& rd, const Register& rn, const Operand& operand);
669 const Register& rn,
672 void Subs(const Register& rd, const Register& rn, const Operand& operand);
673 void Cmn(const Register& rn, const Operand& operand);
674 void Cmp(const Register& rn, const Operand& operand);
679 const Register& rn,
685 void Adc(const Register& rd, const Register& rn, const Operand& operand);
686 void Adcs(const Register& rd, const Register& rn, const Operand& operand);
687 void Sbc(const Register& rd, const Register& rn, const Operand& operand);
688 void Sbcs(const Register& rd, const Register& rn, const Operand& operand);
692 const Register& rn,
727 void Ccmp(const Register& rn,
731 void Ccmn(const Register& rn,
735 void ConditionalCompareMacro(const Register& rn,
980 void Asr(const Register& rd, const Register& rn, unsigned shift) { in Asr() argument
983 VIXL_ASSERT(!rn.IsZero()); in Asr()
985 asr(rd, rn, shift); in Asr()
987 void Asr(const Register& rd, const Register& rn, const Register& rm) { in Asr() argument
990 VIXL_ASSERT(!rn.IsZero()); in Asr()
993 asrv(rd, rn, rm); in Asr()
1016 const Register& rn, in Bfm() argument
1021 VIXL_ASSERT(!rn.IsZero()); in Bfm()
1023 bfm(rd, rn, immr, imms); in Bfm()
1026 const Register& rn, in Bfi() argument
1031 VIXL_ASSERT(!rn.IsZero()); in Bfi()
1033 bfi(rd, rn, lsb, width); in Bfi()
1036 const Register& rn, in Bfxil() argument
1041 VIXL_ASSERT(!rn.IsZero()); in Bfxil()
1043 bfxil(rd, rn, lsb, width); in Bfxil()
1072 void Cinc(const Register& rd, const Register& rn, Condition cond) { in Cinc() argument
1075 VIXL_ASSERT(!rn.IsZero()); in Cinc()
1077 cinc(rd, rn, cond); in Cinc()
1079 void Cinv(const Register& rd, const Register& rn, Condition cond) { in Cinv() argument
1082 VIXL_ASSERT(!rn.IsZero()); in Cinv()
1084 cinv(rd, rn, cond); in Cinv()
1091 void Cls(const Register& rd, const Register& rn) { in Cls() argument
1094 VIXL_ASSERT(!rn.IsZero()); in Cls()
1096 cls(rd, rn); in Cls()
1098 void Clz(const Register& rd, const Register& rn) { in Clz() argument
1101 VIXL_ASSERT(!rn.IsZero()); in Clz()
1103 clz(rd, rn); in Clz()
1105 void Cneg(const Register& rd, const Register& rn, Condition cond) { in Cneg() argument
1108 VIXL_ASSERT(!rn.IsZero()); in Cneg()
1110 cneg(rd, rn, cond); in Cneg()
1125 const Register& rn, in Csinc() argument
1130 VIXL_ASSERT(!rn.IsZero()); in Csinc()
1134 csinc(rd, rn, rm, cond); in Csinc()
1137 const Register& rn, in Csinv() argument
1142 VIXL_ASSERT(!rn.IsZero()); in Csinv()
1146 csinv(rd, rn, rm, cond); in Csinv()
1149 const Register& rn, in Csneg() argument
1154 VIXL_ASSERT(!rn.IsZero()); in Csneg()
1158 csneg(rd, rn, rm, cond); in Csneg()
1171 const Register& rn, in Extr() argument
1176 VIXL_ASSERT(!rn.IsZero()); in Extr()
1179 extr(rd, rn, rm, lsb); in Extr()
1354 void Fmov(const VRegister& vd, const Register& rn) { in Fmov() argument
1356 VIXL_ASSERT(!rn.IsZero()); in Fmov()
1358 fmov(vd, rn); in Fmov()
1366 void Fmov(const VRegister& vd, int index, const Register& rn) { in Fmov() argument
1369 fmov(vd, index, rn); in Fmov()
1602 void Lsl(const Register& rd, const Register& rn, unsigned shift) { in Lsl() argument
1605 VIXL_ASSERT(!rn.IsZero()); in Lsl()
1607 lsl(rd, rn, shift); in Lsl()
1609 void Lsl(const Register& rd, const Register& rn, const Register& rm) { in Lsl() argument
1612 VIXL_ASSERT(!rn.IsZero()); in Lsl()
1615 lslv(rd, rn, rm); in Lsl()
1617 void Lsr(const Register& rd, const Register& rn, unsigned shift) { in Lsr() argument
1620 VIXL_ASSERT(!rn.IsZero()); in Lsr()
1622 lsr(rd, rn, shift); in Lsr()
1624 void Lsr(const Register& rd, const Register& rn, const Register& rm) { in Lsr() argument
1627 VIXL_ASSERT(!rn.IsZero()); in Lsr()
1630 lsrv(rd, rn, rm); in Lsr()
1633 const Register& rn, in Madd() argument
1638 VIXL_ASSERT(!rn.IsZero()); in Madd()
1642 madd(rd, rn, rm, ra); in Madd()
1644 void Mneg(const Register& rd, const Register& rn, const Register& rm) { in Mneg() argument
1647 VIXL_ASSERT(!rn.IsZero()); in Mneg()
1650 mneg(rd, rn, rm); in Mneg()
1653 const Register& rn,
1665 if (!rd.Is(rn) ||
1668 mov(rd, rn);
1705 const Register& rn, in Msub() argument
1710 VIXL_ASSERT(!rn.IsZero()); in Msub()
1714 msub(rd, rn, rm, ra); in Msub()
1716 void Mul(const Register& rd, const Register& rn, const Register& rm) { in Mul() argument
1719 VIXL_ASSERT(!rn.IsZero()); in Mul()
1722 mul(rd, rn, rm); in Mul()
1729 void Rbit(const Register& rd, const Register& rn) { in Rbit() argument
1732 VIXL_ASSERT(!rn.IsZero()); in Rbit()
1734 rbit(rd, rn); in Rbit()
1742 void Rev(const Register& rd, const Register& rn) { in Rev() argument
1745 VIXL_ASSERT(!rn.IsZero()); in Rev()
1747 rev(rd, rn); in Rev()
1749 void Rev16(const Register& rd, const Register& rn) { in Rev16() argument
1752 VIXL_ASSERT(!rn.IsZero()); in Rev16()
1754 rev16(rd, rn); in Rev16()
1756 void Rev32(const Register& rd, const Register& rn) { in Rev32() argument
1759 VIXL_ASSERT(!rn.IsZero()); in Rev32()
1761 rev32(rd, rn); in Rev32()
1770 void Ror(const Register& rd, const Register& rn, const Register& rm) { in Ror() argument
1773 VIXL_ASSERT(!rn.IsZero()); in Ror()
1776 rorv(rd, rn, rm); in Ror()
1779 const Register& rn, in Sbfiz() argument
1784 VIXL_ASSERT(!rn.IsZero()); in Sbfiz()
1786 sbfiz(rd, rn, lsb, width); in Sbfiz()
1789 const Register& rn, in Sbfm() argument
1794 VIXL_ASSERT(!rn.IsZero()); in Sbfm()
1796 sbfm(rd, rn, immr, imms); in Sbfm()
1799 const Register& rn, in Sbfx() argument
1804 VIXL_ASSERT(!rn.IsZero()); in Sbfx()
1806 sbfx(rd, rn, lsb, width); in Sbfx()
1808 void Scvtf(const VRegister& vd, const Register& rn, int fbits = 0) {
1810 VIXL_ASSERT(!rn.IsZero());
1812 scvtf(vd, rn, fbits);
1814 void Sdiv(const Register& rd, const Register& rn, const Register& rm) { in Sdiv() argument
1817 VIXL_ASSERT(!rn.IsZero()); in Sdiv()
1820 sdiv(rd, rn, rm); in Sdiv()
1823 const Register& rn, in Smaddl() argument
1828 VIXL_ASSERT(!rn.IsZero()); in Smaddl()
1832 smaddl(rd, rn, rm, ra); in Smaddl()
1835 const Register& rn, in Smsubl() argument
1840 VIXL_ASSERT(!rn.IsZero()); in Smsubl()
1844 smsubl(rd, rn, rm, ra); in Smsubl()
1846 void Smull(const Register& rd, const Register& rn, const Register& rm) { in Smull() argument
1849 VIXL_ASSERT(!rn.IsZero()); in Smull()
1852 smull(rd, rn, rm); in Smull()
1953 void Sxtb(const Register& rd, const Register& rn) { in Sxtb() argument
1956 VIXL_ASSERT(!rn.IsZero()); in Sxtb()
1958 sxtb(rd, rn); in Sxtb()
1960 void Sxth(const Register& rd, const Register& rn) { in Sxth() argument
1963 VIXL_ASSERT(!rn.IsZero()); in Sxth()
1965 sxth(rd, rn); in Sxth()
1967 void Sxtw(const Register& rd, const Register& rn) { in Sxtw() argument
1970 VIXL_ASSERT(!rn.IsZero()); in Sxtw()
1972 sxtw(rd, rn); in Sxtw()
2041 const Register& rn, in Ubfiz() argument
2046 VIXL_ASSERT(!rn.IsZero()); in Ubfiz()
2048 ubfiz(rd, rn, lsb, width); in Ubfiz()
2051 const Register& rn, in Ubfm() argument
2056 VIXL_ASSERT(!rn.IsZero()); in Ubfm()
2058 ubfm(rd, rn, immr, imms); in Ubfm()
2061 const Register& rn, in Ubfx() argument
2066 VIXL_ASSERT(!rn.IsZero()); in Ubfx()
2068 ubfx(rd, rn, lsb, width); in Ubfx()
2070 void Ucvtf(const VRegister& vd, const Register& rn, int fbits = 0) {
2072 VIXL_ASSERT(!rn.IsZero());
2074 ucvtf(vd, rn, fbits);
2076 void Udiv(const Register& rd, const Register& rn, const Register& rm) { in Udiv() argument
2079 VIXL_ASSERT(!rn.IsZero()); in Udiv()
2082 udiv(rd, rn, rm); in Udiv()
2085 const Register& rn, in Umaddl() argument
2090 VIXL_ASSERT(!rn.IsZero()); in Umaddl()
2094 umaddl(rd, rn, rm, ra); in Umaddl()
2096 void Umull(const Register& rd, const Register& rn, const Register& rm) { in Umull() argument
2099 VIXL_ASSERT(!rn.IsZero()); in Umull()
2102 umull(rd, rn, rm); in Umull()
2113 const Register& rn, in Umsubl() argument
2118 VIXL_ASSERT(!rn.IsZero()); in Umsubl()
2122 umsubl(rd, rn, rm, ra); in Umsubl()
2135 void Uxtb(const Register& rd, const Register& rn) { in Uxtb() argument
2138 VIXL_ASSERT(!rn.IsZero()); in Uxtb()
2140 uxtb(rd, rn); in Uxtb()
2142 void Uxth(const Register& rd, const Register& rn) { in Uxth() argument
2145 VIXL_ASSERT(!rn.IsZero()); in Uxth()
2147 uxth(rd, rn); in Uxth()
2149 void Uxtw(const Register& rd, const Register& rn) { in Uxtw() argument
2152 VIXL_ASSERT(!rn.IsZero()); in Uxtw()
2154 uxtw(rd, rn); in Uxtw()
2521 void Dup(const VRegister& vd, const Register& rn) { in Dup() argument
2524 dup(vd, rn); in Dup()
2542 void Ins(const VRegister& vd, int vd_index, const Register& rn) { in Ins() argument
2545 ins(vd, vd_index, rn); in Ins()
2668 void Mov(const VRegister& vd, int vd_index, const Register& rn) { in Mov() argument
2671 mov(vd, vd_index, rn); in Mov()
2807 void Crc32b(const Register& rd, const Register& rn, const Register& rm) { in Crc32b() argument
2810 crc32b(rd, rn, rm); in Crc32b()
2812 void Crc32h(const Register& rd, const Register& rn, const Register& rm) { in Crc32h() argument
2815 crc32h(rd, rn, rm); in Crc32h()
2817 void Crc32w(const Register& rd, const Register& rn, const Register& rm) { in Crc32w() argument
2820 crc32w(rd, rn, rm); in Crc32w()
2822 void Crc32x(const Register& rd, const Register& rn, const Register& rm) { in Crc32x() argument
2825 crc32x(rd, rn, rm); in Crc32x()
2827 void Crc32cb(const Register& rd, const Register& rn, const Register& rm) { in Crc32cb() argument
2830 crc32cb(rd, rn, rm); in Crc32cb()
2832 void Crc32ch(const Register& rd, const Register& rn, const Register& rm) { in Crc32ch() argument
2835 crc32ch(rd, rn, rm); in Crc32ch()
2837 void Crc32cw(const Register& rd, const Register& rn, const Register& rm) { in Crc32cw() argument
2840 crc32cw(rd, rn, rm); in Crc32cw()
2842 void Crc32cx(const Register& rd, const Register& rn, const Register& rm) { in Crc32cx() argument
2845 crc32cx(rd, rn, rm); in Crc32cx()