Lines Matching refs:Rs
254 ((Rs INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
274 ((Rs INT -1))
292 ((Rd INT -1) (Rs INT -1))
299 ((Rs INT -1))
306 ((Rs INT -1))
1537 ; Rs := source operand, register addressing mode
1538 (dnop Rs "Source general register" () h-gr f-source)
1540 ; [Rs] := source operand, indirect addressing mode
1541 ; = MODE_INDIRECT Rs
1543 ; [Rs+] := source operand, autoincrement addressing mode (see note!)
1544 ; = MODE_AUTOINCREMENT Rs
1546 ; The union of [Rs] and [Rs(+)]
1547 ; = MODEMEMP_YES Rs
1557 ; s := source operand, any of the modes Rs, [Rs] or [Rs+]
1585 (define-pmacro Rd-sfield Rs)
1586 (define-pmacro Rs-dfield Rd)
1973 ; MOVE.m Rs,Rd [ Rd | 011001mm | Rs ]
1976 "move.m ${Rs},${Rd}"
1977 (+ Rd MODE_REGISTER R_MOVE Rs)
1982 (set newval Rs)
2028 ; MOVS.z Rs,Rd [ Rd | 0100011z | Rs ]
2031 "movs.m ${Rs},${Rd}"
2032 (+ Rd MODE_REGISTER R_MOVX Rs)
2037 (set tmpops Rs)
2056 ; MOVU.z Rs,Rd [ Rd | 0100010z | Rs ]
2059 "movu.m ${Rs},${Rd}"
2060 (+ Rd MODE_REGISTER R_MOVX Rs)
2065 (set tmpops Rs)
2362 ; CMP.m Rs,Rd [ Rd | 011011mm | Rs ]
2365 "$Rs,$Rd"
2366 (+ Rd MODE_REGISTER R_CMP Rs)
2371 Rd Rs cbit cbit))
2374 ; CMP.m [Rs],Rd [ Rd | 101011mm | Rs ]
2375 ; CMP.m [Rs+],Rd [ Rd | 111011mm | Rs ]
2378 "[${Rs}${inc}],${Rd}"
2379 (+ INDIR_CMP Rs Rd)
2384 Rd (cris-get-mem BWD Rs) cbit cbit))
2425 ; CMPS.z [Rs],Rd [ Rd | 1000111z | Rs ]
2426 ; CMPS.z [Rs+],Rd [ Rd | 1100111z | Rs ]
2429 "[${Rs}${inc}],$Rd"
2430 (+ Rd INDIR_CMPX Rs)
2435 Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit))
2441 "[${Rs}${inc}],$Rd"
2449 "[${Rs}${inc}],$Rd"
2456 ; CMPU.z [Rs],Rd [ Rd | 1000110z | Rs ]
2457 ; CMPU.z [Rs+],Rd [ Rd | 1100110z | Rs ]
2460 "[${Rs}${inc}],$Rd"
2461 (+ Rd INDIR_CMPX Rs)
2466 Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit))
2472 "[${Rs}${inc}],$Rd"
2480 "[${Rs}${inc}],$Rd"
2487 ; MOVE.m [Rs],Rd [ Rd | 101001mm | Rs ]
2488 ; MOVE.m [Rs+],Rd [ Rd | 111001mm | Rs ]
2491 "[${Rs}${inc}],${Rd}"
2492 (+ INDIR_MOVE_M_R Rs Rd)
2497 (set tmp (cris-get-mem BWD Rs))
2500 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd))
2505 ; MOVS.z [Rs],Rd [ Rd | 1000011z | Rs ]
2506 ; MOVS.z [Rs+],Rd [ Rd | 1100011z | Rs ]
2509 "[${Rs}${inc}],${Rd}"
2510 (+ INDIR_MOVX Rs Rd)
2515 (set tmp (ext SI (cris-get-mem BW Rs)))
2517 (set Rs tmp)
2522 ; MOVU.z [Rs],Rd [ Rd | 1000010z | Rs ]
2523 ; MOVU.z [Rs+],Rd [ Rd | 1100010z | Rs ]
2526 "[${Rs}${inc}],${Rd}"
2527 (+ INDIR_MOVX Rs Rd)
2532 (set tmp (zext SI (cris-get-mem BW Rs)))
2534 (set Rs tmp)
2539 ; MOVE Rs,Pd [ Pd | 01100011 | Rs ]
2550 "move ${Rs},${Pd}"
2551 (+ RFIX_MOVE_R_S MODE_REGISTER SIZE_FIXED Rs Pd)
2554 (set tmp Rs)
2580 ; Note that in the insn format, the Rd operand is in the Rs field (the
2638 ; MOVE [Rs],Pd [ Pd | 10100011 | Rs ]
2639 ; MOVE [Rs+],Pd [ Pd | 11100011 | Rs ]
2653 "move [${Rs}${inc}],${Pd}"
2654 (+ Pd INFIX_MOVE_M_S MODEMEMP_YES inc SIZE_FIXED Rs)
2668 (set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs)))))
2759 ; SBFS [Rs(+)]
2783 ; MOVE Rs,Sd [ Sd | 10110111 | Rs ]
2788 "move ${Rs},${Sd}"
2789 (+ Sd INFIX_MOVE_SS SIZE_FIXED (f-mode 2) Rs)
2792 (set Sd Rs)
2796 ; MOVEM Rs,[Rd] [ Rs | 10111111 | Rd ]
2797 ; MOVEM Rs,[Rd+] [ Rs | 11111111 | Rd ]
2802 (if (ge SI (regno Rs-dfield) regn)
2814 "movem ${Rs-dfield},[${Rd-sfield}${inc}]"
2815 (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield)
2824 ; Rs-dfield is used as an input, causing the timing model to be wrong.
2825 (sequence ((SI dummy)) (set dummy Rs-dfield))
2850 "movem ${Rs-dfield},[${Rd-sfield}${inc}]"
2851 (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield)
2860 (sequence ((SI dummy)) (set dummy Rs-dfield))
2878 ; MOVEM [Rs],Rd [ Rd | 10111011 | Rs ]
2879 ; MOVEM [Rs+],Rd [ Rd | 11111011 | Rs ]
2897 "movem [${Rs}${inc}],${Rd}"
2898 (+ Rd INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs)
2910 Rs
2925 (set Rs (if SI (eq prefix-set 0) addr prefixreg)))
2930 ; (MOVEM [Rs],PC [ 1111 | 10111011 | Rs ])
2931 ; (MOVEM [Rs+],PC [ 1111 | 11111011 | Rs ])
2941 "movem [${Rs}${inc}],${Rd}"
2942 (+ (f-dest 15) INFIX_MOVEM_M_R SIZE_FIXED Rs)
2954 Rs
2978 (set Rs (if SI (eq prefix-set 0) addr prefixreg)))
2986 "movem [${Rs}${inc}],${Rd}"
2987 (+ INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs Rd)
2996 (set addr Rs)
3008 (set Rs addr))
3016 ; ADD.m Rs,Rd [ Rd | 011000mm | Rs ]
3019 "$Rs,$Rd"
3020 (+ Rd MODE_REGISTER R_ADD Rs)
3021 (.pmacro (BWD) (cris-arit add BWD Rd Rs))
3024 ; ADD.m [Rs],Rd [ Rd | 101000mm | Rs ]
3025 ; ADD.m [Rs+],Rd [ Rd | 111000mm | Rs ]
3028 "[${Rs}${inc}],${Rd}"
3029 (+ INDIR_ADD Rs Rd)
3030 (.pmacro (BWD) (cris-arit-3op add BWD Rd (cris-get-mem BWD Rs) Rs))
3071 ; ADDS.z Rs,Rd [ Rd | 0100001z | Rs ]
3074 "$Rs,$Rd"
3075 (+ Rd MODE_REGISTER R_ADDX Rs)
3076 (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -ext) (trunc BW Rs))))
3079 ; ADDS.z [Rs],Rd [ Rd | 1000001z | Rs ]
3080 ; ADDS.z [Rs+],Rd [ Rd | 1100001z | Rs ]
3083 "[${Rs}${inc}],$Rd"
3084 (+ Rd INDIR_ADDX Rs)
3085 (.pmacro (BW) (cris-arit-3op add SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs))
3091 "[${Rs}${inc}],$Rd"
3097 "[${Rs}${inc}],$Rd"
3127 ; ADDU.z Rs,Rd [ Rd | 0100000z | Rs ]
3130 "$Rs,$Rd"
3131 (+ Rd MODE_REGISTER R_ADDX Rs)
3132 (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -zext) (trunc BW Rs))))
3135 ; ADDU.z [Rs],Rd [ Rd | 1000000z | Rs ]
3136 ; ADDU.z [Rs+],Rd [ Rd | 1100000z | Rs ]
3139 "[${Rs}${inc}],$Rd"
3140 (+ Rd INDIR_ADDX Rs)
3142 (cris-arit-3op add SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs))
3148 "[${Rs}${inc}],$Rd"
3154 "[${Rs}${inc}],$Rd"
3159 ; SUB.m Rs,Rd [ Rd | 011010mm | Rs ]
3162 "$Rs,$Rd"
3163 (+ Rd MODE_REGISTER R_SUB Rs)
3164 (.pmacro (BWD) (cris-arit sub BWD Rd Rs))
3167 ; SUB.m [Rs],Rd [ Rd | 101010mm | Rs ]
3168 ; SUB.m [Rs+],Rd [ Rd | 111010mm | Rs ]
3171 "[${Rs}${inc}],${Rd}"
3172 (+ INDIR_SUB Rs Rd)
3173 (.pmacro (BWD) (cris-arit-3op sub BWD Rd (cris-get-mem BWD Rs) Rs))
3198 ; SUBS.z Rs,Rd [ Rd | 0100101z | Rs ]
3201 "$Rs,$Rd"
3202 (+ Rd MODE_REGISTER R_SUBX Rs)
3203 (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -ext) (trunc BW Rs))))
3206 ; SUBS.z [Rs],Rd [ Rd | 1000101z | Rs ]
3207 ; SUBS.z [Rs+],Rd [ Rd | 1100101z | Rs ]
3210 "[${Rs}${inc}],$Rd"
3211 (+ Rd INDIR_SUBX Rs)
3213 (cris-arit-3op sub SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs))
3219 "[${Rs}${inc}],$Rd"
3225 "[${Rs}${inc}],$Rd"
3230 ; SUBU.z Rs,Rd [ Rd | 0100100z | Rs ]
3233 "$Rs,$Rd"
3234 (+ Rd MODE_REGISTER R_SUBX Rs)
3235 (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -zext) (trunc BW Rs))))
3238 ; SUBU.z [Rs],Rd [ Rd | 1000100z | Rs ]
3239 ; SUBU.z [Rs+],Rd [ Rd | 1100100z | Rs ]
3242 "[${Rs}${inc}],$Rd"
3243 (+ Rd INDIR_SUBX Rs)
3245 (cris-arit-3op sub SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs))
3251 "[${Rs}${inc}],$Rd"
3257 "[${Rs}${inc}],$Rd"
3262 ; ADDC Rs,Rd [ Rd | 01010111 | Rs ]
3266 "addc $Rs,$Rd"
3267 (+ Rd MODE_REGISTER RFIX_ADDC SIZE_FIXED Rs)
3268 ; Since this is equivalent to "ax" plus "add.d Rs,Rd", we'll just do
3273 (cris-arit add SI Rd Rs))
3276 ; ADDC [Rs],Rd [ Rd | 10011010 | Rs ]
3277 ; ADDC [Rs+],Rd [ Rd | 11011010 | Rs ]
3281 "addc [${Rs}${inc}],${Rd}"
3282 (+ Rd INDIR_ADDC SIZE_DWORD Rs)
3286 (cris-arit add SI Rd (cris-get-mem SI Rs)))
3289 ; (ADDC [Rs+],Rd [ Rd | 11011010 | 1111 ])
3325 ; ADDI Rs.m,Rd [ Rs | 010100mm | Rd ]
3328 "${Rs-dfield}.m,${Rd-sfield}"
3329 (+ Rd-sfield MODE_REGISTER R_ADDI Rs-dfield)
3334 (set Rd-sfield (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size))))
3338 ; NEG.m Rs,Rd [ Rd | 010110mm | Rs ]
3340 neg "neg.m Rs,Rd"
3341 "$Rs,$Rd"
3342 (+ Rd MODE_REGISTER R_NEG Rs)
3343 (.pmacro (BWD) (cris-arit3 sub BWD Rd 0 Rs))
3346 ; TEST.m [Rs] [ 0000101110mm | Rs ]
3347 ; TEST.m [Rs+] [ 0000111110mm | Rs ]
3349 test-m "test.m [Rs(+)]"
3350 "[${Rs}${inc}]"
3351 (+ (f-dest 0) INDIR_TEST Rs)
3356 (set tmpd (cris-get-mem BWD Rs))
3362 ; MOVE.m Rs,[Rd] [ Rs | 101111mm | Rd ]
3363 ; MOVE.m Rs,[Rd+] [ Rs | 111111mm | Rd ]
3367 "${Rs-dfield},[${Rd-sfield}${inc}]"
3368 (+ Rs-dfield INDIR_MOVE_R_M Rd-sfield)
3373 (set tmpd Rs-dfield)
3378 ; MULS.m Rs,Rd [ Rd | 110100mm | Rs ]
3380 muls "muls.m Rs,Rd"
3382 "$Rs,$Rd"
3383 (+ Rd MODE_MULS INDIR_MUL Rs)
3388 (set src1 (ext DI (trunc BWD Rs)))
3398 ; MULU.m Rs,Rd [ Rd | 100100mm | Rs ]
3400 mulu "mulu.m Rs,Rd"
3402 "$Rs,$Rd"
3403 (+ Rd MODE_MULU INDIR_MUL Rs)
3408 (set src1 (zext DI (trunc BWD Rs)))
3431 ; MSTEP Rs,Rd [ Rd | 01111111 | Rs ]
3435 "mstep $Rs,$Rd"
3436 (+ Rd MODE_REGISTER RFIX_MSTEP SIZE_FIXED Rs)
3439 (set tmps Rs)
3445 ; DSTEP Rs,Rd [ Rd | 01101111 | Rs ]
3448 "dstep $Rs,$Rd"
3449 (+ Rd MODE_REGISTER RFIX_DSTEP SIZE_FIXED Rs)
3452 (set tmps Rs)
3459 ; ABS Rs,Rd [ Rd | 01101011 | Rs ]
3462 "abs $Rs,$Rd"
3463 (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs)
3466 (set tmpd (abs Rs))
3471 ; AND.m Rs,Rd [ Rd | 011100mm | Rs ]
3474 "$Rs,$Rd"
3475 (+ Rd MODE_REGISTER R_AND Rs)
3480 (set tmpd (and BWD Rd Rs))
3485 ; AND.m [Rs],Rd [ Rd | 101100mm | Rs ]
3486 ; AND.m [Rs+],Rd [ Rd | 111100mm | Rs ]
3489 "[${Rs}${inc}],${Rd}"
3490 (+ INDIR_AND Rs Rd)
3495 (set tmpd (and BWD Rd (cris-get-mem BWD Rs)))
3498 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd))
3549 ; OR.m Rs,Rd [ Rd | 011101mm | Rs ]
3552 "$Rs,$Rd"
3553 (+ Rd MODE_REGISTER R_OR Rs)
3558 (set tmpd (or BWD Rd Rs))
3563 ; OR.m [Rs],Rd [ Rd | 101101mm | Rs ]
3564 ; OR.m [Rs+],Rd [ Rd | 111101mm | Rs ]
3567 "[${Rs}${inc}],${Rd}"
3568 (+ INDIR_OR Rs Rd)
3573 (set tmpd (or BWD Rd (cris-get-mem BWD Rs)))
3576 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd))
3627 ; XOR Rs,Rd [ Rd | 01111011 | Rs ]
3630 "xor $Rs,$Rd"
3631 (+ Rd MODE_REGISTER RFIX_XOR SIZE_FIXED Rs)
3634 (set tmpd (xor SI Rd Rs))
3720 "not ${Rs}"
3734 "swap${swapoption} ${Rs}"
3744 ; ASR.m Rs,Rd [ Rd | 011110mm | Rs ]
3747 "$Rs,$Rd"
3748 (+ Rd MODE_REGISTER R_ASR Rs)
3753 (set cnt1 Rs)
3772 ; LSR.m Rs,Rd [ Rd | 011111mm | Rs ]
3775 "$Rs,$Rd"
3776 (+ Rd MODE_REGISTER R_LSR Rs)
3781 (set cnt (and Rs 63))
3803 ; LSL.m Rs,Rd [ Rd | 010011mm | Rs ]
3806 "$Rs,$Rd"
3807 (+ Rd MODE_REGISTER R_LSL Rs)
3812 (set cnt (and Rs 63))
3834 ; BTST Rs,Rd [ Rd | 01001111 | Rs ]
3837 "$Rs,$Rd"
3838 (+ Rd MODE_REGISTER RFIX_BTST SIZE_FIXED Rs)
3841 (set tmpd (sll Rd (sub 31 (and Rs 31))))
4055 ; JAS Rs,Pd [ Pd | 10011011 | Rs ]
4059 "jas ${Rs},${Pd}"
4060 (+ Pd MODE_INDIRECT INFIX_JAS_R SIZE_FIXED Rs)
4064 (if (andif (eq (regno Rs) 1) (eq (regno Pd) 11))
4073 (set pc Rs))))
4081 "jump/jsr/jir ${Rs}"
4082 (+ Pd MODE_INDIRECT INFIX_JUMP_R SIZE_FIXED Rs)
4086 (set pc Rs)
4111 "jump/jsr/jir [${Rs}${inc}]"
4112 (+ Pd INFIX_JUMP_M SIZE_FIXED Rs)
4116 (set pc (cris-get-mem SI Rs))
4163 ; JASC Rs,Pd [ Pd | 10110011 | Rs ]
4167 "jasc ${Rs},${Pd}"
4168 (+ Pd MODE_INDIRECT INFIX_JASC SIZE_FIXED Rs)
4176 (set pc Rs))))
4223 ; BOUND.m Rs,Rd [ Rd | 010111mm | Rs ]
4226 "${Rs},${Rd}"
4227 (+ Rd R_BOUND MODE_REGISTER Rs)
4232 (set tmpops ((.sym BWD -zext) (trunc BWD Rs)))
4239 ; BOUND.m [Rs],Rd [ Rd | 100111mm | Rs ]
4240 ; BOUND.m [Rs+],Rd [ Rd | 110111mm | Rs ]
4244 "[${Rs}${inc}],${Rd}"
4245 (+ Rd INDIR_BOUND Rs)
4250 (set tmpops ((.sym BWD -zext) (cris-get-mem BWD Rs)))
4254 (set Rs newval)
4309 ; LZ Rs,Rd [ Rd | 01110011 | Rs ]
4313 "lz ${Rs},${Rd}"
4314 (+ Rd MODE_REGISTER RFIX_LZ SIZE_FIXED Rs)
4317 (set tmp Rs)
4335 ; ADDOQ o,Rs,ACR [ Rs | 0001 | o ]
4338 "addoq $o,$Rs,ACR"
4339 (+ Rs-dfield MODE_QUICK_IMMEDIATE QHI_ADDOQ o)
4342 (set prefixreg (add SI Rs-dfield o))
4422 ; ADDO.m [Rs],Rd,ACR [ Rd | 100101mm | Rs ]
4423 ; ADDO.m [Rs+],Rd,ACR [ Rd | 110101mm | Rs ]
4426 "[${Rs}${inc}],$Rd,ACR"
4427 (+ Rd INDIR_ADDO Rs)
4432 (set tmps (cris-get-mem BWD Rs))
4471 "dip [${Rs}${inc}]"
4472 (+ (f-dest 0) INFIX_DIP SIZE_FIXED Rs)
4475 (set tmps (cris-get-mem SI Rs))
4492 ; ADDI Rs.m,Rd,ACR [ Rs | 010101mm | Rd ]
4496 "${Rs-dfield}.m,${Rd-sfield},ACR"
4497 (+ Rd-sfield MODE_REGISTER R_ADDI_ACR Rs-dfield)
4502 (set prefixreg (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size))))
4507 biap-pc "biap.m ${Rs-dfield},PC"
4509 "${Rs-dfield}.m,PC"
4510 (+ Rs-dfield MODE_REGISTER R_ADDI_ACR (f-source 15))
4515 (set prefixreg (add SI (add SI pc 4) (mul Rs-dfield (.sym BWD -size))))
4519 ; FIDXI [Rs] [ 0000 | 11010011 | Rs ]
4521 fidxi "fidxi [Rs]"
4523 "fidxi [$Rs]"
4524 (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_FIDXI SIZE_FIXED Rs)
4525 (set pc (c-call USI "@cpu@_fidxi_handler" pc Rs))
4528 ; FTAGI [Rs] [ 0001 | 11010011 | Rs ]
4530 ftagi "ftagi [Rs]"
4532 "fidxi [$Rs]"
4533 (+ (f-dest 1) MODE_AUTOINCREMENT INFIX_FTAGI SIZE_FIXED Rs)
4534 (set pc (c-call USI "@cpu@_ftagi_handler" pc Rs))
4537 ; FIDXD [Rs] [ 0000 | 10101011 | Rs ]
4539 fidxd "fidxd [Rs]"
4541 "fidxd [$Rs]"
4542 (+ (f-dest 0) MODE_INDIRECT INFIX_FIDXD SIZE_FIXED Rs)
4543 (set pc (c-call USI "@cpu@_fidxd_handler" pc Rs))
4546 ; FTAGD [Rs] [ 0001 | 10101011 | Rs ]
4548 ftagd "ftagd [Rs]"
4550 "ftagd [$Rs]"
4551 (+ (f-dest 1) MODE_INDIRECT INFIX_FTAGD SIZE_FIXED Rs)
4552 (set pc (c-call USI "@cpu@_ftagd_handler" pc Rs))