Lines Matching refs:src1

250 	((src1 INT -1) (src2 INT -1)) ; inputs
257 	((src1 INT -1) (src2 INT -1)) ; inputs
280 	((src1 INT) (src2 INT)) ; inputs
316 	((src1 INT -1) (src2 INT -1)) ; inputs
323 	((src1 INT -1) (src2 INT -1)) ; inputs
344 	((src1 INT) (src2 INT)) ; inputs
369 	((src1 INT -1) (src2 INT -1)) ; inputs
376 	((src1 INT -1) (src2 INT -1)) ; inputs
397 	((src1 INT) (src2 INT)) ; inputs
666 ;; The assembler relies upon the fact that dr and src1 are the same field.
668 (dnop src1   "source register 1"            () h-gr   f-r1)
917      "beq $src1,$src2,$disp16"
918      (+ OP1_11 OP2_0 src1 src2 disp16)
919      (if (eq src1 src2) (set pc disp16))
1051      "bne $src1,$src2,$disp16"
1052      (+ OP1_11 OP2_1 src1 src2 disp16)
1053      (if (ne src1 src2) (set pc disp16))
1131      "cmp $src1,$src2"
1132      (+ OP1_0 OP2_4 src1 src2)
1133      (set condbit (lt src1 src2))
1151      "cmpu $src1,$src2"
1152      (+ OP1_0 OP2_5 src1 src2)
1153      (set condbit (ltu src1 src2))
1171      "cmpeq $src1,$src2"
1172      (+ OP1_0 OP2_6 src1 src2)
1173      (set condbit (eq src1 src2))
1481      "machi $src1,$src2"
1482      (+ OP1_3 OP2_4 src1 src2)
1491 			      (ext DI (and WI src1 (const #xffff0000)))
1500      "machi $src1,$src2,$acc"
1501      (+ OP1_3 src1 acc (f-op23 4) src2)
1508 			      (ext DI (and WI src1 (const #xffff0000)))
1518      "maclo $src1,$src2"
1519      (+ OP1_3 OP2_5 src1 src2)
1526 			      (ext DI (sll WI src1 (const 16)))
1535      "maclo $src1,$src2,$acc"
1536      (+ OP1_3 src1 acc (f-op23 5) src2)
1543 			      (ext DI (sll WI src1 (const 16)))
1553      "macwhi $src1,$src2"
1554      (+ OP1_3 OP2_6 src1 src2)
1561 			      (ext DI src1)
1570      "macwhi $src1,$src2,$acc"
1571      (+ OP1_3 src1 acc (f-op23 6) src2)
1575 	       (mul (ext DI src1)
1583      "macwlo $src1,$src2"
1584      (+ OP1_3 OP2_7 src1 src2)
1591 			      (ext DI src1)
1600      "macwlo $src1,$src2,$acc"
1601      (+ OP1_3 src1 acc (f-op23 7) src2)
1605 	       (mul (ext DI src1)
1623      "mulhi $src1,$src2"
1624      (+ OP1_3 OP2_0 src1 src2)
1629 			 (ext DI (and WI src1 (const #xffff0000)))
1638      "mulhi $src1,$src2,$acc"
1639      (+ OP1_3 (f-op23 0) src1 acc src2)
1644 			 (ext DI (and WI src1 (const #xffff0000)))
1654      "mullo $src1,$src2"
1655      (+ OP1_3 OP2_1 src1 src2)
1660 			 (ext DI (sll WI src1 (const 16)))
1669      "mullo $src1,$src2,$acc"
1670      (+ OP1_3 src1 acc (f-op23 1) src2)
1675 			 (ext DI (sll WI src1 (const 16)))
1685      "mulwhi $src1,$src2"
1686      (+ OP1_3 OP2_2 src1 src2)
1691 			 (ext DI src1)
1700      "mulwhi $src1,$src2,$acc"
1701      (+ OP1_3 src1 acc (f-op23 2) src2)
1704 	  (mul (ext DI src1)
1712      "mulwlo $src1,$src2"
1713      (+ OP1_3 OP2_3 src1 src2)
1718 			 (ext DI src1)
1727      "mulwlo $src1,$src2,$acc"
1728      (+ OP1_3 src1 acc (f-op23 3) src2)
1731 	  (mul (ext DI src1)
1806      "mvtachi $src1"
1807      (+ OP1_5 OP2_7 (f-r2 0) src1)
1811 	      (sll DI (ext DI src1) (const 32))))
1812      ((m32r/d (unit u-exec (in sr src1))))
1817      "mvtachi $src1,$accs"
1818      (+ OP1_5 src1 OP2_7 accs (f-op3 0))
1822 	      (sll DI (ext DI src1) (const 32))))
1823      ((m32rx (unit u-exec (in sr src1)))
1824       (m32r2 (unit u-exec (in sr src1))))
1829      "mvtaclo $src1"
1830      (+ OP1_5 OP2_7 (f-r2 1) src1)
1834 	      (zext DI src1)))
1835      ((m32r/d (unit u-exec (in sr src1))))
1840      "mvtaclo $src1,$accs"
1841      (+ OP1_5 src1 OP2_7 accs (f-op3 1))
1845 	      (zext DI src1)))
1846      ((m32rx (unit u-exec (in sr src1)))
1847       (m32r2 (unit u-exec (in sr src1))))
2049 	 (.str "st" suffix " $src1,@$src2")
2050 	 (+ OP1_2 op2-op src1 src2)
2051 	 (set mode (mem mode src2) src1)
2058 	  (.str "st" suffix " $src1,@($src2)")
2059 	  (emit (.sym st suffix) src1 src2))
2062 	 (.str "st" suffix " $src1,@($slo16,$src2)")
2063 	 (+ OP1_10 op2-op src1 src2 slo16)
2064 	 (set mode (mem mode (add src2 slo16)) src1)
2071 	  (.str "st" suffix " $src1,@($src2,$slo16)")
2072 	  (emit (.sym st suffix -d) src1 src2 slo16))
2081      "st $src1,@+$src2"
2082      (+ OP1_2 OP2_6 src1 src2)
2086 	       (set (mem WI new-src2) src1)
2099      "sth $src1,@$src2+"
2100      (+ OP1_2 OP2_3 src1 src2)
2104 	       (set (mem HI new-src2) src1)
2115      "stb $src1,@$src2+"
2116      (+ OP1_2 OP2_1 src1 src2)
2120 	       (set (mem QI new-src2) src1)
2131      "st $src1,@-$src2"
2132      (+ OP1_2 OP2_7 src1 src2)
2137      ;	       (set (mem WI src2) src1))
2140 	       (set (mem WI new-src2) src1)
2152   "push $src1"
2153   (emit st-minus src1 (src2 15)) ; "st %0,@-sp"
2209      "unlock $src1,@$src2"
2210      (+ OP1_2 OP2_5 src1 src2)
2213 		   (set (mem WI src2) src1))
2293      "macwu1 $src1,$src2"
2294      (+ OP1_5 src1 OP2_11 src2)
2301 				  (ext DI src1)
2312      "msblo $src1,$src2"
2313      (+ OP1_5 src1 OP2_13 src2)
2321 					     (ext DI (trunc HI src1))
2334      "mulwu1 $src1,$src2"
2335      (+ OP1_5 src1 OP2_10 src2)
2340 			    (ext DI src1)
2351      "maclh1 $src1,$src2"
2352      (+ OP1_5 src1 OP2_12 src2)
2361 					    (ext SI (trunc HI src1))