1237               REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)  in bfin_gen_dsp32alu()  argument
1246   ASSIGN_R (dst0);  in bfin_gen_dsp32alu()
1255 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,  in bfin_gen_dsp32shift()  argument
1264   ASSIGN_R (dst0);  in bfin_gen_dsp32shift()
1272 bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag,  in bfin_gen_dsp32shiftimm()  argument
1281   ASSIGN_R (dst0);  in bfin_gen_dsp32shiftimm()
2360   int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);  in decode_dsp32alu_0()  local
2370     return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32alu_0()
2372     return DREGL_MASK (dst0);  in decode_dsp32alu_0()
2374     return DREGH_MASK (dst0);  in decode_dsp32alu_0()
2376     return DREGL_MASK (dst0);  in decode_dsp32alu_0()
2378     return DREGH_MASK (dst0);  in decode_dsp32alu_0()
2391     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2393     return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32alu_0()
2397     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2405     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2417     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2419     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2422     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2424     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2426     return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32alu_0()
2429     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2431     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2434     return DREGL_MASK (dst0);  in decode_dsp32alu_0()
2436     return DREGL_MASK (dst0);  in decode_dsp32alu_0()
2439     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2441     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2444     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2446     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2453     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2456     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2459     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2462     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2464     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2467     return DREG_MASK (dst0);  in decode_dsp32alu_0()
2469     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2471     return DREG_MASK (dst0) | DREG_MASK (dst1);  in decode_dsp32alu_0()
2490   int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);  in decode_dsp32shift_0()  local
2494     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shift_0()
2496     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shift_0()
2498     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shift_0()
2506     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2508     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2510     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2512     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2514     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2516     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2518     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2520     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2522     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2524     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2526     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2528     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2530     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2532     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2534     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2536     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2560     return sop < 2 ? DREGL_MASK (dst0) : DREG_MASK (dst0);  in decode_dsp32shift_0()
2562     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2564     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2566     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2570     return DREGL_MASK (dst0);  in decode_dsp32shift_0()
2572     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2574     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2576     return DREG_MASK (dst0);  in decode_dsp32shift_0()
2591   int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);  in decode_dsp32shiftimm_0()  local
2597     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shiftimm_0()
2599     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shiftimm_0()
2601     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shiftimm_0()
2603     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shiftimm_0()
2605     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);  in decode_dsp32shiftimm_0()
2623     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2625     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2627     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2629     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2631     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2633     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2635     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2637     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2639     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()
2641     return DREG_MASK (dst0);  in decode_dsp32shiftimm_0()