Lines Matching refs:MIPS
6 @node MIPS-Dependent
7 @chapter MIPS Dependent Features
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS FP ABIs:: Marking which FP ABI is in use
32 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
40 @node MIPS Options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
73 @cindex @option{-mvxworks-pic} option, MIPS
77 @cindex MIPS architecture options
93 Generate code for a particular MIPS Instruction Set Architecture level.
100 generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
104 see @ref{MIPS ISA, Directives to override the ISA level}.
118 On some MIPS variants there is a 32-bit mode flag; when this flag is
136 only be used with MIPS II and above.
150 Generate code for the MIPS 16 processor. This is equivalent to putting
171 Generate code for the MIPS-3D Application Specific Extension.
172 This tells the assembler to accept MIPS-3D instructions.
215 Generate code for the MIPS SIMD Architecture Extension.
221 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
294 Generate code for the MIPS R4650 chip. This tells the assembler to accept
303 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
308 Generate code for a particular MIPS CPU. It is exactly equivalent to
407 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
419 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
421 @cindex @code{-nocpp} ignored (MIPS)
475 @cindex @option{-mnan=} command line option, MIPS
478 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
480 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
516 @node MIPS Macros
519 MIPS assemblers have traditionally provided a wider range of
520 instructions than the MIPS architecture itself. These extra
526 Some MIPS macro instructions extend an underlying architectural instruction
542 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
543 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
544 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
554 @cindex @code{at} register, MIPS
576 @node MIPS Symbol Sizes
631 @node MIPS Small Data
636 @cindex small data, MIPS
637 @cindex @code{gp} register, MIPS
648 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
650 In order to cut down on this overhead, most embedded MIPS systems
654 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
687 @node MIPS ISA
690 @cindex MIPS ISA override
693 the MIPS Instruction Set Architecture level on the fly: @code{.set
702 configuration. You can use this feature to permit specific MIPS III
706 @cindex MIPS CPU override
714 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
715 in which it will assemble instructions for the MIPS 16 processor. Use
718 Traditional MIPS assemblers do not support this directive.
724 Traditional MIPS assemblers do not support this directive.
726 @node MIPS assembly options
729 @cindex MIPS directives to override command line options
741 Traditional MIPS assemblers do not support this directive.
743 @cindex MIPS 32-bit microMIPS instruction generation override
752 Traditional MIPS assemblers do not support this directive.
754 @node MIPS autoextend
755 @section Directives for extending MIPS 16 bit instructions
759 By default, MIPS 16 instructions are automatically extended to 32 bits
766 This directive is only meaningful when in MIPS 16 mode. Traditional
767 MIPS assemblers do not support this directive.
769 @node MIPS insn
774 data is actually instructions. This makes a difference in MIPS 16 and
805 @node MIPS FP ABIs
808 * MIPS FP ABI History:: History of FP ABIs
809 * MIPS FP ABI Variants:: Supported FP ABIs
810 * MIPS FP ABI Selection:: Automatic selection of FP ABI
811 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
814 @node MIPS FP ABI History
816 @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS
817 @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS
818 The MIPS ABIs support a variety of different floating-point extensions
829 @node MIPS FP ABI Variants
864 a minimum architecture of MIPS II.
881 @node MIPS FP ABI Selection
883 @cindex @code{.module fp=@var{nn}} directive, MIPS
900 @node MIPS FP ABI Compatibility
914 @node MIPS NaN Encodings
917 @cindex MIPS IEEE 754 NaN data encoding selection
918 @cindex @code{.nan} directive, MIPS
924 signalling NaNs. However, the original MIPS implementation assigned the
929 and as from Sep 2012 the current release of the MIPS architecture
932 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
938 the original MIPS encoding. If several @code{.nan} directives are given,
953 Traditional MIPS assemblers do not support these directives.
955 @node MIPS Option Stack
958 @cindex MIPS option stack
971 Traditional MIPS assemblers do not support these directives.
973 @node MIPS ASE Instruction Generation Overrides
974 @section Directives to control generation of MIPS ASE instructions
976 @cindex MIPS MIPS-3D instruction generation override
980 from the MIPS-3D Application Specific Extension from that point on
981 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
993 @cindex MIPS MDMX instruction generation override
1001 @cindex MIPS DSP Release 1 instruction generation override
1009 @cindex MIPS DSP Release 2 instruction generation override
1018 @cindex MIPS DSP Release 3 instruction generation override
1027 @cindex MIPS MT instruction generation override
1035 @cindex MIPS MCU instruction generation override
1043 @cindex MIPS SIMD Architecture instruction generation override
1047 from the MIPS SIMD Architecture Extension from that point on
1059 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
1066 Traditional MIPS assemblers do not support these directives.
1068 @node MIPS Floating-Point
1089 Traditional MIPS assemblers do not support these directives.
1091 @node MIPS Syntax
1092 @section Syntactical considerations for the MIPS assembler
1094 * MIPS-Chars:: Special Characters
1097 @node MIPS-Chars
1100 @cindex line comment character, MIPS
1101 @cindex MIPS line comment character
1110 @cindex line separator, MIPS
1111 @cindex statement separator, MIPS
1112 @cindex MIPS line separator