Lines Matching refs:I_JX
158 #define I_JX 0x100 /* Jx/Hx instruction */ macro
460 { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } },
461 { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } },
462 { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } },
463 { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } },
464 { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } },
465 { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } },
466 { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } },
467 { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } },
468 { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } },
469 { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } },
470 { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } },
471 { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } },
472 { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } },
473 { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } },
474 { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } },
475 { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } },
477 { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } },
479 { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } },
480 { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } },
481 { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } },
482 { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } },
484 { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } },
485 { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } },
486 { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } },
487 { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } },
488 { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } },
489 { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } },
490 { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } },
491 { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } },
493 { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } },
494 { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } },
495 { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } },
496 { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } },
497 { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } },
498 { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } },
499 { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } },
500 { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } },
501 { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } },
502 { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } },
503 { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } },
504 { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } },
505 { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } },
506 { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } },
507 { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } },
508 { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } },
510 { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } },
511 { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } },
512 { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } },
513 { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } },
514 { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } },
515 { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } },