Lines Matching refs:RL
110 #define RL OP( 0, LIT, 0, 0 ) macro
232 { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } },
233 { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } },
234 { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } },
235 { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } },
236 { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } },
237 { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } },
238 { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } },
239 { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } },
240 { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } },
241 { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } },
242 { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } },
243 { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } },
244 { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } },
245 { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } },
246 { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } },
247 { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } },
248 { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } },
249 { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } },
250 { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } },
251 { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } },
252 { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } },
253 { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } },
254 { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } },
255 { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } },
256 { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } },
257 { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } },
258 { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } },
259 { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } },
260 { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } },
261 { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } },
341 { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } },
352 { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } },
353 { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } },
354 { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } },
355 { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } },
432 { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } },
433 { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } },
434 { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } },
437 { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } },
440 { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } },
454 { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } },
456 { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } },
510 { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } },