Lines Matching refs:SIMM24
305 #define SIMM24 (IMM24+1) macro
310 #define IMM24_MEM (SIMM24+1)
565 { "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
592 { "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
602 { "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
612 { "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
780 { "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
787 { "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
799 { "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
806 { "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
813 { "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
848 { "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
1068 { "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FSM2}},
1069 { "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FSM2}},
1071 { "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEM2 (SIMM24, RM0)}},
1072 { "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEMINC2 (RM0, SIMM24)}},
1074 { "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FDM2}},
1075 { "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FDM2}},
1077 { "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEM2 (SIMM24, RM0)}},
1078 { "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEMINC2 (RM0, SIMM24)}},