Lines Matching refs:XL
2835 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) macro
2838 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
4201 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4431 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4433 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4434 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4437 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4438 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4439 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4441 {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
4442 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4444 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4446 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4448 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4450 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4451 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4453 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4454 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4458 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4460 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4462 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4464 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4465 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4467 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4468 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4470 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4472 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4474 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4476 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4477 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4479 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4480 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
7188 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7189 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7190 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7191 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7192 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7193 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7194 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7198 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7203 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7204 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7209 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7211 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7212 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},