Lines Matching refs:TIC80_OPERAND_GPR

177   { "r0",	TIC80_OPERAND_GPR | 0 },
178   { "r1",	TIC80_OPERAND_GPR | 1 },
179   { "r10",	TIC80_OPERAND_GPR | 10 },
180   { "r11",	TIC80_OPERAND_GPR | 11 },
181   { "r12",	TIC80_OPERAND_GPR | 12 },
182   { "r13",	TIC80_OPERAND_GPR | 13 },
183   { "r14",	TIC80_OPERAND_GPR | 14 },
184   { "r15",	TIC80_OPERAND_GPR | 15 },
185   { "r16",	TIC80_OPERAND_GPR | 16 },
186   { "r17",	TIC80_OPERAND_GPR | 17 },
187   { "r18",	TIC80_OPERAND_GPR | 18 },
188   { "r19",	TIC80_OPERAND_GPR | 19 },
189   { "r2",	TIC80_OPERAND_GPR | 2 },
190   { "r20",	TIC80_OPERAND_GPR | 20 },
191   { "r21",	TIC80_OPERAND_GPR | 21 },
192   { "r22",	TIC80_OPERAND_GPR | 22 },
193   { "r23",	TIC80_OPERAND_GPR | 23 },
194   { "r24",	TIC80_OPERAND_GPR | 24 },
195   { "r25",	TIC80_OPERAND_GPR | 25 },
196   { "r26",	TIC80_OPERAND_GPR | 26 },
197   { "r27",	TIC80_OPERAND_GPR | 27 },
198   { "r28",	TIC80_OPERAND_GPR | 28 },
199   { "r29",	TIC80_OPERAND_GPR | 29 },
200   { "r3",	TIC80_OPERAND_GPR | 3 },
201   { "r30",	TIC80_OPERAND_GPR | 30 },
202   { "r31",	TIC80_OPERAND_GPR | 31 },
203   { "r4",	TIC80_OPERAND_GPR | 4 },
204   { "r5",	TIC80_OPERAND_GPR | 5 },
205   { "r6",	TIC80_OPERAND_GPR | 6 },
206   { "r7",	TIC80_OPERAND_GPR | 7 },
207   { "r8",	TIC80_OPERAND_GPR | 8 },
208   { "r9",	TIC80_OPERAND_GPR | 9 },
385   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
390   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
395   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
400   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
405   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
410   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
469   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
475   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
481   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
486   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },