1 /* Definitions for opcode table for the sparc. 2 Copyright (C) 1989-2016 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 5 the GNU Binutils. 6 7 GAS/GDB is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS/GDB is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS or GDB; see the file COPYING3. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include "ansidecl.h" 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* The SPARC opcode table (and other related data) is defined in 29 the opcodes library in sparc-opc.c. If you change anything here, make 30 sure you fix up that file, and vice versa. */ 31 32 /* FIXME-someday: perhaps the ,a's and such should be embedded in the 33 instruction's name rather than the args. This would make gas faster, pinsn 34 slower, but would mess up some macros a bit. xoxorich. */ 35 36 /* List of instruction sets variations. 37 These values are such that each element is either a superset of a 38 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 39 returns non-zero. 40 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 41 Don't change this without updating sparc-opc.c. */ 42 43 enum sparc_opcode_arch_val 44 { 45 SPARC_OPCODE_ARCH_V6 = 0, 46 SPARC_OPCODE_ARCH_V7, 47 SPARC_OPCODE_ARCH_V8, 48 SPARC_OPCODE_ARCH_LEON, 49 SPARC_OPCODE_ARCH_SPARCLET, 50 SPARC_OPCODE_ARCH_SPARCLITE, 51 /* V9 variants must appear last. */ 52 SPARC_OPCODE_ARCH_V9, 53 SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ 54 SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ 55 SPARC_OPCODE_ARCH_V9C, /* V9 with UA2005 and T1 additions. */ 56 SPARC_OPCODE_ARCH_V9D, /* V9 with UA2007 and T3 additions. */ 57 SPARC_OPCODE_ARCH_V9E, /* V9 with OSA2011 and T4 additions modulus integer multiply-add. */ 58 SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer 59 multiply and Fujitsu fp multiply-add. */ 60 SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */ 61 SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_V9M, 62 SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ 63 }; 64 65 66 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in 67 insn encoding/decoding. */ 68 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 69 70 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 71 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 72 73 /* Table of cpu variants. */ 74 75 typedef struct sparc_opcode_arch 76 { 77 const char *name; 78 /* Mask of sparc_opcode_arch_val's supported. 79 EG: For v7 this would be 80 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 81 These are short's because sparc_opcode.architecture is. */ 82 short supported; 83 } sparc_opcode_arch; 84 85 extern const struct sparc_opcode_arch sparc_opcode_archs[]; 86 87 /* Given architecture name, look up it's sparc_opcode_arch_val value. */ 88 extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); 89 90 /* Return the bitmask of supported architectures for ARCH. */ 91 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 92 93 /* Non-zero if ARCH1 conflicts with ARCH2. 94 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 95 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 96 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 97 != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 98 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 99 != SPARC_OPCODE_SUPPORTED (ARCH2))) 100 101 /* Structure of an opcode table entry. */ 102 103 typedef struct sparc_opcode 104 { 105 const char *name; 106 unsigned long match; /* Bits that must be set. */ 107 unsigned long lose; /* Bits that must not be set. */ 108 const char *args; 109 /* This was called "delayed" in versions before the flags. */ 110 unsigned int flags; 111 unsigned int hwcaps; 112 unsigned int hwcaps2; 113 short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 114 } sparc_opcode; 115 116 /* FIXME: Add F_ANACHRONISTIC flag for v9. */ 117 #define F_DELAYED 0x00000001 /* Delayed branch. */ 118 #define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ 119 #define F_UNBR 0x00000004 /* Unconditional branch. */ 120 #define F_CONDBR 0x00000008 /* Conditional branch. */ 121 #define F_JSR 0x00000010 /* Subroutine call. */ 122 #define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */ 123 #define F_FBR 0x00000040 /* Floating point branch. */ 124 #define F_PREFERRED 0x00000080 /* A preferred alias. */ 125 126 #define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) 127 128 /* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* 129 values precisely. See include/elf/sparc.h. */ 130 #define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ 131 #define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ 132 #define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ 133 #define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ 134 #define HWCAP_POPC 0x00000010 /* 'popc' insn */ 135 #define HWCAP_VIS 0x00000020 /* VIS insns */ 136 #define HWCAP_VIS2 0x00000040 /* VIS2 insns */ 137 #define HWCAP_ASI_BLK_INIT \ 138 0x00000080 /* block init ASIs */ 139 #define HWCAP_FMAF 0x00000100 /* fused multiply-add */ 140 #define HWCAP_VIS3 0x00000400 /* VIS3 insns */ 141 #define HWCAP_HPC 0x00000800 /* HPC insns */ 142 #define HWCAP_RANDOM 0x00001000 /* 'random' insn */ 143 #define HWCAP_TRANS 0x00002000 /* transaction insns */ 144 #define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */ 145 #define HWCAP_IMA 0x00008000 /* integer multiply-add */ 146 #define HWCAP_ASI_CACHE_SPARING \ 147 0x00010000 /* cache sparing ASIs */ 148 #define HWCAP_AES 0x00020000 /* AES crypto insns */ 149 #define HWCAP_DES 0x00040000 /* DES crypto insns */ 150 #define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */ 151 #define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */ 152 #define HWCAP_MD5 0x00200000 /* MD5 hashing insns */ 153 #define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */ 154 #define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */ 155 #define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */ 156 #define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */ 157 #define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ 158 #define HWCAP_PAUSE 0x08000000 /* Pause insn */ 159 #define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ 160 #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ 161 162 #define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ 163 #define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */ 164 #define HWCAP2_ADP 0x00000004 /* Application Data Protection */ 165 #define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ 166 #define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ 167 #define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ 168 #define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ 169 #define HWCAP2_NSEC \ 170 0x00000080 /* pause insn with support for nsec timings */ 171 #define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ 172 #define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ 173 #define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ 174 175 176 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a 177 macro), which is 64 bits. It is handled as a special case. 178 179 The match component is a mask saying which bits must match a particular 180 opcode in order for an instruction to be an instance of that opcode. 181 182 The args component is a string containing one character for each operand of the 183 instruction. 184 185 Kinds of operands: 186 # Number used by optimizer. It is ignored. 187 1 rs1 register. 188 2 rs2 register. 189 d rd register. 190 e frs1 floating point register. 191 v frs1 floating point register (double/even). 192 V frs1 floating point register (quad/multiple of 4). 193 f frs2 floating point register. 194 B frs2 floating point register (double/even). 195 R frs2 floating point register (quad/multiple of 4). 196 4 frs3 floating point register. 197 5 frs3 floating point register (doube/even). 198 g frsd floating point register. 199 H frsd floating point register (double/even). 200 J frsd floating point register (quad/multiple of 4). 201 } frsd floating point register (double/even) that is == frs2 202 b crs1 coprocessor register 203 c crs2 coprocessor register 204 D crsd coprocessor register 205 m alternate space register (asr) in rd 206 M alternate space register (asr) in rs1 207 h 22 high bits. 208 X 5 bit unsigned immediate 209 Y 6 bit unsigned immediate 210 3 SIAM mode (3 bits). (v9b) 211 K MEMBAR mask (7 bits). (v9) 212 j 10 bit Immediate. (v9) 213 I 11 bit Immediate. (v9) 214 i 13 bit Immediate. 215 n 22 bit immediate. 216 k 2+14 bit PC relative immediate. (v9) 217 G 19 bit PC relative immediate. (v9) 218 l 22 bit PC relative immediate. 219 L 30 bit PC relative immediate. 220 a Annul. The annul bit is set. 221 A Alternate address space. Stored as 8 bits. 222 C Coprocessor state register. 223 F floating point state register. 224 p Processor state register. 225 N Branch predict clear ",pn" (v9) 226 T Branch predict set ",pt" (v9) 227 z %icc. (v9) 228 Z %xcc. (v9) 229 q Floating point queue. 230 r Single register that is both rs1 and rd. 231 O Single register that is both rs2 and rd. 232 Q Coprocessor queue. 233 S Special case. 234 t Trap base register. 235 w Window invalid mask register. 236 y Y register. 237 u sparclet coprocessor registers in rd position 238 U sparclet coprocessor registers in rs1 position 239 E %ccr. (v9) 240 s %fprs. (v9) 241 P %pc. (v9) 242 W %tick. (v9) 243 { %mcdper. (v9b) 244 o %asi. (v9) 245 6 %fcc0. (v9) 246 7 %fcc1. (v9) 247 8 %fcc2. (v9) 248 9 %fcc3. (v9) 249 ! Privileged Register in rd (v9) 250 ? Privileged Register in rs1 (v9) 251 % Hyperprivileged Register in rd (v9b) 252 $ Hyperprivileged Register in rs1 (v9b) 253 * Prefetch function constant. (v9) 254 x OPF field (v9 impdep). 255 0 32/64 bit immediate for set or setx (v9) insns 256 _ Ancillary state register in rd (v9a) 257 / Ancillary state register in rs1 (v9a) 258 ( entire floating point state register (%efsr) 259 ) 5 bit immediate placed in RS3 field 260 = 2+8 bit PC relative immediate. (v9) */ 261 262 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 263 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ 264 #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ 265 #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ 266 #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ 267 #define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ 268 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ 269 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z)) 270 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ 271 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ 272 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ 273 #define F1(x) (OP (x)) 274 #define DISP30(x) ((x) & 0x3fffffff) 275 #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ 276 #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ 277 #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ 278 #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ 279 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ 280 #define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */ 281 #define ASI_RS2(x) (SIMM13 (x)) 282 #define MEMBAR(x) ((x) & 0x7f) 283 #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ 284 285 #define ANNUL (1 << 29) 286 #define BPRED (1 << 19) /* V9. */ 287 #define IMMED F3I (1) 288 #define RD_G0 RD (~0) 289 #define RS1_G0 RS1 (~0) 290 #define RS2_G0 RS2 (~0) 291 292 extern const struct sparc_opcode sparc_opcodes[]; 293 extern const int sparc_num_opcodes; 294 295 extern int sparc_encode_asi (const char *); 296 extern const char *sparc_decode_asi (int); 297 extern int sparc_encode_membar (const char *); 298 extern const char *sparc_decode_membar (int); 299 extern int sparc_encode_prefetch (const char *); 300 extern const char *sparc_decode_prefetch (int); 301 extern int sparc_encode_sparclet_cpreg (const char *); 302 extern const char *sparc_decode_sparclet_cpreg (int); 303 304 /* Local Variables: 305 fill-column: 131 306 comment-column: 0 307 End: */ 308 309 #ifdef __cplusplus 310 } 311 #endif 312