1 /*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "assembler_mips.h"
18
19 #include <map>
20
21 #include "base/stl_util.h"
22 #include "utils/assembler_test.h"
23
24 #define __ GetAssembler()->
25
26 namespace art {
27
28 struct MIPSCpuRegisterCompare {
operator ()art::MIPSCpuRegisterCompare29 bool operator()(const mips::Register& a, const mips::Register& b) const {
30 return a < b;
31 }
32 };
33
34 class AssemblerMIPSTest : public AssemblerTest<mips::MipsAssembler,
35 mips::MipsLabel,
36 mips::Register,
37 mips::FRegister,
38 uint32_t> {
39 public:
40 typedef AssemblerTest<mips::MipsAssembler,
41 mips::MipsLabel,
42 mips::Register,
43 mips::FRegister,
44 uint32_t> Base;
45
46 protected:
47 // Get the typically used name for this architecture, e.g., aarch64, x86-64, ...
GetArchitectureString()48 std::string GetArchitectureString() OVERRIDE {
49 return "mips";
50 }
51
GetAssemblerParameters()52 std::string GetAssemblerParameters() OVERRIDE {
53 return " --no-warn -32 -march=mips32r2";
54 }
55
GetDisassembleParameters()56 std::string GetDisassembleParameters() OVERRIDE {
57 return " -D -bbinary -mmips:isa32r2";
58 }
59
SetUpHelpers()60 void SetUpHelpers() OVERRIDE {
61 if (registers_.size() == 0) {
62 registers_.push_back(new mips::Register(mips::ZERO));
63 registers_.push_back(new mips::Register(mips::AT));
64 registers_.push_back(new mips::Register(mips::V0));
65 registers_.push_back(new mips::Register(mips::V1));
66 registers_.push_back(new mips::Register(mips::A0));
67 registers_.push_back(new mips::Register(mips::A1));
68 registers_.push_back(new mips::Register(mips::A2));
69 registers_.push_back(new mips::Register(mips::A3));
70 registers_.push_back(new mips::Register(mips::T0));
71 registers_.push_back(new mips::Register(mips::T1));
72 registers_.push_back(new mips::Register(mips::T2));
73 registers_.push_back(new mips::Register(mips::T3));
74 registers_.push_back(new mips::Register(mips::T4));
75 registers_.push_back(new mips::Register(mips::T5));
76 registers_.push_back(new mips::Register(mips::T6));
77 registers_.push_back(new mips::Register(mips::T7));
78 registers_.push_back(new mips::Register(mips::S0));
79 registers_.push_back(new mips::Register(mips::S1));
80 registers_.push_back(new mips::Register(mips::S2));
81 registers_.push_back(new mips::Register(mips::S3));
82 registers_.push_back(new mips::Register(mips::S4));
83 registers_.push_back(new mips::Register(mips::S5));
84 registers_.push_back(new mips::Register(mips::S6));
85 registers_.push_back(new mips::Register(mips::S7));
86 registers_.push_back(new mips::Register(mips::T8));
87 registers_.push_back(new mips::Register(mips::T9));
88 registers_.push_back(new mips::Register(mips::K0));
89 registers_.push_back(new mips::Register(mips::K1));
90 registers_.push_back(new mips::Register(mips::GP));
91 registers_.push_back(new mips::Register(mips::SP));
92 registers_.push_back(new mips::Register(mips::FP));
93 registers_.push_back(new mips::Register(mips::RA));
94
95 secondary_register_names_.emplace(mips::Register(mips::ZERO), "zero");
96 secondary_register_names_.emplace(mips::Register(mips::AT), "at");
97 secondary_register_names_.emplace(mips::Register(mips::V0), "v0");
98 secondary_register_names_.emplace(mips::Register(mips::V1), "v1");
99 secondary_register_names_.emplace(mips::Register(mips::A0), "a0");
100 secondary_register_names_.emplace(mips::Register(mips::A1), "a1");
101 secondary_register_names_.emplace(mips::Register(mips::A2), "a2");
102 secondary_register_names_.emplace(mips::Register(mips::A3), "a3");
103 secondary_register_names_.emplace(mips::Register(mips::T0), "t0");
104 secondary_register_names_.emplace(mips::Register(mips::T1), "t1");
105 secondary_register_names_.emplace(mips::Register(mips::T2), "t2");
106 secondary_register_names_.emplace(mips::Register(mips::T3), "t3");
107 secondary_register_names_.emplace(mips::Register(mips::T4), "t4");
108 secondary_register_names_.emplace(mips::Register(mips::T5), "t5");
109 secondary_register_names_.emplace(mips::Register(mips::T6), "t6");
110 secondary_register_names_.emplace(mips::Register(mips::T7), "t7");
111 secondary_register_names_.emplace(mips::Register(mips::S0), "s0");
112 secondary_register_names_.emplace(mips::Register(mips::S1), "s1");
113 secondary_register_names_.emplace(mips::Register(mips::S2), "s2");
114 secondary_register_names_.emplace(mips::Register(mips::S3), "s3");
115 secondary_register_names_.emplace(mips::Register(mips::S4), "s4");
116 secondary_register_names_.emplace(mips::Register(mips::S5), "s5");
117 secondary_register_names_.emplace(mips::Register(mips::S6), "s6");
118 secondary_register_names_.emplace(mips::Register(mips::S7), "s7");
119 secondary_register_names_.emplace(mips::Register(mips::T8), "t8");
120 secondary_register_names_.emplace(mips::Register(mips::T9), "t9");
121 secondary_register_names_.emplace(mips::Register(mips::K0), "k0");
122 secondary_register_names_.emplace(mips::Register(mips::K1), "k1");
123 secondary_register_names_.emplace(mips::Register(mips::GP), "gp");
124 secondary_register_names_.emplace(mips::Register(mips::SP), "sp");
125 secondary_register_names_.emplace(mips::Register(mips::FP), "fp");
126 secondary_register_names_.emplace(mips::Register(mips::RA), "ra");
127
128 fp_registers_.push_back(new mips::FRegister(mips::F0));
129 fp_registers_.push_back(new mips::FRegister(mips::F1));
130 fp_registers_.push_back(new mips::FRegister(mips::F2));
131 fp_registers_.push_back(new mips::FRegister(mips::F3));
132 fp_registers_.push_back(new mips::FRegister(mips::F4));
133 fp_registers_.push_back(new mips::FRegister(mips::F5));
134 fp_registers_.push_back(new mips::FRegister(mips::F6));
135 fp_registers_.push_back(new mips::FRegister(mips::F7));
136 fp_registers_.push_back(new mips::FRegister(mips::F8));
137 fp_registers_.push_back(new mips::FRegister(mips::F9));
138 fp_registers_.push_back(new mips::FRegister(mips::F10));
139 fp_registers_.push_back(new mips::FRegister(mips::F11));
140 fp_registers_.push_back(new mips::FRegister(mips::F12));
141 fp_registers_.push_back(new mips::FRegister(mips::F13));
142 fp_registers_.push_back(new mips::FRegister(mips::F14));
143 fp_registers_.push_back(new mips::FRegister(mips::F15));
144 fp_registers_.push_back(new mips::FRegister(mips::F16));
145 fp_registers_.push_back(new mips::FRegister(mips::F17));
146 fp_registers_.push_back(new mips::FRegister(mips::F18));
147 fp_registers_.push_back(new mips::FRegister(mips::F19));
148 fp_registers_.push_back(new mips::FRegister(mips::F20));
149 fp_registers_.push_back(new mips::FRegister(mips::F21));
150 fp_registers_.push_back(new mips::FRegister(mips::F22));
151 fp_registers_.push_back(new mips::FRegister(mips::F23));
152 fp_registers_.push_back(new mips::FRegister(mips::F24));
153 fp_registers_.push_back(new mips::FRegister(mips::F25));
154 fp_registers_.push_back(new mips::FRegister(mips::F26));
155 fp_registers_.push_back(new mips::FRegister(mips::F27));
156 fp_registers_.push_back(new mips::FRegister(mips::F28));
157 fp_registers_.push_back(new mips::FRegister(mips::F29));
158 fp_registers_.push_back(new mips::FRegister(mips::F30));
159 fp_registers_.push_back(new mips::FRegister(mips::F31));
160 }
161 }
162
TearDown()163 void TearDown() OVERRIDE {
164 AssemblerTest::TearDown();
165 STLDeleteElements(®isters_);
166 STLDeleteElements(&fp_registers_);
167 }
168
GetAddresses()169 std::vector<mips::MipsLabel> GetAddresses() {
170 UNIMPLEMENTED(FATAL) << "Feature not implemented yet";
171 UNREACHABLE();
172 }
173
GetRegisters()174 std::vector<mips::Register*> GetRegisters() OVERRIDE {
175 return registers_;
176 }
177
GetFPRegisters()178 std::vector<mips::FRegister*> GetFPRegisters() OVERRIDE {
179 return fp_registers_;
180 }
181
CreateImmediate(int64_t imm_value)182 uint32_t CreateImmediate(int64_t imm_value) OVERRIDE {
183 return imm_value;
184 }
185
GetSecondaryRegisterName(const mips::Register & reg)186 std::string GetSecondaryRegisterName(const mips::Register& reg) OVERRIDE {
187 CHECK(secondary_register_names_.find(reg) != secondary_register_names_.end());
188 return secondary_register_names_[reg];
189 }
190
RepeatInsn(size_t count,const std::string & insn)191 std::string RepeatInsn(size_t count, const std::string& insn) {
192 std::string result;
193 for (; count != 0u; --count) {
194 result += insn;
195 }
196 return result;
197 }
198
BranchHelper(void (mips::MipsAssembler::* f)(mips::MipsLabel *,bool),const std::string & instr_name,bool is_bare=false)199 void BranchHelper(void (mips::MipsAssembler::*f)(mips::MipsLabel*,
200 bool),
201 const std::string& instr_name,
202 bool is_bare = false) {
203 __ SetReorder(false);
204 mips::MipsLabel label1, label2;
205 (Base::GetAssembler()->*f)(&label1, is_bare);
206 constexpr size_t kAdduCount1 = 63;
207 for (size_t i = 0; i != kAdduCount1; ++i) {
208 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
209 }
210 __ Bind(&label1);
211 (Base::GetAssembler()->*f)(&label2, is_bare);
212 constexpr size_t kAdduCount2 = 64;
213 for (size_t i = 0; i != kAdduCount2; ++i) {
214 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
215 }
216 __ Bind(&label2);
217 (Base::GetAssembler()->*f)(&label1, is_bare);
218 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
219
220 std::string expected =
221 ".set noreorder\n" +
222 instr_name + " 1f\n" +
223 (is_bare ? "" : "nop\n") +
224 RepeatInsn(kAdduCount1, "addu $zero, $zero, $zero\n") +
225 "1:\n" +
226 instr_name + " 2f\n" +
227 (is_bare ? "" : "nop\n") +
228 RepeatInsn(kAdduCount2, "addu $zero, $zero, $zero\n") +
229 "2:\n" +
230 instr_name + " 1b\n" +
231 (is_bare ? "" : "nop\n") +
232 "addu $zero, $zero, $zero\n";
233 DriverStr(expected, instr_name);
234 }
235
BranchCondOneRegHelper(void (mips::MipsAssembler::* f)(mips::Register,mips::MipsLabel *,bool),const std::string & instr_name,bool is_bare=false)236 void BranchCondOneRegHelper(void (mips::MipsAssembler::*f)(mips::Register,
237 mips::MipsLabel*,
238 bool),
239 const std::string& instr_name,
240 bool is_bare = false) {
241 __ SetReorder(false);
242 mips::MipsLabel label;
243 (Base::GetAssembler()->*f)(mips::A0, &label, is_bare);
244 constexpr size_t kAdduCount1 = 63;
245 for (size_t i = 0; i != kAdduCount1; ++i) {
246 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
247 }
248 __ Bind(&label);
249 constexpr size_t kAdduCount2 = 64;
250 for (size_t i = 0; i != kAdduCount2; ++i) {
251 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
252 }
253 (Base::GetAssembler()->*f)(mips::A1, &label, is_bare);
254 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
255
256 std::string expected =
257 ".set noreorder\n" +
258 instr_name + " $a0, 1f\n" +
259 (is_bare ? "" : "nop\n") +
260 RepeatInsn(kAdduCount1, "addu $zero, $zero, $zero\n") +
261 "1:\n" +
262 RepeatInsn(kAdduCount2, "addu $zero, $zero, $zero\n") +
263 instr_name + " $a1, 1b\n" +
264 (is_bare ? "" : "nop\n") +
265 "addu $zero, $zero, $zero\n";
266 DriverStr(expected, instr_name);
267 }
268
BranchCondTwoRegsHelper(void (mips::MipsAssembler::* f)(mips::Register,mips::Register,mips::MipsLabel *,bool),const std::string & instr_name,bool is_bare=false)269 void BranchCondTwoRegsHelper(void (mips::MipsAssembler::*f)(mips::Register,
270 mips::Register,
271 mips::MipsLabel*,
272 bool),
273 const std::string& instr_name,
274 bool is_bare = false) {
275 __ SetReorder(false);
276 mips::MipsLabel label;
277 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label, is_bare);
278 constexpr size_t kAdduCount1 = 63;
279 for (size_t i = 0; i != kAdduCount1; ++i) {
280 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
281 }
282 __ Bind(&label);
283 constexpr size_t kAdduCount2 = 64;
284 for (size_t i = 0; i != kAdduCount2; ++i) {
285 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
286 }
287 (Base::GetAssembler()->*f)(mips::A2, mips::A3, &label, is_bare);
288 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
289
290 std::string expected =
291 ".set noreorder\n" +
292 instr_name + " $a0, $a1, 1f\n" +
293 (is_bare ? "" : "nop\n") +
294 RepeatInsn(kAdduCount1, "addu $zero, $zero, $zero\n") +
295 "1:\n" +
296 RepeatInsn(kAdduCount2, "addu $zero, $zero, $zero\n") +
297 instr_name + " $a2, $a3, 1b\n" +
298 (is_bare ? "" : "nop\n") +
299 "addu $zero, $zero, $zero\n";
300 DriverStr(expected, instr_name);
301 }
302
BranchFpuCondCodeHelper(void (mips::MipsAssembler::* f)(int,mips::MipsLabel *,bool),const std::string & instr_name,bool is_bare=false)303 void BranchFpuCondCodeHelper(void (mips::MipsAssembler::*f)(int,
304 mips::MipsLabel*,
305 bool),
306 const std::string& instr_name,
307 bool is_bare = false) {
308 __ SetReorder(false);
309 mips::MipsLabel label;
310 (Base::GetAssembler()->*f)(0, &label, is_bare);
311 constexpr size_t kAdduCount1 = 63;
312 for (size_t i = 0; i != kAdduCount1; ++i) {
313 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
314 }
315 __ Bind(&label);
316 constexpr size_t kAdduCount2 = 64;
317 for (size_t i = 0; i != kAdduCount2; ++i) {
318 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
319 }
320 (Base::GetAssembler()->*f)(7, &label, is_bare);
321 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
322
323 std::string expected =
324 ".set noreorder\n" +
325 instr_name + " $fcc0, 1f\n" +
326 (is_bare ? "" : "nop\n") +
327 RepeatInsn(kAdduCount1, "addu $zero, $zero, $zero\n") +
328 "1:\n" +
329 RepeatInsn(kAdduCount2, "addu $zero, $zero, $zero\n") +
330 instr_name + " $fcc7, 1b\n" +
331 (is_bare ? "" : "nop\n") +
332 "addu $zero, $zero, $zero\n";
333 DriverStr(expected, instr_name);
334 }
335
336 private:
337 std::vector<mips::Register*> registers_;
338 std::map<mips::Register, std::string, MIPSCpuRegisterCompare> secondary_register_names_;
339
340 std::vector<mips::FRegister*> fp_registers_;
341 };
342
343
TEST_F(AssemblerMIPSTest,Toolchain)344 TEST_F(AssemblerMIPSTest, Toolchain) {
345 EXPECT_TRUE(CheckTools());
346 }
347
TEST_F(AssemblerMIPSTest,Addu)348 TEST_F(AssemblerMIPSTest, Addu) {
349 DriverStr(RepeatRRR(&mips::MipsAssembler::Addu, "addu ${reg1}, ${reg2}, ${reg3}"), "Addu");
350 }
351
TEST_F(AssemblerMIPSTest,Addiu)352 TEST_F(AssemblerMIPSTest, Addiu) {
353 DriverStr(RepeatRRIb(&mips::MipsAssembler::Addiu, -16, "addiu ${reg1}, ${reg2}, {imm}"), "Addiu");
354 }
355
TEST_F(AssemblerMIPSTest,Subu)356 TEST_F(AssemblerMIPSTest, Subu) {
357 DriverStr(RepeatRRR(&mips::MipsAssembler::Subu, "subu ${reg1}, ${reg2}, ${reg3}"), "Subu");
358 }
359
TEST_F(AssemblerMIPSTest,MultR2)360 TEST_F(AssemblerMIPSTest, MultR2) {
361 DriverStr(RepeatRR(&mips::MipsAssembler::MultR2, "mult ${reg1}, ${reg2}"), "MultR2");
362 }
363
TEST_F(AssemblerMIPSTest,MultuR2)364 TEST_F(AssemblerMIPSTest, MultuR2) {
365 DriverStr(RepeatRR(&mips::MipsAssembler::MultuR2, "multu ${reg1}, ${reg2}"), "MultuR2");
366 }
367
TEST_F(AssemblerMIPSTest,DivR2Basic)368 TEST_F(AssemblerMIPSTest, DivR2Basic) {
369 DriverStr(RepeatRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg1}, ${reg2}"), "DivR2Basic");
370 }
371
TEST_F(AssemblerMIPSTest,DivuR2Basic)372 TEST_F(AssemblerMIPSTest, DivuR2Basic) {
373 DriverStr(RepeatRR(&mips::MipsAssembler::DivuR2, "divu $zero, ${reg1}, ${reg2}"), "DivuR2Basic");
374 }
375
TEST_F(AssemblerMIPSTest,MulR2)376 TEST_F(AssemblerMIPSTest, MulR2) {
377 DriverStr(RepeatRRR(&mips::MipsAssembler::MulR2, "mul ${reg1}, ${reg2}, ${reg3}"), "MulR2");
378 }
379
TEST_F(AssemblerMIPSTest,DivR2)380 TEST_F(AssemblerMIPSTest, DivR2) {
381 DriverStr(RepeatRRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg2}, ${reg3}\nmflo ${reg1}"),
382 "DivR2");
383 }
384
TEST_F(AssemblerMIPSTest,ModR2)385 TEST_F(AssemblerMIPSTest, ModR2) {
386 DriverStr(RepeatRRR(&mips::MipsAssembler::ModR2, "div $zero, ${reg2}, ${reg3}\nmfhi ${reg1}"),
387 "ModR2");
388 }
389
TEST_F(AssemblerMIPSTest,DivuR2)390 TEST_F(AssemblerMIPSTest, DivuR2) {
391 DriverStr(RepeatRRR(&mips::MipsAssembler::DivuR2, "divu $zero, ${reg2}, ${reg3}\nmflo ${reg1}"),
392 "DivuR2");
393 }
394
TEST_F(AssemblerMIPSTest,ModuR2)395 TEST_F(AssemblerMIPSTest, ModuR2) {
396 DriverStr(RepeatRRR(&mips::MipsAssembler::ModuR2, "divu $zero, ${reg2}, ${reg3}\nmfhi ${reg1}"),
397 "ModuR2");
398 }
399
TEST_F(AssemblerMIPSTest,And)400 TEST_F(AssemblerMIPSTest, And) {
401 DriverStr(RepeatRRR(&mips::MipsAssembler::And, "and ${reg1}, ${reg2}, ${reg3}"), "And");
402 }
403
TEST_F(AssemblerMIPSTest,Andi)404 TEST_F(AssemblerMIPSTest, Andi) {
405 DriverStr(RepeatRRIb(&mips::MipsAssembler::Andi, 16, "andi ${reg1}, ${reg2}, {imm}"), "Andi");
406 }
407
TEST_F(AssemblerMIPSTest,Or)408 TEST_F(AssemblerMIPSTest, Or) {
409 DriverStr(RepeatRRR(&mips::MipsAssembler::Or, "or ${reg1}, ${reg2}, ${reg3}"), "Or");
410 }
411
TEST_F(AssemblerMIPSTest,Ori)412 TEST_F(AssemblerMIPSTest, Ori) {
413 DriverStr(RepeatRRIb(&mips::MipsAssembler::Ori, 16, "ori ${reg1}, ${reg2}, {imm}"), "Ori");
414 }
415
TEST_F(AssemblerMIPSTest,Xor)416 TEST_F(AssemblerMIPSTest, Xor) {
417 DriverStr(RepeatRRR(&mips::MipsAssembler::Xor, "xor ${reg1}, ${reg2}, ${reg3}"), "Xor");
418 }
419
TEST_F(AssemblerMIPSTest,Xori)420 TEST_F(AssemblerMIPSTest, Xori) {
421 DriverStr(RepeatRRIb(&mips::MipsAssembler::Xori, 16, "xori ${reg1}, ${reg2}, {imm}"), "Xori");
422 }
423
TEST_F(AssemblerMIPSTest,Nor)424 TEST_F(AssemblerMIPSTest, Nor) {
425 DriverStr(RepeatRRR(&mips::MipsAssembler::Nor, "nor ${reg1}, ${reg2}, ${reg3}"), "Nor");
426 }
427
428 //////////
429 // MISC //
430 //////////
431
TEST_F(AssemblerMIPSTest,Movz)432 TEST_F(AssemblerMIPSTest, Movz) {
433 DriverStr(RepeatRRR(&mips::MipsAssembler::Movz, "movz ${reg1}, ${reg2}, ${reg3}"), "Movz");
434 }
435
TEST_F(AssemblerMIPSTest,Movn)436 TEST_F(AssemblerMIPSTest, Movn) {
437 DriverStr(RepeatRRR(&mips::MipsAssembler::Movn, "movn ${reg1}, ${reg2}, ${reg3}"), "Movn");
438 }
439
TEST_F(AssemblerMIPSTest,Seb)440 TEST_F(AssemblerMIPSTest, Seb) {
441 DriverStr(RepeatRR(&mips::MipsAssembler::Seb, "seb ${reg1}, ${reg2}"), "Seb");
442 }
443
TEST_F(AssemblerMIPSTest,Seh)444 TEST_F(AssemblerMIPSTest, Seh) {
445 DriverStr(RepeatRR(&mips::MipsAssembler::Seh, "seh ${reg1}, ${reg2}"), "Seh");
446 }
447
TEST_F(AssemblerMIPSTest,Sll)448 TEST_F(AssemblerMIPSTest, Sll) {
449 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sll, 5, "sll ${reg1}, ${reg2}, {imm}"), "Sll");
450 }
451
TEST_F(AssemblerMIPSTest,Srl)452 TEST_F(AssemblerMIPSTest, Srl) {
453 DriverStr(RepeatRRIb(&mips::MipsAssembler::Srl, 5, "srl ${reg1}, ${reg2}, {imm}"), "Srl");
454 }
455
TEST_F(AssemblerMIPSTest,Sra)456 TEST_F(AssemblerMIPSTest, Sra) {
457 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sra, 5, "sra ${reg1}, ${reg2}, {imm}"), "Sra");
458 }
459
TEST_F(AssemblerMIPSTest,Sllv)460 TEST_F(AssemblerMIPSTest, Sllv) {
461 DriverStr(RepeatRRR(&mips::MipsAssembler::Sllv, "sllv ${reg1}, ${reg2}, ${reg3}"), "Sllv");
462 }
463
TEST_F(AssemblerMIPSTest,Srlv)464 TEST_F(AssemblerMIPSTest, Srlv) {
465 DriverStr(RepeatRRR(&mips::MipsAssembler::Srlv, "srlv ${reg1}, ${reg2}, ${reg3}"), "Srlv");
466 }
467
TEST_F(AssemblerMIPSTest,Rotrv)468 TEST_F(AssemblerMIPSTest, Rotrv) {
469 DriverStr(RepeatRRR(&mips::MipsAssembler::Rotrv, "rotrv ${reg1}, ${reg2}, ${reg3}"), "rotrv");
470 }
471
TEST_F(AssemblerMIPSTest,Srav)472 TEST_F(AssemblerMIPSTest, Srav) {
473 DriverStr(RepeatRRR(&mips::MipsAssembler::Srav, "srav ${reg1}, ${reg2}, ${reg3}"), "Srav");
474 }
475
TEST_F(AssemblerMIPSTest,Ins)476 TEST_F(AssemblerMIPSTest, Ins) {
477 std::vector<mips::Register*> regs = GetRegisters();
478 WarnOnCombinations(regs.size() * regs.size() * 33 * 16);
479 std::string expected;
480 for (mips::Register* reg1 : regs) {
481 for (mips::Register* reg2 : regs) {
482 for (int32_t pos = 0; pos < 32; pos++) {
483 for (int32_t size = 1; pos + size <= 32; size++) {
484 __ Ins(*reg1, *reg2, pos, size);
485 std::ostringstream instr;
486 instr << "ins $" << *reg1 << ", $" << *reg2 << ", " << pos << ", " << size << "\n";
487 expected += instr.str();
488 }
489 }
490 }
491 }
492 DriverStr(expected, "Ins");
493 }
494
TEST_F(AssemblerMIPSTest,Ext)495 TEST_F(AssemblerMIPSTest, Ext) {
496 std::vector<mips::Register*> regs = GetRegisters();
497 WarnOnCombinations(regs.size() * regs.size() * 33 * 16);
498 std::string expected;
499 for (mips::Register* reg1 : regs) {
500 for (mips::Register* reg2 : regs) {
501 for (int32_t pos = 0; pos < 32; pos++) {
502 for (int32_t size = 1; pos + size <= 32; size++) {
503 __ Ext(*reg1, *reg2, pos, size);
504 std::ostringstream instr;
505 instr << "ext $" << *reg1 << ", $" << *reg2 << ", " << pos << ", " << size << "\n";
506 expected += instr.str();
507 }
508 }
509 }
510 }
511 DriverStr(expected, "Ext");
512 }
513
TEST_F(AssemblerMIPSTest,ClzR2)514 TEST_F(AssemblerMIPSTest, ClzR2) {
515 DriverStr(RepeatRR(&mips::MipsAssembler::ClzR2, "clz ${reg1}, ${reg2}"), "clzR2");
516 }
517
TEST_F(AssemblerMIPSTest,CloR2)518 TEST_F(AssemblerMIPSTest, CloR2) {
519 DriverStr(RepeatRR(&mips::MipsAssembler::CloR2, "clo ${reg1}, ${reg2}"), "cloR2");
520 }
521
TEST_F(AssemblerMIPSTest,Lb)522 TEST_F(AssemblerMIPSTest, Lb) {
523 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lb, -16, "lb ${reg1}, {imm}(${reg2})"), "Lb");
524 }
525
TEST_F(AssemblerMIPSTest,Lh)526 TEST_F(AssemblerMIPSTest, Lh) {
527 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lh, -16, "lh ${reg1}, {imm}(${reg2})"), "Lh");
528 }
529
TEST_F(AssemblerMIPSTest,Lwl)530 TEST_F(AssemblerMIPSTest, Lwl) {
531 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lwl, -16, "lwl ${reg1}, {imm}(${reg2})"), "Lwl");
532 }
533
TEST_F(AssemblerMIPSTest,Lw)534 TEST_F(AssemblerMIPSTest, Lw) {
535 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lw, -16, "lw ${reg1}, {imm}(${reg2})"), "Lw");
536 }
537
TEST_F(AssemblerMIPSTest,Lwr)538 TEST_F(AssemblerMIPSTest, Lwr) {
539 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lwr, -16, "lwr ${reg1}, {imm}(${reg2})"), "Lwr");
540 }
541
TEST_F(AssemblerMIPSTest,Lbu)542 TEST_F(AssemblerMIPSTest, Lbu) {
543 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lbu, -16, "lbu ${reg1}, {imm}(${reg2})"), "Lbu");
544 }
545
TEST_F(AssemblerMIPSTest,Lhu)546 TEST_F(AssemblerMIPSTest, Lhu) {
547 DriverStr(RepeatRRIb(&mips::MipsAssembler::Lhu, -16, "lhu ${reg1}, {imm}(${reg2})"), "Lhu");
548 }
549
TEST_F(AssemblerMIPSTest,Lui)550 TEST_F(AssemblerMIPSTest, Lui) {
551 DriverStr(RepeatRIb(&mips::MipsAssembler::Lui, 16, "lui ${reg}, {imm}"), "Lui");
552 }
553
TEST_F(AssemblerMIPSTest,Mfhi)554 TEST_F(AssemblerMIPSTest, Mfhi) {
555 DriverStr(RepeatR(&mips::MipsAssembler::Mfhi, "mfhi ${reg}"), "Mfhi");
556 }
557
TEST_F(AssemblerMIPSTest,Mflo)558 TEST_F(AssemblerMIPSTest, Mflo) {
559 DriverStr(RepeatR(&mips::MipsAssembler::Mflo, "mflo ${reg}"), "Mflo");
560 }
561
TEST_F(AssemblerMIPSTest,Sb)562 TEST_F(AssemblerMIPSTest, Sb) {
563 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sb, -16, "sb ${reg1}, {imm}(${reg2})"), "Sb");
564 }
565
TEST_F(AssemblerMIPSTest,Sh)566 TEST_F(AssemblerMIPSTest, Sh) {
567 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sh, -16, "sh ${reg1}, {imm}(${reg2})"), "Sh");
568 }
569
TEST_F(AssemblerMIPSTest,Swl)570 TEST_F(AssemblerMIPSTest, Swl) {
571 DriverStr(RepeatRRIb(&mips::MipsAssembler::Swl, -16, "swl ${reg1}, {imm}(${reg2})"), "Swl");
572 }
573
TEST_F(AssemblerMIPSTest,Sw)574 TEST_F(AssemblerMIPSTest, Sw) {
575 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sw, -16, "sw ${reg1}, {imm}(${reg2})"), "Sw");
576 }
577
TEST_F(AssemblerMIPSTest,Swr)578 TEST_F(AssemblerMIPSTest, Swr) {
579 DriverStr(RepeatRRIb(&mips::MipsAssembler::Swr, -16, "swr ${reg1}, {imm}(${reg2})"), "Swr");
580 }
581
TEST_F(AssemblerMIPSTest,LlR2)582 TEST_F(AssemblerMIPSTest, LlR2) {
583 DriverStr(RepeatRRIb(&mips::MipsAssembler::LlR2, -16, "ll ${reg1}, {imm}(${reg2})"), "LlR2");
584 }
585
TEST_F(AssemblerMIPSTest,ScR2)586 TEST_F(AssemblerMIPSTest, ScR2) {
587 DriverStr(RepeatRRIb(&mips::MipsAssembler::ScR2, -16, "sc ${reg1}, {imm}(${reg2})"), "ScR2");
588 }
589
TEST_F(AssemblerMIPSTest,Slt)590 TEST_F(AssemblerMIPSTest, Slt) {
591 DriverStr(RepeatRRR(&mips::MipsAssembler::Slt, "slt ${reg1}, ${reg2}, ${reg3}"), "Slt");
592 }
593
TEST_F(AssemblerMIPSTest,Sltu)594 TEST_F(AssemblerMIPSTest, Sltu) {
595 DriverStr(RepeatRRR(&mips::MipsAssembler::Sltu, "sltu ${reg1}, ${reg2}, ${reg3}"), "Sltu");
596 }
597
TEST_F(AssemblerMIPSTest,Slti)598 TEST_F(AssemblerMIPSTest, Slti) {
599 DriverStr(RepeatRRIb(&mips::MipsAssembler::Slti, -16, "slti ${reg1}, ${reg2}, {imm}"), "Slti");
600 }
601
TEST_F(AssemblerMIPSTest,Sltiu)602 TEST_F(AssemblerMIPSTest, Sltiu) {
603 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sltiu, -16, "sltiu ${reg1}, ${reg2}, {imm}"), "Sltiu");
604 }
605
TEST_F(AssemblerMIPSTest,AddS)606 TEST_F(AssemblerMIPSTest, AddS) {
607 DriverStr(RepeatFFF(&mips::MipsAssembler::AddS, "add.s ${reg1}, ${reg2}, ${reg3}"), "AddS");
608 }
609
TEST_F(AssemblerMIPSTest,AddD)610 TEST_F(AssemblerMIPSTest, AddD) {
611 DriverStr(RepeatFFF(&mips::MipsAssembler::AddD, "add.d ${reg1}, ${reg2}, ${reg3}"), "AddD");
612 }
613
TEST_F(AssemblerMIPSTest,SubS)614 TEST_F(AssemblerMIPSTest, SubS) {
615 DriverStr(RepeatFFF(&mips::MipsAssembler::SubS, "sub.s ${reg1}, ${reg2}, ${reg3}"), "SubS");
616 }
617
TEST_F(AssemblerMIPSTest,SubD)618 TEST_F(AssemblerMIPSTest, SubD) {
619 DriverStr(RepeatFFF(&mips::MipsAssembler::SubD, "sub.d ${reg1}, ${reg2}, ${reg3}"), "SubD");
620 }
621
TEST_F(AssemblerMIPSTest,MulS)622 TEST_F(AssemblerMIPSTest, MulS) {
623 DriverStr(RepeatFFF(&mips::MipsAssembler::MulS, "mul.s ${reg1}, ${reg2}, ${reg3}"), "MulS");
624 }
625
TEST_F(AssemblerMIPSTest,MulD)626 TEST_F(AssemblerMIPSTest, MulD) {
627 DriverStr(RepeatFFF(&mips::MipsAssembler::MulD, "mul.d ${reg1}, ${reg2}, ${reg3}"), "MulD");
628 }
629
TEST_F(AssemblerMIPSTest,DivS)630 TEST_F(AssemblerMIPSTest, DivS) {
631 DriverStr(RepeatFFF(&mips::MipsAssembler::DivS, "div.s ${reg1}, ${reg2}, ${reg3}"), "DivS");
632 }
633
TEST_F(AssemblerMIPSTest,DivD)634 TEST_F(AssemblerMIPSTest, DivD) {
635 DriverStr(RepeatFFF(&mips::MipsAssembler::DivD, "div.d ${reg1}, ${reg2}, ${reg3}"), "DivD");
636 }
637
TEST_F(AssemblerMIPSTest,MovS)638 TEST_F(AssemblerMIPSTest, MovS) {
639 DriverStr(RepeatFF(&mips::MipsAssembler::MovS, "mov.s ${reg1}, ${reg2}"), "MovS");
640 }
641
TEST_F(AssemblerMIPSTest,MovD)642 TEST_F(AssemblerMIPSTest, MovD) {
643 DriverStr(RepeatFF(&mips::MipsAssembler::MovD, "mov.d ${reg1}, ${reg2}"), "MovD");
644 }
645
TEST_F(AssemblerMIPSTest,NegS)646 TEST_F(AssemblerMIPSTest, NegS) {
647 DriverStr(RepeatFF(&mips::MipsAssembler::NegS, "neg.s ${reg1}, ${reg2}"), "NegS");
648 }
649
TEST_F(AssemblerMIPSTest,NegD)650 TEST_F(AssemblerMIPSTest, NegD) {
651 DriverStr(RepeatFF(&mips::MipsAssembler::NegD, "neg.d ${reg1}, ${reg2}"), "NegD");
652 }
653
TEST_F(AssemblerMIPSTest,FloorWS)654 TEST_F(AssemblerMIPSTest, FloorWS) {
655 DriverStr(RepeatFF(&mips::MipsAssembler::FloorWS, "floor.w.s ${reg1}, ${reg2}"), "floor.w.s");
656 }
657
TEST_F(AssemblerMIPSTest,FloorWD)658 TEST_F(AssemblerMIPSTest, FloorWD) {
659 DriverStr(RepeatFF(&mips::MipsAssembler::FloorWD, "floor.w.d ${reg1}, ${reg2}"), "floor.w.d");
660 }
661
TEST_F(AssemblerMIPSTest,CunS)662 TEST_F(AssemblerMIPSTest, CunS) {
663 DriverStr(RepeatIbFF(&mips::MipsAssembler::CunS, 3, "c.un.s $fcc{imm}, ${reg1}, ${reg2}"),
664 "CunS");
665 }
666
TEST_F(AssemblerMIPSTest,CeqS)667 TEST_F(AssemblerMIPSTest, CeqS) {
668 DriverStr(RepeatIbFF(&mips::MipsAssembler::CeqS, 3, "c.eq.s $fcc{imm}, ${reg1}, ${reg2}"),
669 "CeqS");
670 }
671
TEST_F(AssemblerMIPSTest,CueqS)672 TEST_F(AssemblerMIPSTest, CueqS) {
673 DriverStr(RepeatIbFF(&mips::MipsAssembler::CueqS, 3, "c.ueq.s $fcc{imm}, ${reg1}, ${reg2}"),
674 "CueqS");
675 }
676
TEST_F(AssemblerMIPSTest,ColtS)677 TEST_F(AssemblerMIPSTest, ColtS) {
678 DriverStr(RepeatIbFF(&mips::MipsAssembler::ColtS, 3, "c.olt.s $fcc{imm}, ${reg1}, ${reg2}"),
679 "ColtS");
680 }
681
TEST_F(AssemblerMIPSTest,CultS)682 TEST_F(AssemblerMIPSTest, CultS) {
683 DriverStr(RepeatIbFF(&mips::MipsAssembler::CultS, 3, "c.ult.s $fcc{imm}, ${reg1}, ${reg2}"),
684 "CultS");
685 }
686
TEST_F(AssemblerMIPSTest,ColeS)687 TEST_F(AssemblerMIPSTest, ColeS) {
688 DriverStr(RepeatIbFF(&mips::MipsAssembler::ColeS, 3, "c.ole.s $fcc{imm}, ${reg1}, ${reg2}"),
689 "ColeS");
690 }
691
TEST_F(AssemblerMIPSTest,CuleS)692 TEST_F(AssemblerMIPSTest, CuleS) {
693 DriverStr(RepeatIbFF(&mips::MipsAssembler::CuleS, 3, "c.ule.s $fcc{imm}, ${reg1}, ${reg2}"),
694 "CuleS");
695 }
696
TEST_F(AssemblerMIPSTest,CunD)697 TEST_F(AssemblerMIPSTest, CunD) {
698 DriverStr(RepeatIbFF(&mips::MipsAssembler::CunD, 3, "c.un.d $fcc{imm}, ${reg1}, ${reg2}"),
699 "CunD");
700 }
701
TEST_F(AssemblerMIPSTest,CeqD)702 TEST_F(AssemblerMIPSTest, CeqD) {
703 DriverStr(RepeatIbFF(&mips::MipsAssembler::CeqD, 3, "c.eq.d $fcc{imm}, ${reg1}, ${reg2}"),
704 "CeqD");
705 }
706
TEST_F(AssemblerMIPSTest,CueqD)707 TEST_F(AssemblerMIPSTest, CueqD) {
708 DriverStr(RepeatIbFF(&mips::MipsAssembler::CueqD, 3, "c.ueq.d $fcc{imm}, ${reg1}, ${reg2}"),
709 "CueqD");
710 }
711
TEST_F(AssemblerMIPSTest,ColtD)712 TEST_F(AssemblerMIPSTest, ColtD) {
713 DriverStr(RepeatIbFF(&mips::MipsAssembler::ColtD, 3, "c.olt.d $fcc{imm}, ${reg1}, ${reg2}"),
714 "ColtD");
715 }
716
TEST_F(AssemblerMIPSTest,CultD)717 TEST_F(AssemblerMIPSTest, CultD) {
718 DriverStr(RepeatIbFF(&mips::MipsAssembler::CultD, 3, "c.ult.d $fcc{imm}, ${reg1}, ${reg2}"),
719 "CultD");
720 }
721
TEST_F(AssemblerMIPSTest,ColeD)722 TEST_F(AssemblerMIPSTest, ColeD) {
723 DriverStr(RepeatIbFF(&mips::MipsAssembler::ColeD, 3, "c.ole.d $fcc{imm}, ${reg1}, ${reg2}"),
724 "ColeD");
725 }
726
TEST_F(AssemblerMIPSTest,CuleD)727 TEST_F(AssemblerMIPSTest, CuleD) {
728 DriverStr(RepeatIbFF(&mips::MipsAssembler::CuleD, 3, "c.ule.d $fcc{imm}, ${reg1}, ${reg2}"),
729 "CuleD");
730 }
731
TEST_F(AssemblerMIPSTest,Movf)732 TEST_F(AssemblerMIPSTest, Movf) {
733 DriverStr(RepeatRRIb(&mips::MipsAssembler::Movf, 3, "movf ${reg1}, ${reg2}, $fcc{imm}"), "Movf");
734 }
735
TEST_F(AssemblerMIPSTest,Movt)736 TEST_F(AssemblerMIPSTest, Movt) {
737 DriverStr(RepeatRRIb(&mips::MipsAssembler::Movt, 3, "movt ${reg1}, ${reg2}, $fcc{imm}"), "Movt");
738 }
739
TEST_F(AssemblerMIPSTest,MovfS)740 TEST_F(AssemblerMIPSTest, MovfS) {
741 DriverStr(RepeatFFIb(&mips::MipsAssembler::MovfS, 3, "movf.s ${reg1}, ${reg2}, $fcc{imm}"),
742 "MovfS");
743 }
744
TEST_F(AssemblerMIPSTest,MovfD)745 TEST_F(AssemblerMIPSTest, MovfD) {
746 DriverStr(RepeatFFIb(&mips::MipsAssembler::MovfD, 3, "movf.d ${reg1}, ${reg2}, $fcc{imm}"),
747 "MovfD");
748 }
749
TEST_F(AssemblerMIPSTest,MovtS)750 TEST_F(AssemblerMIPSTest, MovtS) {
751 DriverStr(RepeatFFIb(&mips::MipsAssembler::MovtS, 3, "movt.s ${reg1}, ${reg2}, $fcc{imm}"),
752 "MovtS");
753 }
754
TEST_F(AssemblerMIPSTest,MovtD)755 TEST_F(AssemblerMIPSTest, MovtD) {
756 DriverStr(RepeatFFIb(&mips::MipsAssembler::MovtD, 3, "movt.d ${reg1}, ${reg2}, $fcc{imm}"),
757 "MovtD");
758 }
759
TEST_F(AssemblerMIPSTest,MovzS)760 TEST_F(AssemblerMIPSTest, MovzS) {
761 DriverStr(RepeatFFR(&mips::MipsAssembler::MovzS, "movz.s ${reg1}, ${reg2}, ${reg3}"), "MovzS");
762 }
763
TEST_F(AssemblerMIPSTest,MovzD)764 TEST_F(AssemblerMIPSTest, MovzD) {
765 DriverStr(RepeatFFR(&mips::MipsAssembler::MovzD, "movz.d ${reg1}, ${reg2}, ${reg3}"), "MovzD");
766 }
767
TEST_F(AssemblerMIPSTest,MovnS)768 TEST_F(AssemblerMIPSTest, MovnS) {
769 DriverStr(RepeatFFR(&mips::MipsAssembler::MovnS, "movn.s ${reg1}, ${reg2}, ${reg3}"), "MovnS");
770 }
771
TEST_F(AssemblerMIPSTest,MovnD)772 TEST_F(AssemblerMIPSTest, MovnD) {
773 DriverStr(RepeatFFR(&mips::MipsAssembler::MovnD, "movn.d ${reg1}, ${reg2}, ${reg3}"), "MovnD");
774 }
775
TEST_F(AssemblerMIPSTest,CvtSW)776 TEST_F(AssemblerMIPSTest, CvtSW) {
777 DriverStr(RepeatFF(&mips::MipsAssembler::Cvtsw, "cvt.s.w ${reg1}, ${reg2}"), "CvtSW");
778 }
779
TEST_F(AssemblerMIPSTest,CvtDW)780 TEST_F(AssemblerMIPSTest, CvtDW) {
781 DriverStr(RepeatFF(&mips::MipsAssembler::Cvtdw, "cvt.d.w ${reg1}, ${reg2}"), "CvtDW");
782 }
783
TEST_F(AssemblerMIPSTest,CvtSL)784 TEST_F(AssemblerMIPSTest, CvtSL) {
785 DriverStr(RepeatFF(&mips::MipsAssembler::Cvtsl, "cvt.s.l ${reg1}, ${reg2}"), "CvtSL");
786 }
787
TEST_F(AssemblerMIPSTest,CvtDL)788 TEST_F(AssemblerMIPSTest, CvtDL) {
789 DriverStr(RepeatFF(&mips::MipsAssembler::Cvtdl, "cvt.d.l ${reg1}, ${reg2}"), "CvtDL");
790 }
791
TEST_F(AssemblerMIPSTest,CvtSD)792 TEST_F(AssemblerMIPSTest, CvtSD) {
793 DriverStr(RepeatFF(&mips::MipsAssembler::Cvtsd, "cvt.s.d ${reg1}, ${reg2}"), "CvtSD");
794 }
795
TEST_F(AssemblerMIPSTest,CvtDS)796 TEST_F(AssemblerMIPSTest, CvtDS) {
797 DriverStr(RepeatFF(&mips::MipsAssembler::Cvtds, "cvt.d.s ${reg1}, ${reg2}"), "CvtDS");
798 }
799
TEST_F(AssemblerMIPSTest,TruncWS)800 TEST_F(AssemblerMIPSTest, TruncWS) {
801 DriverStr(RepeatFF(&mips::MipsAssembler::TruncWS, "trunc.w.s ${reg1}, ${reg2}"), "TruncWS");
802 }
803
TEST_F(AssemblerMIPSTest,TruncWD)804 TEST_F(AssemblerMIPSTest, TruncWD) {
805 DriverStr(RepeatFF(&mips::MipsAssembler::TruncWD, "trunc.w.d ${reg1}, ${reg2}"), "TruncWD");
806 }
807
TEST_F(AssemblerMIPSTest,TruncLS)808 TEST_F(AssemblerMIPSTest, TruncLS) {
809 DriverStr(RepeatFF(&mips::MipsAssembler::TruncLS, "trunc.l.s ${reg1}, ${reg2}"), "TruncLS");
810 }
811
TEST_F(AssemblerMIPSTest,TruncLD)812 TEST_F(AssemblerMIPSTest, TruncLD) {
813 DriverStr(RepeatFF(&mips::MipsAssembler::TruncLD, "trunc.l.d ${reg1}, ${reg2}"), "TruncLD");
814 }
815
TEST_F(AssemblerMIPSTest,Mfc1)816 TEST_F(AssemblerMIPSTest, Mfc1) {
817 DriverStr(RepeatRF(&mips::MipsAssembler::Mfc1, "mfc1 ${reg1}, ${reg2}"), "Mfc1");
818 }
819
TEST_F(AssemblerMIPSTest,Mtc1)820 TEST_F(AssemblerMIPSTest, Mtc1) {
821 DriverStr(RepeatRF(&mips::MipsAssembler::Mtc1, "mtc1 ${reg1}, ${reg2}"), "Mtc1");
822 }
823
TEST_F(AssemblerMIPSTest,Mfhc1)824 TEST_F(AssemblerMIPSTest, Mfhc1) {
825 DriverStr(RepeatRF(&mips::MipsAssembler::Mfhc1, "mfhc1 ${reg1}, ${reg2}"), "Mfhc1");
826 }
827
TEST_F(AssemblerMIPSTest,Mthc1)828 TEST_F(AssemblerMIPSTest, Mthc1) {
829 DriverStr(RepeatRF(&mips::MipsAssembler::Mthc1, "mthc1 ${reg1}, ${reg2}"), "Mthc1");
830 }
831
TEST_F(AssemblerMIPSTest,Lwc1)832 TEST_F(AssemblerMIPSTest, Lwc1) {
833 DriverStr(RepeatFRIb(&mips::MipsAssembler::Lwc1, -16, "lwc1 ${reg1}, {imm}(${reg2})"), "Lwc1");
834 }
835
TEST_F(AssemblerMIPSTest,Ldc1)836 TEST_F(AssemblerMIPSTest, Ldc1) {
837 DriverStr(RepeatFRIb(&mips::MipsAssembler::Ldc1, -16, "ldc1 ${reg1}, {imm}(${reg2})"), "Ldc1");
838 }
839
TEST_F(AssemblerMIPSTest,Swc1)840 TEST_F(AssemblerMIPSTest, Swc1) {
841 DriverStr(RepeatFRIb(&mips::MipsAssembler::Swc1, -16, "swc1 ${reg1}, {imm}(${reg2})"), "Swc1");
842 }
843
TEST_F(AssemblerMIPSTest,Sdc1)844 TEST_F(AssemblerMIPSTest, Sdc1) {
845 DriverStr(RepeatFRIb(&mips::MipsAssembler::Sdc1, -16, "sdc1 ${reg1}, {imm}(${reg2})"), "Sdc1");
846 }
847
TEST_F(AssemblerMIPSTest,Move)848 TEST_F(AssemblerMIPSTest, Move) {
849 DriverStr(RepeatRR(&mips::MipsAssembler::Move, "or ${reg1}, ${reg2}, $zero"), "Move");
850 }
851
TEST_F(AssemblerMIPSTest,Clear)852 TEST_F(AssemblerMIPSTest, Clear) {
853 DriverStr(RepeatR(&mips::MipsAssembler::Clear, "or ${reg}, $zero, $zero"), "Clear");
854 }
855
TEST_F(AssemblerMIPSTest,Not)856 TEST_F(AssemblerMIPSTest, Not) {
857 DriverStr(RepeatRR(&mips::MipsAssembler::Not, "nor ${reg1}, ${reg2}, $zero"), "Not");
858 }
859
TEST_F(AssemblerMIPSTest,Addiu32)860 TEST_F(AssemblerMIPSTest, Addiu32) {
861 __ Addiu32(mips::A1, mips::A2, -0x8000);
862 __ Addiu32(mips::A1, mips::A2, +0);
863 __ Addiu32(mips::A1, mips::A2, +0x7FFF);
864 __ Addiu32(mips::A1, mips::A2, -0x10000);
865 __ Addiu32(mips::A1, mips::A2, -0x8001);
866 __ Addiu32(mips::A1, mips::A2, +0x8000);
867 __ Addiu32(mips::A1, mips::A2, +0xFFFE);
868 __ Addiu32(mips::A1, mips::A2, -0x10001);
869 __ Addiu32(mips::A1, mips::A2, +0xFFFF);
870 __ Addiu32(mips::A1, mips::A2, +0x10000);
871 __ Addiu32(mips::A1, mips::A2, +0x10001);
872 __ Addiu32(mips::A1, mips::A2, +0x12345678);
873
874 const char* expected =
875 "addiu $a1, $a2, -0x8000\n"
876 "addiu $a1, $a2, 0\n"
877 "addiu $a1, $a2, 0x7FFF\n"
878 "addiu $at, $a2, -0x8000\n"
879 "addiu $a1, $at, -0x8000\n"
880 "addiu $at, $a2, -0x8000\n"
881 "addiu $a1, $at, -1\n"
882 "addiu $at, $a2, 0x7FFF\n"
883 "addiu $a1, $at, 1\n"
884 "addiu $at, $a2, 0x7FFF\n"
885 "addiu $a1, $at, 0x7FFF\n"
886 "lui $at, 0xFFFE\n"
887 "ori $at, $at, 0xFFFF\n"
888 "addu $a1, $a2, $at\n"
889 "ori $at, $zero, 0xFFFF\n"
890 "addu $a1, $a2, $at\n"
891 "lui $at, 1\n"
892 "addu $a1, $a2, $at\n"
893 "lui $at, 1\n"
894 "ori $at, $at, 1\n"
895 "addu $a1, $a2, $at\n"
896 "lui $at, 0x1234\n"
897 "ori $at, $at, 0x5678\n"
898 "addu $a1, $a2, $at\n";
899 DriverStr(expected, "Addiu32");
900 }
901
TEST_F(AssemblerMIPSTest,LoadFromOffset)902 TEST_F(AssemblerMIPSTest, LoadFromOffset) {
903 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x8000);
904 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0);
905 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x7FF8);
906 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x7FFB);
907 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x7FFC);
908 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x7FFF);
909 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0xFFF0);
910 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x8008);
911 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x8001);
912 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x8000);
913 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0xFFF0);
914 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x17FE8);
915 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x0FFF8);
916 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x0FFF1);
917 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x0FFF1);
918 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x0FFF8);
919 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x17FE8);
920 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x17FF0);
921 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, -0x17FE9);
922 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x17FE9);
923 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x17FF0);
924 __ LoadFromOffset(mips::kLoadSignedByte, mips::A3, mips::A1, +0x12345678);
925
926 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x8000);
927 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0);
928 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x7FF8);
929 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x7FFB);
930 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x7FFC);
931 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x7FFF);
932 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0xFFF0);
933 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x8008);
934 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x8001);
935 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x8000);
936 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0xFFF0);
937 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x17FE8);
938 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x0FFF8);
939 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x0FFF1);
940 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x0FFF1);
941 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x0FFF8);
942 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x17FE8);
943 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x17FF0);
944 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, -0x17FE9);
945 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x17FE9);
946 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x17FF0);
947 __ LoadFromOffset(mips::kLoadUnsignedByte, mips::A3, mips::A1, +0x12345678);
948
949 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x8000);
950 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0);
951 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x7FF8);
952 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x7FFB);
953 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x7FFC);
954 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x7FFF);
955 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0xFFF0);
956 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x8008);
957 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x8001);
958 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x8000);
959 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0xFFF0);
960 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x17FE8);
961 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x0FFF8);
962 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x0FFF1);
963 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x0FFF1);
964 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x0FFF8);
965 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x17FE8);
966 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x17FF0);
967 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, -0x17FE9);
968 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x17FE9);
969 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x17FF0);
970 __ LoadFromOffset(mips::kLoadSignedHalfword, mips::A3, mips::A1, +0x12345678);
971
972 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x8000);
973 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0);
974 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x7FF8);
975 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x7FFB);
976 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x7FFC);
977 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x7FFF);
978 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0xFFF0);
979 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x8008);
980 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x8001);
981 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x8000);
982 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0xFFF0);
983 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x17FE8);
984 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x0FFF8);
985 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x0FFF1);
986 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x0FFF1);
987 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x0FFF8);
988 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x17FE8);
989 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x17FF0);
990 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, -0x17FE9);
991 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x17FE9);
992 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x17FF0);
993 __ LoadFromOffset(mips::kLoadUnsignedHalfword, mips::A3, mips::A1, +0x12345678);
994
995 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x8000);
996 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0);
997 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x7FF8);
998 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x7FFB);
999 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x7FFC);
1000 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x7FFF);
1001 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0xFFF0);
1002 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x8008);
1003 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x8001);
1004 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x8000);
1005 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0xFFF0);
1006 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x17FE8);
1007 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x0FFF8);
1008 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x0FFF1);
1009 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x0FFF1);
1010 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x0FFF8);
1011 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x17FE8);
1012 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x17FF0);
1013 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, -0x17FE9);
1014 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x17FE9);
1015 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x17FF0);
1016 __ LoadFromOffset(mips::kLoadWord, mips::A3, mips::A1, +0x12345678);
1017
1018 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x8000);
1019 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0);
1020 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FF8);
1021 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFB);
1022 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFC);
1023 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFF);
1024 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0xFFF0);
1025 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x8008);
1026 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x8001);
1027 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x8000);
1028 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0xFFF0);
1029 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x17FE8);
1030 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x0FFF8);
1031 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x0FFF1);
1032 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x0FFF1);
1033 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x0FFF8);
1034 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x17FE8);
1035 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x17FF0);
1036 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x17FE9);
1037 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x17FE9);
1038 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x17FF0);
1039 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x12345678);
1040
1041 const char* expected =
1042 "lb $a3, -0x8000($a1)\n"
1043 "lb $a3, 0($a1)\n"
1044 "lb $a3, 0x7FF8($a1)\n"
1045 "lb $a3, 0x7FFB($a1)\n"
1046 "lb $a3, 0x7FFC($a1)\n"
1047 "lb $a3, 0x7FFF($a1)\n"
1048 "addiu $at, $a1, -0x7FF8\n"
1049 "lb $a3, -0x7FF8($at)\n"
1050 "addiu $at, $a1, -0x7FF8\n"
1051 "lb $a3, -0x10($at)\n"
1052 "addiu $at, $a1, -0x7FF8\n"
1053 "lb $a3, -9($at)\n"
1054 "addiu $at, $a1, 0x7FF8\n"
1055 "lb $a3, 8($at)\n"
1056 "addiu $at, $a1, 0x7FF8\n"
1057 "lb $a3, 0x7FF8($at)\n"
1058 "addiu $at, $a1, -0x7FF8\n"
1059 "addiu $at, $at, -0x7FF8\n"
1060 "lb $a3, -0x7FF8($at)\n"
1061 "addiu $at, $a1, -0x7FF8\n"
1062 "addiu $at, $at, -0x7FF8\n"
1063 "lb $a3, -8($at)\n"
1064 "addiu $at, $a1, -0x7FF8\n"
1065 "addiu $at, $at, -0x7FF8\n"
1066 "lb $a3, -1($at)\n"
1067 "addiu $at, $a1, 0x7FF8\n"
1068 "addiu $at, $at, 0x7FF8\n"
1069 "lb $a3, 1($at)\n"
1070 "addiu $at, $a1, 0x7FF8\n"
1071 "addiu $at, $at, 0x7FF8\n"
1072 "lb $a3, 8($at)\n"
1073 "addiu $at, $a1, 0x7FF8\n"
1074 "addiu $at, $at, 0x7FF8\n"
1075 "lb $a3, 0x7FF8($at)\n"
1076 "lui $at, 0xFFFE\n"
1077 "ori $at, $at, 0x8010\n"
1078 "addu $at, $at, $a1\n"
1079 "lb $a3, 0($at)\n"
1080 "lui $at, 0xFFFE\n"
1081 "ori $at, $at, 0x8010\n"
1082 "addu $at, $at, $a1\n"
1083 "lb $a3, 7($at)\n"
1084 "lui $at, 0x1\n"
1085 "ori $at, $at, 0x7FE8\n"
1086 "addu $at, $at, $a1\n"
1087 "lb $a3, 1($at)\n"
1088 "lui $at, 0x1\n"
1089 "ori $at, $at, 0x7FF0\n"
1090 "addu $at, $at, $a1\n"
1091 "lb $a3, 0($at)\n"
1092 "lui $at, 0x1234\n"
1093 "ori $at, $at, 0x5678\n"
1094 "addu $at, $at, $a1\n"
1095 "lb $a3, 0($at)\n"
1096
1097 "lbu $a3, -0x8000($a1)\n"
1098 "lbu $a3, 0($a1)\n"
1099 "lbu $a3, 0x7FF8($a1)\n"
1100 "lbu $a3, 0x7FFB($a1)\n"
1101 "lbu $a3, 0x7FFC($a1)\n"
1102 "lbu $a3, 0x7FFF($a1)\n"
1103 "addiu $at, $a1, -0x7FF8\n"
1104 "lbu $a3, -0x7FF8($at)\n"
1105 "addiu $at, $a1, -0x7FF8\n"
1106 "lbu $a3, -0x10($at)\n"
1107 "addiu $at, $a1, -0x7FF8\n"
1108 "lbu $a3, -9($at)\n"
1109 "addiu $at, $a1, 0x7FF8\n"
1110 "lbu $a3, 8($at)\n"
1111 "addiu $at, $a1, 0x7FF8\n"
1112 "lbu $a3, 0x7FF8($at)\n"
1113 "addiu $at, $a1, -0x7FF8\n"
1114 "addiu $at, $at, -0x7FF8\n"
1115 "lbu $a3, -0x7FF8($at)\n"
1116 "addiu $at, $a1, -0x7FF8\n"
1117 "addiu $at, $at, -0x7FF8\n"
1118 "lbu $a3, -8($at)\n"
1119 "addiu $at, $a1, -0x7FF8\n"
1120 "addiu $at, $at, -0x7FF8\n"
1121 "lbu $a3, -1($at)\n"
1122 "addiu $at, $a1, 0x7FF8\n"
1123 "addiu $at, $at, 0x7FF8\n"
1124 "lbu $a3, 1($at)\n"
1125 "addiu $at, $a1, 0x7FF8\n"
1126 "addiu $at, $at, 0x7FF8\n"
1127 "lbu $a3, 8($at)\n"
1128 "addiu $at, $a1, 0x7FF8\n"
1129 "addiu $at, $at, 0x7FF8\n"
1130 "lbu $a3, 0x7FF8($at)\n"
1131 "lui $at, 0xFFFE\n"
1132 "ori $at, $at, 0x8010\n"
1133 "addu $at, $at, $a1\n"
1134 "lbu $a3, 0($at)\n"
1135 "lui $at, 0xFFFE\n"
1136 "ori $at, $at, 0x8010\n"
1137 "addu $at, $at, $a1\n"
1138 "lbu $a3, 7($at)\n"
1139 "lui $at, 0x1\n"
1140 "ori $at, $at, 0x7FE8\n"
1141 "addu $at, $at, $a1\n"
1142 "lbu $a3, 1($at)\n"
1143 "lui $at, 0x1\n"
1144 "ori $at, $at, 0x7FF0\n"
1145 "addu $at, $at, $a1\n"
1146 "lbu $a3, 0($at)\n"
1147 "lui $at, 0x1234\n"
1148 "ori $at, $at, 0x5678\n"
1149 "addu $at, $at, $a1\n"
1150 "lbu $a3, 0($at)\n"
1151
1152 "lh $a3, -0x8000($a1)\n"
1153 "lh $a3, 0($a1)\n"
1154 "lh $a3, 0x7FF8($a1)\n"
1155 "lh $a3, 0x7FFB($a1)\n"
1156 "lh $a3, 0x7FFC($a1)\n"
1157 "lh $a3, 0x7FFF($a1)\n"
1158 "addiu $at, $a1, -0x7FF8\n"
1159 "lh $a3, -0x7FF8($at)\n"
1160 "addiu $at, $a1, -0x7FF8\n"
1161 "lh $a3, -0x10($at)\n"
1162 "addiu $at, $a1, -0x7FF8\n"
1163 "lh $a3, -9($at)\n"
1164 "addiu $at, $a1, 0x7FF8\n"
1165 "lh $a3, 8($at)\n"
1166 "addiu $at, $a1, 0x7FF8\n"
1167 "lh $a3, 0x7FF8($at)\n"
1168 "addiu $at, $a1, -0x7FF8\n"
1169 "addiu $at, $at, -0x7FF8\n"
1170 "lh $a3, -0x7FF8($at)\n"
1171 "addiu $at, $a1, -0x7FF8\n"
1172 "addiu $at, $at, -0x7FF8\n"
1173 "lh $a3, -8($at)\n"
1174 "addiu $at, $a1, -0x7FF8\n"
1175 "addiu $at, $at, -0x7FF8\n"
1176 "lh $a3, -1($at)\n"
1177 "addiu $at, $a1, 0x7FF8\n"
1178 "addiu $at, $at, 0x7FF8\n"
1179 "lh $a3, 1($at)\n"
1180 "addiu $at, $a1, 0x7FF8\n"
1181 "addiu $at, $at, 0x7FF8\n"
1182 "lh $a3, 8($at)\n"
1183 "addiu $at, $a1, 0x7FF8\n"
1184 "addiu $at, $at, 0x7FF8\n"
1185 "lh $a3, 0x7FF8($at)\n"
1186 "lui $at, 0xFFFE\n"
1187 "ori $at, $at, 0x8010\n"
1188 "addu $at, $at, $a1\n"
1189 "lh $a3, 0($at)\n"
1190 "lui $at, 0xFFFE\n"
1191 "ori $at, $at, 0x8010\n"
1192 "addu $at, $at, $a1\n"
1193 "lh $a3, 7($at)\n"
1194 "lui $at, 0x1\n"
1195 "ori $at, $at, 0x7FE8\n"
1196 "addu $at, $at, $a1\n"
1197 "lh $a3, 1($at)\n"
1198 "lui $at, 0x1\n"
1199 "ori $at, $at, 0x7FF0\n"
1200 "addu $at, $at, $a1\n"
1201 "lh $a3, 0($at)\n"
1202 "lui $at, 0x1234\n"
1203 "ori $at, $at, 0x5678\n"
1204 "addu $at, $at, $a1\n"
1205 "lh $a3, 0($at)\n"
1206
1207 "lhu $a3, -0x8000($a1)\n"
1208 "lhu $a3, 0($a1)\n"
1209 "lhu $a3, 0x7FF8($a1)\n"
1210 "lhu $a3, 0x7FFB($a1)\n"
1211 "lhu $a3, 0x7FFC($a1)\n"
1212 "lhu $a3, 0x7FFF($a1)\n"
1213 "addiu $at, $a1, -0x7FF8\n"
1214 "lhu $a3, -0x7FF8($at)\n"
1215 "addiu $at, $a1, -0x7FF8\n"
1216 "lhu $a3, -0x10($at)\n"
1217 "addiu $at, $a1, -0x7FF8\n"
1218 "lhu $a3, -9($at)\n"
1219 "addiu $at, $a1, 0x7FF8\n"
1220 "lhu $a3, 8($at)\n"
1221 "addiu $at, $a1, 0x7FF8\n"
1222 "lhu $a3, 0x7FF8($at)\n"
1223 "addiu $at, $a1, -0x7FF8\n"
1224 "addiu $at, $at, -0x7FF8\n"
1225 "lhu $a3, -0x7FF8($at)\n"
1226 "addiu $at, $a1, -0x7FF8\n"
1227 "addiu $at, $at, -0x7FF8\n"
1228 "lhu $a3, -8($at)\n"
1229 "addiu $at, $a1, -0x7FF8\n"
1230 "addiu $at, $at, -0x7FF8\n"
1231 "lhu $a3, -1($at)\n"
1232 "addiu $at, $a1, 0x7FF8\n"
1233 "addiu $at, $at, 0x7FF8\n"
1234 "lhu $a3, 1($at)\n"
1235 "addiu $at, $a1, 0x7FF8\n"
1236 "addiu $at, $at, 0x7FF8\n"
1237 "lhu $a3, 8($at)\n"
1238 "addiu $at, $a1, 0x7FF8\n"
1239 "addiu $at, $at, 0x7FF8\n"
1240 "lhu $a3, 0x7FF8($at)\n"
1241 "lui $at, 0xFFFE\n"
1242 "ori $at, $at, 0x8010\n"
1243 "addu $at, $at, $a1\n"
1244 "lhu $a3, 0($at)\n"
1245 "lui $at, 0xFFFE\n"
1246 "ori $at, $at, 0x8010\n"
1247 "addu $at, $at, $a1\n"
1248 "lhu $a3, 7($at)\n"
1249 "lui $at, 0x1\n"
1250 "ori $at, $at, 0x7FE8\n"
1251 "addu $at, $at, $a1\n"
1252 "lhu $a3, 1($at)\n"
1253 "lui $at, 0x1\n"
1254 "ori $at, $at, 0x7FF0\n"
1255 "addu $at, $at, $a1\n"
1256 "lhu $a3, 0($at)\n"
1257 "lui $at, 0x1234\n"
1258 "ori $at, $at, 0x5678\n"
1259 "addu $at, $at, $a1\n"
1260 "lhu $a3, 0($at)\n"
1261
1262 "lw $a3, -0x8000($a1)\n"
1263 "lw $a3, 0($a1)\n"
1264 "lw $a3, 0x7FF8($a1)\n"
1265 "lw $a3, 0x7FFB($a1)\n"
1266 "lw $a3, 0x7FFC($a1)\n"
1267 "lw $a3, 0x7FFF($a1)\n"
1268 "addiu $at, $a1, -0x7FF8\n"
1269 "lw $a3, -0x7FF8($at)\n"
1270 "addiu $at, $a1, -0x7FF8\n"
1271 "lw $a3, -0x10($at)\n"
1272 "addiu $at, $a1, -0x7FF8\n"
1273 "lw $a3, -9($at)\n"
1274 "addiu $at, $a1, 0x7FF8\n"
1275 "lw $a3, 8($at)\n"
1276 "addiu $at, $a1, 0x7FF8\n"
1277 "lw $a3, 0x7FF8($at)\n"
1278 "addiu $at, $a1, -0x7FF8\n"
1279 "addiu $at, $at, -0x7FF8\n"
1280 "lw $a3, -0x7FF8($at)\n"
1281 "addiu $at, $a1, -0x7FF8\n"
1282 "addiu $at, $at, -0x7FF8\n"
1283 "lw $a3, -8($at)\n"
1284 "addiu $at, $a1, -0x7FF8\n"
1285 "addiu $at, $at, -0x7FF8\n"
1286 "lw $a3, -1($at)\n"
1287 "addiu $at, $a1, 0x7FF8\n"
1288 "addiu $at, $at, 0x7FF8\n"
1289 "lw $a3, 1($at)\n"
1290 "addiu $at, $a1, 0x7FF8\n"
1291 "addiu $at, $at, 0x7FF8\n"
1292 "lw $a3, 8($at)\n"
1293 "addiu $at, $a1, 0x7FF8\n"
1294 "addiu $at, $at, 0x7FF8\n"
1295 "lw $a3, 0x7FF8($at)\n"
1296 "lui $at, 0xFFFE\n"
1297 "ori $at, $at, 0x8010\n"
1298 "addu $at, $at, $a1\n"
1299 "lw $a3, 0($at)\n"
1300 "lui $at, 0xFFFE\n"
1301 "ori $at, $at, 0x8010\n"
1302 "addu $at, $at, $a1\n"
1303 "lw $a3, 7($at)\n"
1304 "lui $at, 0x1\n"
1305 "ori $at, $at, 0x7FE8\n"
1306 "addu $at, $at, $a1\n"
1307 "lw $a3, 1($at)\n"
1308 "lui $at, 0x1\n"
1309 "ori $at, $at, 0x7FF0\n"
1310 "addu $at, $at, $a1\n"
1311 "lw $a3, 0($at)\n"
1312 "lui $at, 0x1234\n"
1313 "ori $at, $at, 0x5678\n"
1314 "addu $at, $at, $a1\n"
1315 "lw $a3, 0($at)\n"
1316
1317 "lw $a0, -0x8000($a2)\n"
1318 "lw $a1, -0x7FFC($a2)\n"
1319 "lw $a0, 0($a2)\n"
1320 "lw $a1, 4($a2)\n"
1321 "lw $a0, 0x7FF8($a2)\n"
1322 "lw $a1, 0x7FFC($a2)\n"
1323 "lw $a0, 0x7FFB($a2)\n"
1324 "lw $a1, 0x7FFF($a2)\n"
1325 "addiu $at, $a2, 0x7FF8\n"
1326 "lw $a0, 4($at)\n"
1327 "lw $a1, 8($at)\n"
1328 "addiu $at, $a2, 0x7FF8\n"
1329 "lw $a0, 7($at)\n"
1330 "lw $a1, 11($at)\n"
1331 "addiu $at, $a2, -0x7FF8\n"
1332 "lw $a0, -0x7FF8($at)\n"
1333 "lw $a1, -0x7FF4($at)\n"
1334 "addiu $at, $a2, -0x7FF8\n"
1335 "lw $a0, -0x10($at)\n"
1336 "lw $a1, -0xC($at)\n"
1337 "addiu $at, $a2, -0x7FF8\n"
1338 "lw $a0, -9($at)\n"
1339 "lw $a1, -5($at)\n"
1340 "addiu $at, $a2, 0x7FF8\n"
1341 "lw $a0, 8($at)\n"
1342 "lw $a1, 12($at)\n"
1343 "addiu $at, $a2, 0x7FF8\n"
1344 "lw $a0, 0x7FF8($at)\n"
1345 "lw $a1, 0x7FFC($at)\n"
1346 "addiu $at, $a2, -0x7FF8\n"
1347 "addiu $at, $at, -0x7FF8\n"
1348 "lw $a0, -0x7FF8($at)\n"
1349 "lw $a1, -0x7FF4($at)\n"
1350 "addiu $at, $a2, -0x7FF8\n"
1351 "addiu $at, $at, -0x7FF8\n"
1352 "lw $a0, -8($at)\n"
1353 "lw $a1, -4($at)\n"
1354 "addiu $at, $a2, -0x7FF8\n"
1355 "addiu $at, $at, -0x7FF8\n"
1356 "lw $a0, -1($at)\n"
1357 "lw $a1, 3($at)\n"
1358 "addiu $at, $a2, 0x7FF8\n"
1359 "addiu $at, $at, 0x7FF8\n"
1360 "lw $a0, 1($at)\n"
1361 "lw $a1, 5($at)\n"
1362 "addiu $at, $a2, 0x7FF8\n"
1363 "addiu $at, $at, 0x7FF8\n"
1364 "lw $a0, 8($at)\n"
1365 "lw $a1, 12($at)\n"
1366 "addiu $at, $a2, 0x7FF8\n"
1367 "addiu $at, $at, 0x7FF8\n"
1368 "lw $a0, 0x7FF8($at)\n"
1369 "lw $a1, 0x7FFC($at)\n"
1370 "lui $at, 0xFFFE\n"
1371 "ori $at, $at, 0x8010\n"
1372 "addu $at, $at, $a2\n"
1373 "lw $a0, 0($at)\n"
1374 "lw $a1, 4($at)\n"
1375 "lui $at, 0xFFFE\n"
1376 "ori $at, $at, 0x8010\n"
1377 "addu $at, $at, $a2\n"
1378 "lw $a0, 7($at)\n"
1379 "lw $a1, 11($at)\n"
1380 "lui $at, 0x1\n"
1381 "ori $at, $at, 0x7FE8\n"
1382 "addu $at, $at, $a2\n"
1383 "lw $a0, 1($at)\n"
1384 "lw $a1, 5($at)\n"
1385 "lui $at, 0x1\n"
1386 "ori $at, $at, 0x7FF0\n"
1387 "addu $at, $at, $a2\n"
1388 "lw $a0, 0($at)\n"
1389 "lw $a1, 4($at)\n"
1390 "lui $at, 0x1234\n"
1391 "ori $at, $at, 0x5678\n"
1392 "addu $at, $at, $a2\n"
1393 "lw $a0, 0($at)\n"
1394 "lw $a1, 4($at)\n";
1395 DriverStr(expected, "LoadFromOffset");
1396 }
1397
TEST_F(AssemblerMIPSTest,LoadSFromOffset)1398 TEST_F(AssemblerMIPSTest, LoadSFromOffset) {
1399 __ LoadSFromOffset(mips::F2, mips::A0, -0x8000);
1400 __ LoadSFromOffset(mips::F2, mips::A0, +0);
1401 __ LoadSFromOffset(mips::F2, mips::A0, +0x7FF8);
1402 __ LoadSFromOffset(mips::F2, mips::A0, +0x7FFB);
1403 __ LoadSFromOffset(mips::F2, mips::A0, +0x7FFC);
1404 __ LoadSFromOffset(mips::F2, mips::A0, +0x7FFF);
1405 __ LoadSFromOffset(mips::F2, mips::A0, -0xFFF0);
1406 __ LoadSFromOffset(mips::F2, mips::A0, -0x8008);
1407 __ LoadSFromOffset(mips::F2, mips::A0, -0x8001);
1408 __ LoadSFromOffset(mips::F2, mips::A0, +0x8000);
1409 __ LoadSFromOffset(mips::F2, mips::A0, +0xFFF0);
1410 __ LoadSFromOffset(mips::F2, mips::A0, -0x17FE8);
1411 __ LoadSFromOffset(mips::F2, mips::A0, -0x0FFF8);
1412 __ LoadSFromOffset(mips::F2, mips::A0, -0x0FFF1);
1413 __ LoadSFromOffset(mips::F2, mips::A0, +0x0FFF1);
1414 __ LoadSFromOffset(mips::F2, mips::A0, +0x0FFF8);
1415 __ LoadSFromOffset(mips::F2, mips::A0, +0x17FE8);
1416 __ LoadSFromOffset(mips::F2, mips::A0, -0x17FF0);
1417 __ LoadSFromOffset(mips::F2, mips::A0, -0x17FE9);
1418 __ LoadSFromOffset(mips::F2, mips::A0, +0x17FE9);
1419 __ LoadSFromOffset(mips::F2, mips::A0, +0x17FF0);
1420 __ LoadSFromOffset(mips::F2, mips::A0, +0x12345678);
1421
1422 const char* expected =
1423 "lwc1 $f2, -0x8000($a0)\n"
1424 "lwc1 $f2, 0($a0)\n"
1425 "lwc1 $f2, 0x7FF8($a0)\n"
1426 "lwc1 $f2, 0x7FFB($a0)\n"
1427 "lwc1 $f2, 0x7FFC($a0)\n"
1428 "lwc1 $f2, 0x7FFF($a0)\n"
1429 "addiu $at, $a0, -0x7FF8\n"
1430 "lwc1 $f2, -0x7FF8($at)\n"
1431 "addiu $at, $a0, -0x7FF8\n"
1432 "lwc1 $f2, -0x10($at)\n"
1433 "addiu $at, $a0, -0x7FF8\n"
1434 "lwc1 $f2, -9($at)\n"
1435 "addiu $at, $a0, 0x7FF8\n"
1436 "lwc1 $f2, 8($at)\n"
1437 "addiu $at, $a0, 0x7FF8\n"
1438 "lwc1 $f2, 0x7FF8($at)\n"
1439 "addiu $at, $a0, -0x7FF8\n"
1440 "addiu $at, $at, -0x7FF8\n"
1441 "lwc1 $f2, -0x7FF8($at)\n"
1442 "addiu $at, $a0, -0x7FF8\n"
1443 "addiu $at, $at, -0x7FF8\n"
1444 "lwc1 $f2, -8($at)\n"
1445 "addiu $at, $a0, -0x7FF8\n"
1446 "addiu $at, $at, -0x7FF8\n"
1447 "lwc1 $f2, -1($at)\n"
1448 "addiu $at, $a0, 0x7FF8\n"
1449 "addiu $at, $at, 0x7FF8\n"
1450 "lwc1 $f2, 1($at)\n"
1451 "addiu $at, $a0, 0x7FF8\n"
1452 "addiu $at, $at, 0x7FF8\n"
1453 "lwc1 $f2, 8($at)\n"
1454 "addiu $at, $a0, 0x7FF8\n"
1455 "addiu $at, $at, 0x7FF8\n"
1456 "lwc1 $f2, 0x7FF8($at)\n"
1457 "lui $at, 0xFFFE\n"
1458 "ori $at, $at, 0x8010\n"
1459 "addu $at, $at, $a0\n"
1460 "lwc1 $f2, 0($at)\n"
1461 "lui $at, 0xFFFE\n"
1462 "ori $at, $at, 0x8010\n"
1463 "addu $at, $at, $a0\n"
1464 "lwc1 $f2, 7($at)\n"
1465 "lui $at, 0x1\n"
1466 "ori $at, $at, 0x7FE8\n"
1467 "addu $at, $at, $a0\n"
1468 "lwc1 $f2, 1($at)\n"
1469 "lui $at, 0x1\n"
1470 "ori $at, $at, 0x7FF0\n"
1471 "addu $at, $at, $a0\n"
1472 "lwc1 $f2, 0($at)\n"
1473 "lui $at, 0x1234\n"
1474 "ori $at, $at, 0x5678\n"
1475 "addu $at, $at, $a0\n"
1476 "lwc1 $f2, 0($at)\n";
1477 DriverStr(expected, "LoadSFromOffset");
1478 }
1479
TEST_F(AssemblerMIPSTest,LoadDFromOffset)1480 TEST_F(AssemblerMIPSTest, LoadDFromOffset) {
1481 __ LoadDFromOffset(mips::F0, mips::A0, -0x8000);
1482 __ LoadDFromOffset(mips::F0, mips::A0, +0);
1483 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FF8);
1484 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFB);
1485 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFC);
1486 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFF);
1487 __ LoadDFromOffset(mips::F0, mips::A0, -0xFFF0);
1488 __ LoadDFromOffset(mips::F0, mips::A0, -0x8008);
1489 __ LoadDFromOffset(mips::F0, mips::A0, -0x8001);
1490 __ LoadDFromOffset(mips::F0, mips::A0, +0x8000);
1491 __ LoadDFromOffset(mips::F0, mips::A0, +0xFFF0);
1492 __ LoadDFromOffset(mips::F0, mips::A0, -0x17FE8);
1493 __ LoadDFromOffset(mips::F0, mips::A0, -0x0FFF8);
1494 __ LoadDFromOffset(mips::F0, mips::A0, -0x0FFF1);
1495 __ LoadDFromOffset(mips::F0, mips::A0, +0x0FFF1);
1496 __ LoadDFromOffset(mips::F0, mips::A0, +0x0FFF8);
1497 __ LoadDFromOffset(mips::F0, mips::A0, +0x17FE8);
1498 __ LoadDFromOffset(mips::F0, mips::A0, -0x17FF0);
1499 __ LoadDFromOffset(mips::F0, mips::A0, -0x17FE9);
1500 __ LoadDFromOffset(mips::F0, mips::A0, +0x17FE9);
1501 __ LoadDFromOffset(mips::F0, mips::A0, +0x17FF0);
1502 __ LoadDFromOffset(mips::F0, mips::A0, +0x12345678);
1503
1504 const char* expected =
1505 "ldc1 $f0, -0x8000($a0)\n"
1506 "ldc1 $f0, 0($a0)\n"
1507 "ldc1 $f0, 0x7FF8($a0)\n"
1508 "lwc1 $f0, 0x7FFB($a0)\n"
1509 "lwc1 $f1, 0x7FFF($a0)\n"
1510 "addiu $at, $a0, 0x7FF8\n"
1511 "lwc1 $f0, 4($at)\n"
1512 "lwc1 $f1, 8($at)\n"
1513 "addiu $at, $a0, 0x7FF8\n"
1514 "lwc1 $f0, 7($at)\n"
1515 "lwc1 $f1, 11($at)\n"
1516 "addiu $at, $a0, -0x7FF8\n"
1517 "ldc1 $f0, -0x7FF8($at)\n"
1518 "addiu $at, $a0, -0x7FF8\n"
1519 "ldc1 $f0, -0x10($at)\n"
1520 "addiu $at, $a0, -0x7FF8\n"
1521 "lwc1 $f0, -9($at)\n"
1522 "lwc1 $f1, -5($at)\n"
1523 "addiu $at, $a0, 0x7FF8\n"
1524 "ldc1 $f0, 8($at)\n"
1525 "addiu $at, $a0, 0x7FF8\n"
1526 "ldc1 $f0, 0x7FF8($at)\n"
1527 "addiu $at, $a0, -0x7FF8\n"
1528 "addiu $at, $at, -0x7FF8\n"
1529 "ldc1 $f0, -0x7FF8($at)\n"
1530 "addiu $at, $a0, -0x7FF8\n"
1531 "addiu $at, $at, -0x7FF8\n"
1532 "ldc1 $f0, -8($at)\n"
1533 "addiu $at, $a0, -0x7FF8\n"
1534 "addiu $at, $at, -0x7FF8\n"
1535 "lwc1 $f0, -1($at)\n"
1536 "lwc1 $f1, 3($at)\n"
1537 "addiu $at, $a0, 0x7FF8\n"
1538 "addiu $at, $at, 0x7FF8\n"
1539 "lwc1 $f0, 1($at)\n"
1540 "lwc1 $f1, 5($at)\n"
1541 "addiu $at, $a0, 0x7FF8\n"
1542 "addiu $at, $at, 0x7FF8\n"
1543 "ldc1 $f0, 8($at)\n"
1544 "addiu $at, $a0, 0x7FF8\n"
1545 "addiu $at, $at, 0x7FF8\n"
1546 "ldc1 $f0, 0x7FF8($at)\n"
1547 "lui $at, 0xFFFE\n"
1548 "ori $at, $at, 0x8010\n"
1549 "addu $at, $at, $a0\n"
1550 "ldc1 $f0, 0($at)\n"
1551 "lui $at, 0xFFFE\n"
1552 "ori $at, $at, 0x8010\n"
1553 "addu $at, $at, $a0\n"
1554 "lwc1 $f0, 7($at)\n"
1555 "lwc1 $f1, 11($at)\n"
1556 "lui $at, 0x1\n"
1557 "ori $at, $at, 0x7FE8\n"
1558 "addu $at, $at, $a0\n"
1559 "lwc1 $f0, 1($at)\n"
1560 "lwc1 $f1, 5($at)\n"
1561 "lui $at, 0x1\n"
1562 "ori $at, $at, 0x7FF0\n"
1563 "addu $at, $at, $a0\n"
1564 "ldc1 $f0, 0($at)\n"
1565 "lui $at, 0x1234\n"
1566 "ori $at, $at, 0x5678\n"
1567 "addu $at, $at, $a0\n"
1568 "ldc1 $f0, 0($at)\n";
1569 DriverStr(expected, "LoadDFromOffset");
1570 }
1571
TEST_F(AssemblerMIPSTest,StoreToOffset)1572 TEST_F(AssemblerMIPSTest, StoreToOffset) {
1573 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x8000);
1574 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0);
1575 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FF8);
1576 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FFB);
1577 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FFC);
1578 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FFF);
1579 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0xFFF0);
1580 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x8008);
1581 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x8001);
1582 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x8000);
1583 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0xFFF0);
1584 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x17FE8);
1585 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x0FFF8);
1586 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x0FFF1);
1587 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x0FFF1);
1588 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x0FFF8);
1589 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x17FE8);
1590 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x17FF0);
1591 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x17FE9);
1592 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x17FE9);
1593 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x17FF0);
1594 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x12345678);
1595
1596 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x8000);
1597 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0);
1598 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x7FF8);
1599 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x7FFB);
1600 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x7FFC);
1601 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x7FFF);
1602 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0xFFF0);
1603 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x8008);
1604 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x8001);
1605 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x8000);
1606 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0xFFF0);
1607 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x17FE8);
1608 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x0FFF8);
1609 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x0FFF1);
1610 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x0FFF1);
1611 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x0FFF8);
1612 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x17FE8);
1613 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x17FF0);
1614 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, -0x17FE9);
1615 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x17FE9);
1616 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x17FF0);
1617 __ StoreToOffset(mips::kStoreHalfword, mips::A3, mips::A1, +0x12345678);
1618
1619 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x8000);
1620 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0);
1621 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x7FF8);
1622 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x7FFB);
1623 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x7FFC);
1624 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x7FFF);
1625 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0xFFF0);
1626 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x8008);
1627 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x8001);
1628 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x8000);
1629 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0xFFF0);
1630 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x17FE8);
1631 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x0FFF8);
1632 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x0FFF1);
1633 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x0FFF1);
1634 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x0FFF8);
1635 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x17FE8);
1636 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x17FF0);
1637 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, -0x17FE9);
1638 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x17FE9);
1639 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x17FF0);
1640 __ StoreToOffset(mips::kStoreWord, mips::A3, mips::A1, +0x12345678);
1641
1642 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x8000);
1643 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0);
1644 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x7FF8);
1645 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x7FFB);
1646 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x7FFC);
1647 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x7FFF);
1648 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0xFFF0);
1649 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x8008);
1650 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x8001);
1651 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x8000);
1652 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0xFFF0);
1653 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x17FE8);
1654 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x0FFF8);
1655 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x0FFF1);
1656 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x0FFF1);
1657 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x0FFF8);
1658 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x17FE8);
1659 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x17FF0);
1660 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, -0x17FE9);
1661 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x17FE9);
1662 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x17FF0);
1663 __ StoreToOffset(mips::kStoreDoubleword, mips::A0, mips::A2, +0x12345678);
1664
1665 const char* expected =
1666 "sb $a3, -0x8000($a1)\n"
1667 "sb $a3, 0($a1)\n"
1668 "sb $a3, 0x7FF8($a1)\n"
1669 "sb $a3, 0x7FFB($a1)\n"
1670 "sb $a3, 0x7FFC($a1)\n"
1671 "sb $a3, 0x7FFF($a1)\n"
1672 "addiu $at, $a1, -0x7FF8\n"
1673 "sb $a3, -0x7FF8($at)\n"
1674 "addiu $at, $a1, -0x7FF8\n"
1675 "sb $a3, -0x10($at)\n"
1676 "addiu $at, $a1, -0x7FF8\n"
1677 "sb $a3, -9($at)\n"
1678 "addiu $at, $a1, 0x7FF8\n"
1679 "sb $a3, 8($at)\n"
1680 "addiu $at, $a1, 0x7FF8\n"
1681 "sb $a3, 0x7FF8($at)\n"
1682 "addiu $at, $a1, -0x7FF8\n"
1683 "addiu $at, $at, -0x7FF8\n"
1684 "sb $a3, -0x7FF8($at)\n"
1685 "addiu $at, $a1, -0x7FF8\n"
1686 "addiu $at, $at, -0x7FF8\n"
1687 "sb $a3, -8($at)\n"
1688 "addiu $at, $a1, -0x7FF8\n"
1689 "addiu $at, $at, -0x7FF8\n"
1690 "sb $a3, -1($at)\n"
1691 "addiu $at, $a1, 0x7FF8\n"
1692 "addiu $at, $at, 0x7FF8\n"
1693 "sb $a3, 1($at)\n"
1694 "addiu $at, $a1, 0x7FF8\n"
1695 "addiu $at, $at, 0x7FF8\n"
1696 "sb $a3, 8($at)\n"
1697 "addiu $at, $a1, 0x7FF8\n"
1698 "addiu $at, $at, 0x7FF8\n"
1699 "sb $a3, 0x7FF8($at)\n"
1700 "lui $at, 0xFFFE\n"
1701 "ori $at, $at, 0x8010\n"
1702 "addu $at, $at, $a1\n"
1703 "sb $a3, 0($at)\n"
1704 "lui $at, 0xFFFE\n"
1705 "ori $at, $at, 0x8010\n"
1706 "addu $at, $at, $a1\n"
1707 "sb $a3, 7($at)\n"
1708 "lui $at, 0x1\n"
1709 "ori $at, $at, 0x7FE8\n"
1710 "addu $at, $at, $a1\n"
1711 "sb $a3, 1($at)\n"
1712 "lui $at, 0x1\n"
1713 "ori $at, $at, 0x7FF0\n"
1714 "addu $at, $at, $a1\n"
1715 "sb $a3, 0($at)\n"
1716 "lui $at, 0x1234\n"
1717 "ori $at, $at, 0x5678\n"
1718 "addu $at, $at, $a1\n"
1719 "sb $a3, 0($at)\n"
1720
1721 "sh $a3, -0x8000($a1)\n"
1722 "sh $a3, 0($a1)\n"
1723 "sh $a3, 0x7FF8($a1)\n"
1724 "sh $a3, 0x7FFB($a1)\n"
1725 "sh $a3, 0x7FFC($a1)\n"
1726 "sh $a3, 0x7FFF($a1)\n"
1727 "addiu $at, $a1, -0x7FF8\n"
1728 "sh $a3, -0x7FF8($at)\n"
1729 "addiu $at, $a1, -0x7FF8\n"
1730 "sh $a3, -0x10($at)\n"
1731 "addiu $at, $a1, -0x7FF8\n"
1732 "sh $a3, -9($at)\n"
1733 "addiu $at, $a1, 0x7FF8\n"
1734 "sh $a3, 8($at)\n"
1735 "addiu $at, $a1, 0x7FF8\n"
1736 "sh $a3, 0x7FF8($at)\n"
1737 "addiu $at, $a1, -0x7FF8\n"
1738 "addiu $at, $at, -0x7FF8\n"
1739 "sh $a3, -0x7FF8($at)\n"
1740 "addiu $at, $a1, -0x7FF8\n"
1741 "addiu $at, $at, -0x7FF8\n"
1742 "sh $a3, -8($at)\n"
1743 "addiu $at, $a1, -0x7FF8\n"
1744 "addiu $at, $at, -0x7FF8\n"
1745 "sh $a3, -1($at)\n"
1746 "addiu $at, $a1, 0x7FF8\n"
1747 "addiu $at, $at, 0x7FF8\n"
1748 "sh $a3, 1($at)\n"
1749 "addiu $at, $a1, 0x7FF8\n"
1750 "addiu $at, $at, 0x7FF8\n"
1751 "sh $a3, 8($at)\n"
1752 "addiu $at, $a1, 0x7FF8\n"
1753 "addiu $at, $at, 0x7FF8\n"
1754 "sh $a3, 0x7FF8($at)\n"
1755 "lui $at, 0xFFFE\n"
1756 "ori $at, $at, 0x8010\n"
1757 "addu $at, $at, $a1\n"
1758 "sh $a3, 0($at)\n"
1759 "lui $at, 0xFFFE\n"
1760 "ori $at, $at, 0x8010\n"
1761 "addu $at, $at, $a1\n"
1762 "sh $a3, 7($at)\n"
1763 "lui $at, 0x1\n"
1764 "ori $at, $at, 0x7FE8\n"
1765 "addu $at, $at, $a1\n"
1766 "sh $a3, 1($at)\n"
1767 "lui $at, 0x1\n"
1768 "ori $at, $at, 0x7FF0\n"
1769 "addu $at, $at, $a1\n"
1770 "sh $a3, 0($at)\n"
1771 "lui $at, 0x1234\n"
1772 "ori $at, $at, 0x5678\n"
1773 "addu $at, $at, $a1\n"
1774 "sh $a3, 0($at)\n"
1775
1776 "sw $a3, -0x8000($a1)\n"
1777 "sw $a3, 0($a1)\n"
1778 "sw $a3, 0x7FF8($a1)\n"
1779 "sw $a3, 0x7FFB($a1)\n"
1780 "sw $a3, 0x7FFC($a1)\n"
1781 "sw $a3, 0x7FFF($a1)\n"
1782 "addiu $at, $a1, -0x7FF8\n"
1783 "sw $a3, -0x7FF8($at)\n"
1784 "addiu $at, $a1, -0x7FF8\n"
1785 "sw $a3, -0x10($at)\n"
1786 "addiu $at, $a1, -0x7FF8\n"
1787 "sw $a3, -9($at)\n"
1788 "addiu $at, $a1, 0x7FF8\n"
1789 "sw $a3, 8($at)\n"
1790 "addiu $at, $a1, 0x7FF8\n"
1791 "sw $a3, 0x7FF8($at)\n"
1792 "addiu $at, $a1, -0x7FF8\n"
1793 "addiu $at, $at, -0x7FF8\n"
1794 "sw $a3, -0x7FF8($at)\n"
1795 "addiu $at, $a1, -0x7FF8\n"
1796 "addiu $at, $at, -0x7FF8\n"
1797 "sw $a3, -8($at)\n"
1798 "addiu $at, $a1, -0x7FF8\n"
1799 "addiu $at, $at, -0x7FF8\n"
1800 "sw $a3, -1($at)\n"
1801 "addiu $at, $a1, 0x7FF8\n"
1802 "addiu $at, $at, 0x7FF8\n"
1803 "sw $a3, 1($at)\n"
1804 "addiu $at, $a1, 0x7FF8\n"
1805 "addiu $at, $at, 0x7FF8\n"
1806 "sw $a3, 8($at)\n"
1807 "addiu $at, $a1, 0x7FF8\n"
1808 "addiu $at, $at, 0x7FF8\n"
1809 "sw $a3, 0x7FF8($at)\n"
1810 "lui $at, 0xFFFE\n"
1811 "ori $at, $at, 0x8010\n"
1812 "addu $at, $at, $a1\n"
1813 "sw $a3, 0($at)\n"
1814 "lui $at, 0xFFFE\n"
1815 "ori $at, $at, 0x8010\n"
1816 "addu $at, $at, $a1\n"
1817 "sw $a3, 7($at)\n"
1818 "lui $at, 0x1\n"
1819 "ori $at, $at, 0x7FE8\n"
1820 "addu $at, $at, $a1\n"
1821 "sw $a3, 1($at)\n"
1822 "lui $at, 0x1\n"
1823 "ori $at, $at, 0x7FF0\n"
1824 "addu $at, $at, $a1\n"
1825 "sw $a3, 0($at)\n"
1826 "lui $at, 0x1234\n"
1827 "ori $at, $at, 0x5678\n"
1828 "addu $at, $at, $a1\n"
1829 "sw $a3, 0($at)\n"
1830
1831 "sw $a0, -0x8000($a2)\n"
1832 "sw $a1, -0x7FFC($a2)\n"
1833 "sw $a0, 0($a2)\n"
1834 "sw $a1, 4($a2)\n"
1835 "sw $a0, 0x7FF8($a2)\n"
1836 "sw $a1, 0x7FFC($a2)\n"
1837 "sw $a0, 0x7FFB($a2)\n"
1838 "sw $a1, 0x7FFF($a2)\n"
1839 "addiu $at, $a2, 0x7FF8\n"
1840 "sw $a0, 4($at)\n"
1841 "sw $a1, 8($at)\n"
1842 "addiu $at, $a2, 0x7FF8\n"
1843 "sw $a0, 7($at)\n"
1844 "sw $a1, 11($at)\n"
1845 "addiu $at, $a2, -0x7FF8\n"
1846 "sw $a0, -0x7FF8($at)\n"
1847 "sw $a1, -0x7FF4($at)\n"
1848 "addiu $at, $a2, -0x7FF8\n"
1849 "sw $a0, -0x10($at)\n"
1850 "sw $a1, -0xC($at)\n"
1851 "addiu $at, $a2, -0x7FF8\n"
1852 "sw $a0, -9($at)\n"
1853 "sw $a1, -5($at)\n"
1854 "addiu $at, $a2, 0x7FF8\n"
1855 "sw $a0, 8($at)\n"
1856 "sw $a1, 12($at)\n"
1857 "addiu $at, $a2, 0x7FF8\n"
1858 "sw $a0, 0x7FF8($at)\n"
1859 "sw $a1, 0x7FFC($at)\n"
1860 "addiu $at, $a2, -0x7FF8\n"
1861 "addiu $at, $at, -0x7FF8\n"
1862 "sw $a0, -0x7FF8($at)\n"
1863 "sw $a1, -0x7FF4($at)\n"
1864 "addiu $at, $a2, -0x7FF8\n"
1865 "addiu $at, $at, -0x7FF8\n"
1866 "sw $a0, -8($at)\n"
1867 "sw $a1, -4($at)\n"
1868 "addiu $at, $a2, -0x7FF8\n"
1869 "addiu $at, $at, -0x7FF8\n"
1870 "sw $a0, -1($at)\n"
1871 "sw $a1, 3($at)\n"
1872 "addiu $at, $a2, 0x7FF8\n"
1873 "addiu $at, $at, 0x7FF8\n"
1874 "sw $a0, 1($at)\n"
1875 "sw $a1, 5($at)\n"
1876 "addiu $at, $a2, 0x7FF8\n"
1877 "addiu $at, $at, 0x7FF8\n"
1878 "sw $a0, 8($at)\n"
1879 "sw $a1, 12($at)\n"
1880 "addiu $at, $a2, 0x7FF8\n"
1881 "addiu $at, $at, 0x7FF8\n"
1882 "sw $a0, 0x7FF8($at)\n"
1883 "sw $a1, 0x7FFC($at)\n"
1884 "lui $at, 0xFFFE\n"
1885 "ori $at, $at, 0x8010\n"
1886 "addu $at, $at, $a2\n"
1887 "sw $a0, 0($at)\n"
1888 "sw $a1, 4($at)\n"
1889 "lui $at, 0xFFFE\n"
1890 "ori $at, $at, 0x8010\n"
1891 "addu $at, $at, $a2\n"
1892 "sw $a0, 7($at)\n"
1893 "sw $a1, 11($at)\n"
1894 "lui $at, 0x1\n"
1895 "ori $at, $at, 0x7FE8\n"
1896 "addu $at, $at, $a2\n"
1897 "sw $a0, 1($at)\n"
1898 "sw $a1, 5($at)\n"
1899 "lui $at, 0x1\n"
1900 "ori $at, $at, 0x7FF0\n"
1901 "addu $at, $at, $a2\n"
1902 "sw $a0, 0($at)\n"
1903 "sw $a1, 4($at)\n"
1904 "lui $at, 0x1234\n"
1905 "ori $at, $at, 0x5678\n"
1906 "addu $at, $at, $a2\n"
1907 "sw $a0, 0($at)\n"
1908 "sw $a1, 4($at)\n";
1909 DriverStr(expected, "StoreToOffset");
1910 }
1911
TEST_F(AssemblerMIPSTest,StoreSToOffset)1912 TEST_F(AssemblerMIPSTest, StoreSToOffset) {
1913 __ StoreSToOffset(mips::F2, mips::A0, -0x8000);
1914 __ StoreSToOffset(mips::F2, mips::A0, +0);
1915 __ StoreSToOffset(mips::F2, mips::A0, +0x7FF8);
1916 __ StoreSToOffset(mips::F2, mips::A0, +0x7FFB);
1917 __ StoreSToOffset(mips::F2, mips::A0, +0x7FFC);
1918 __ StoreSToOffset(mips::F2, mips::A0, +0x7FFF);
1919 __ StoreSToOffset(mips::F2, mips::A0, -0xFFF0);
1920 __ StoreSToOffset(mips::F2, mips::A0, -0x8008);
1921 __ StoreSToOffset(mips::F2, mips::A0, -0x8001);
1922 __ StoreSToOffset(mips::F2, mips::A0, +0x8000);
1923 __ StoreSToOffset(mips::F2, mips::A0, +0xFFF0);
1924 __ StoreSToOffset(mips::F2, mips::A0, -0x17FE8);
1925 __ StoreSToOffset(mips::F2, mips::A0, -0x0FFF8);
1926 __ StoreSToOffset(mips::F2, mips::A0, -0x0FFF1);
1927 __ StoreSToOffset(mips::F2, mips::A0, +0x0FFF1);
1928 __ StoreSToOffset(mips::F2, mips::A0, +0x0FFF8);
1929 __ StoreSToOffset(mips::F2, mips::A0, +0x17FE8);
1930 __ StoreSToOffset(mips::F2, mips::A0, -0x17FF0);
1931 __ StoreSToOffset(mips::F2, mips::A0, -0x17FE9);
1932 __ StoreSToOffset(mips::F2, mips::A0, +0x17FE9);
1933 __ StoreSToOffset(mips::F2, mips::A0, +0x17FF0);
1934 __ StoreSToOffset(mips::F2, mips::A0, +0x12345678);
1935
1936 const char* expected =
1937 "swc1 $f2, -0x8000($a0)\n"
1938 "swc1 $f2, 0($a0)\n"
1939 "swc1 $f2, 0x7FF8($a0)\n"
1940 "swc1 $f2, 0x7FFB($a0)\n"
1941 "swc1 $f2, 0x7FFC($a0)\n"
1942 "swc1 $f2, 0x7FFF($a0)\n"
1943 "addiu $at, $a0, -0x7FF8\n"
1944 "swc1 $f2, -0x7FF8($at)\n"
1945 "addiu $at, $a0, -0x7FF8\n"
1946 "swc1 $f2, -0x10($at)\n"
1947 "addiu $at, $a0, -0x7FF8\n"
1948 "swc1 $f2, -9($at)\n"
1949 "addiu $at, $a0, 0x7FF8\n"
1950 "swc1 $f2, 8($at)\n"
1951 "addiu $at, $a0, 0x7FF8\n"
1952 "swc1 $f2, 0x7FF8($at)\n"
1953 "addiu $at, $a0, -0x7FF8\n"
1954 "addiu $at, $at, -0x7FF8\n"
1955 "swc1 $f2, -0x7FF8($at)\n"
1956 "addiu $at, $a0, -0x7FF8\n"
1957 "addiu $at, $at, -0x7FF8\n"
1958 "swc1 $f2, -8($at)\n"
1959 "addiu $at, $a0, -0x7FF8\n"
1960 "addiu $at, $at, -0x7FF8\n"
1961 "swc1 $f2, -1($at)\n"
1962 "addiu $at, $a0, 0x7FF8\n"
1963 "addiu $at, $at, 0x7FF8\n"
1964 "swc1 $f2, 1($at)\n"
1965 "addiu $at, $a0, 0x7FF8\n"
1966 "addiu $at, $at, 0x7FF8\n"
1967 "swc1 $f2, 8($at)\n"
1968 "addiu $at, $a0, 0x7FF8\n"
1969 "addiu $at, $at, 0x7FF8\n"
1970 "swc1 $f2, 0x7FF8($at)\n"
1971 "lui $at, 0xFFFE\n"
1972 "ori $at, $at, 0x8010\n"
1973 "addu $at, $at, $a0\n"
1974 "swc1 $f2, 0($at)\n"
1975 "lui $at, 0xFFFE\n"
1976 "ori $at, $at, 0x8010\n"
1977 "addu $at, $at, $a0\n"
1978 "swc1 $f2, 7($at)\n"
1979 "lui $at, 0x1\n"
1980 "ori $at, $at, 0x7FE8\n"
1981 "addu $at, $at, $a0\n"
1982 "swc1 $f2, 1($at)\n"
1983 "lui $at, 0x1\n"
1984 "ori $at, $at, 0x7FF0\n"
1985 "addu $at, $at, $a0\n"
1986 "swc1 $f2, 0($at)\n"
1987 "lui $at, 0x1234\n"
1988 "ori $at, $at, 0x5678\n"
1989 "addu $at, $at, $a0\n"
1990 "swc1 $f2, 0($at)\n";
1991 DriverStr(expected, "StoreSToOffset");
1992 }
1993
TEST_F(AssemblerMIPSTest,StoreDToOffset)1994 TEST_F(AssemblerMIPSTest, StoreDToOffset) {
1995 __ StoreDToOffset(mips::F0, mips::A0, -0x8000);
1996 __ StoreDToOffset(mips::F0, mips::A0, +0);
1997 __ StoreDToOffset(mips::F0, mips::A0, +0x7FF8);
1998 __ StoreDToOffset(mips::F0, mips::A0, +0x7FFB);
1999 __ StoreDToOffset(mips::F0, mips::A0, +0x7FFC);
2000 __ StoreDToOffset(mips::F0, mips::A0, +0x7FFF);
2001 __ StoreDToOffset(mips::F0, mips::A0, -0xFFF0);
2002 __ StoreDToOffset(mips::F0, mips::A0, -0x8008);
2003 __ StoreDToOffset(mips::F0, mips::A0, -0x8001);
2004 __ StoreDToOffset(mips::F0, mips::A0, +0x8000);
2005 __ StoreDToOffset(mips::F0, mips::A0, +0xFFF0);
2006 __ StoreDToOffset(mips::F0, mips::A0, -0x17FE8);
2007 __ StoreDToOffset(mips::F0, mips::A0, -0x0FFF8);
2008 __ StoreDToOffset(mips::F0, mips::A0, -0x0FFF1);
2009 __ StoreDToOffset(mips::F0, mips::A0, +0x0FFF1);
2010 __ StoreDToOffset(mips::F0, mips::A0, +0x0FFF8);
2011 __ StoreDToOffset(mips::F0, mips::A0, +0x17FE8);
2012 __ StoreDToOffset(mips::F0, mips::A0, -0x17FF0);
2013 __ StoreDToOffset(mips::F0, mips::A0, -0x17FE9);
2014 __ StoreDToOffset(mips::F0, mips::A0, +0x17FE9);
2015 __ StoreDToOffset(mips::F0, mips::A0, +0x17FF0);
2016 __ StoreDToOffset(mips::F0, mips::A0, +0x12345678);
2017
2018 const char* expected =
2019 "sdc1 $f0, -0x8000($a0)\n"
2020 "sdc1 $f0, 0($a0)\n"
2021 "sdc1 $f0, 0x7FF8($a0)\n"
2022 "swc1 $f0, 0x7FFB($a0)\n"
2023 "swc1 $f1, 0x7FFF($a0)\n"
2024 "addiu $at, $a0, 0x7FF8\n"
2025 "swc1 $f0, 4($at)\n"
2026 "swc1 $f1, 8($at)\n"
2027 "addiu $at, $a0, 0x7FF8\n"
2028 "swc1 $f0, 7($at)\n"
2029 "swc1 $f1, 11($at)\n"
2030 "addiu $at, $a0, -0x7FF8\n"
2031 "sdc1 $f0, -0x7FF8($at)\n"
2032 "addiu $at, $a0, -0x7FF8\n"
2033 "sdc1 $f0, -0x10($at)\n"
2034 "addiu $at, $a0, -0x7FF8\n"
2035 "swc1 $f0, -9($at)\n"
2036 "swc1 $f1, -5($at)\n"
2037 "addiu $at, $a0, 0x7FF8\n"
2038 "sdc1 $f0, 8($at)\n"
2039 "addiu $at, $a0, 0x7FF8\n"
2040 "sdc1 $f0, 0x7FF8($at)\n"
2041 "addiu $at, $a0, -0x7FF8\n"
2042 "addiu $at, $at, -0x7FF8\n"
2043 "sdc1 $f0, -0x7FF8($at)\n"
2044 "addiu $at, $a0, -0x7FF8\n"
2045 "addiu $at, $at, -0x7FF8\n"
2046 "sdc1 $f0, -8($at)\n"
2047 "addiu $at, $a0, -0x7FF8\n"
2048 "addiu $at, $at, -0x7FF8\n"
2049 "swc1 $f0, -1($at)\n"
2050 "swc1 $f1, 3($at)\n"
2051 "addiu $at, $a0, 0x7FF8\n"
2052 "addiu $at, $at, 0x7FF8\n"
2053 "swc1 $f0, 1($at)\n"
2054 "swc1 $f1, 5($at)\n"
2055 "addiu $at, $a0, 0x7FF8\n"
2056 "addiu $at, $at, 0x7FF8\n"
2057 "sdc1 $f0, 8($at)\n"
2058 "addiu $at, $a0, 0x7FF8\n"
2059 "addiu $at, $at, 0x7FF8\n"
2060 "sdc1 $f0, 0x7FF8($at)\n"
2061 "lui $at, 0xFFFE\n"
2062 "ori $at, $at, 0x8010\n"
2063 "addu $at, $at, $a0\n"
2064 "sdc1 $f0, 0($at)\n"
2065 "lui $at, 0xFFFE\n"
2066 "ori $at, $at, 0x8010\n"
2067 "addu $at, $at, $a0\n"
2068 "swc1 $f0, 7($at)\n"
2069 "swc1 $f1, 11($at)\n"
2070 "lui $at, 0x1\n"
2071 "ori $at, $at, 0x7FE8\n"
2072 "addu $at, $at, $a0\n"
2073 "swc1 $f0, 1($at)\n"
2074 "swc1 $f1, 5($at)\n"
2075 "lui $at, 0x1\n"
2076 "ori $at, $at, 0x7FF0\n"
2077 "addu $at, $at, $a0\n"
2078 "sdc1 $f0, 0($at)\n"
2079 "lui $at, 0x1234\n"
2080 "ori $at, $at, 0x5678\n"
2081 "addu $at, $at, $a0\n"
2082 "sdc1 $f0, 0($at)\n";
2083 DriverStr(expected, "StoreDToOffset");
2084 }
2085
TEST_F(AssemblerMIPSTest,StoreConstToOffset)2086 TEST_F(AssemblerMIPSTest, StoreConstToOffset) {
2087 __ StoreConstToOffset(mips::kStoreByte, 0xFF, mips::A1, +0, mips::T8);
2088 __ StoreConstToOffset(mips::kStoreHalfword, 0xFFFF, mips::A1, +0, mips::T8);
2089 __ StoreConstToOffset(mips::kStoreWord, 0x12345678, mips::A1, +0, mips::T8);
2090 __ StoreConstToOffset(mips::kStoreDoubleword, 0x123456789ABCDEF0, mips::A1, +0, mips::T8);
2091
2092 __ StoreConstToOffset(mips::kStoreByte, 0, mips::A1, +0, mips::T8);
2093 __ StoreConstToOffset(mips::kStoreHalfword, 0, mips::A1, +0, mips::T8);
2094 __ StoreConstToOffset(mips::kStoreWord, 0, mips::A1, +0, mips::T8);
2095 __ StoreConstToOffset(mips::kStoreDoubleword, 0, mips::A1, +0, mips::T8);
2096
2097 __ StoreConstToOffset(mips::kStoreDoubleword, 0x1234567812345678, mips::A1, +0, mips::T8);
2098 __ StoreConstToOffset(mips::kStoreDoubleword, 0x1234567800000000, mips::A1, +0, mips::T8);
2099 __ StoreConstToOffset(mips::kStoreDoubleword, 0x0000000012345678, mips::A1, +0, mips::T8);
2100
2101 __ StoreConstToOffset(mips::kStoreWord, 0, mips::T8, +0, mips::T8);
2102 __ StoreConstToOffset(mips::kStoreWord, 0x12345678, mips::T8, +0, mips::T8);
2103
2104 __ StoreConstToOffset(mips::kStoreWord, 0, mips::A1, -0xFFF0, mips::T8);
2105 __ StoreConstToOffset(mips::kStoreWord, 0x12345678, mips::A1, +0xFFF0, mips::T8);
2106
2107 __ StoreConstToOffset(mips::kStoreWord, 0, mips::T8, -0xFFF0, mips::T8);
2108 __ StoreConstToOffset(mips::kStoreWord, 0x12345678, mips::T8, +0xFFF0, mips::T8);
2109
2110 const char* expected =
2111 "ori $t8, $zero, 0xFF\n"
2112 "sb $t8, 0($a1)\n"
2113 "ori $t8, $zero, 0xFFFF\n"
2114 "sh $t8, 0($a1)\n"
2115 "lui $t8, 0x1234\n"
2116 "ori $t8, $t8, 0x5678\n"
2117 "sw $t8, 0($a1)\n"
2118 "lui $t8, 0x9ABC\n"
2119 "ori $t8, $t8, 0xDEF0\n"
2120 "sw $t8, 0($a1)\n"
2121 "lui $t8, 0x1234\n"
2122 "ori $t8, $t8, 0x5678\n"
2123 "sw $t8, 4($a1)\n"
2124
2125 "sb $zero, 0($a1)\n"
2126 "sh $zero, 0($a1)\n"
2127 "sw $zero, 0($a1)\n"
2128 "sw $zero, 0($a1)\n"
2129 "sw $zero, 4($a1)\n"
2130
2131 "lui $t8, 0x1234\n"
2132 "ori $t8, $t8, 0x5678\n"
2133 "sw $t8, 0($a1)\n"
2134 "sw $t8, 4($a1)\n"
2135 "sw $zero, 0($a1)\n"
2136 "lui $t8, 0x1234\n"
2137 "ori $t8, $t8, 0x5678\n"
2138 "sw $t8, 4($a1)\n"
2139 "lui $t8, 0x1234\n"
2140 "ori $t8, $t8, 0x5678\n"
2141 "sw $t8, 0($a1)\n"
2142 "sw $zero, 4($a1)\n"
2143
2144 "sw $zero, 0($t8)\n"
2145 "lui $at, 0x1234\n"
2146 "ori $at, $at, 0x5678\n"
2147 "sw $at, 0($t8)\n"
2148
2149 "addiu $at, $a1, -0x7FF8\n"
2150 "sw $zero, -0x7FF8($at)\n"
2151 "addiu $at, $a1, 0x7FF8\n"
2152 "lui $t8, 0x1234\n"
2153 "ori $t8, $t8, 0x5678\n"
2154 "sw $t8, 0x7FF8($at)\n"
2155
2156 "addiu $at, $t8, -0x7FF8\n"
2157 "sw $zero, -0x7FF8($at)\n"
2158 "addiu $at, $t8, 0x7FF8\n"
2159 "lui $t8, 0x1234\n"
2160 "ori $t8, $t8, 0x5678\n"
2161 "sw $t8, 0x7FF8($at)\n";
2162 DriverStr(expected, "StoreConstToOffset");
2163 }
2164
2165 //////////////
2166 // BRANCHES //
2167 //////////////
2168
TEST_F(AssemblerMIPSTest,B)2169 TEST_F(AssemblerMIPSTest, B) {
2170 BranchHelper(&mips::MipsAssembler::B, "B");
2171 }
2172
TEST_F(AssemblerMIPSTest,Bal)2173 TEST_F(AssemblerMIPSTest, Bal) {
2174 BranchHelper(&mips::MipsAssembler::Bal, "Bal");
2175 }
2176
TEST_F(AssemblerMIPSTest,Beq)2177 TEST_F(AssemblerMIPSTest, Beq) {
2178 BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq");
2179 }
2180
TEST_F(AssemblerMIPSTest,Bne)2181 TEST_F(AssemblerMIPSTest, Bne) {
2182 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bne, "Bne");
2183 }
2184
TEST_F(AssemblerMIPSTest,Beqz)2185 TEST_F(AssemblerMIPSTest, Beqz) {
2186 BranchCondOneRegHelper(&mips::MipsAssembler::Beqz, "Beqz");
2187 }
2188
TEST_F(AssemblerMIPSTest,Bnez)2189 TEST_F(AssemblerMIPSTest, Bnez) {
2190 BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez");
2191 }
2192
TEST_F(AssemblerMIPSTest,Bltz)2193 TEST_F(AssemblerMIPSTest, Bltz) {
2194 BranchCondOneRegHelper(&mips::MipsAssembler::Bltz, "Bltz");
2195 }
2196
TEST_F(AssemblerMIPSTest,Bgez)2197 TEST_F(AssemblerMIPSTest, Bgez) {
2198 BranchCondOneRegHelper(&mips::MipsAssembler::Bgez, "Bgez");
2199 }
2200
TEST_F(AssemblerMIPSTest,Blez)2201 TEST_F(AssemblerMIPSTest, Blez) {
2202 BranchCondOneRegHelper(&mips::MipsAssembler::Blez, "Blez");
2203 }
2204
TEST_F(AssemblerMIPSTest,Bgtz)2205 TEST_F(AssemblerMIPSTest, Bgtz) {
2206 BranchCondOneRegHelper(&mips::MipsAssembler::Bgtz, "Bgtz");
2207 }
2208
TEST_F(AssemblerMIPSTest,Blt)2209 TEST_F(AssemblerMIPSTest, Blt) {
2210 BranchCondTwoRegsHelper(&mips::MipsAssembler::Blt, "Blt");
2211 }
2212
TEST_F(AssemblerMIPSTest,Bge)2213 TEST_F(AssemblerMIPSTest, Bge) {
2214 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bge, "Bge");
2215 }
2216
TEST_F(AssemblerMIPSTest,Bltu)2217 TEST_F(AssemblerMIPSTest, Bltu) {
2218 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltu, "Bltu");
2219 }
2220
TEST_F(AssemblerMIPSTest,Bgeu)2221 TEST_F(AssemblerMIPSTest, Bgeu) {
2222 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeu, "Bgeu");
2223 }
2224
TEST_F(AssemblerMIPSTest,Bc1f)2225 TEST_F(AssemblerMIPSTest, Bc1f) {
2226 BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1f, "Bc1f");
2227 }
2228
TEST_F(AssemblerMIPSTest,Bc1t)2229 TEST_F(AssemblerMIPSTest, Bc1t) {
2230 BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1t, "Bc1t");
2231 }
2232
TEST_F(AssemblerMIPSTest,BareB)2233 TEST_F(AssemblerMIPSTest, BareB) {
2234 BranchHelper(&mips::MipsAssembler::B, "B", /* is_bare */ true);
2235 }
2236
TEST_F(AssemblerMIPSTest,BareBal)2237 TEST_F(AssemblerMIPSTest, BareBal) {
2238 BranchHelper(&mips::MipsAssembler::Bal, "Bal", /* is_bare */ true);
2239 }
2240
TEST_F(AssemblerMIPSTest,BareBeq)2241 TEST_F(AssemblerMIPSTest, BareBeq) {
2242 BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare */ true);
2243 }
2244
TEST_F(AssemblerMIPSTest,BareBne)2245 TEST_F(AssemblerMIPSTest, BareBne) {
2246 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bne, "Bne", /* is_bare */ true);
2247 }
2248
TEST_F(AssemblerMIPSTest,BareBeqz)2249 TEST_F(AssemblerMIPSTest, BareBeqz) {
2250 BranchCondOneRegHelper(&mips::MipsAssembler::Beqz, "Beqz", /* is_bare */ true);
2251 }
2252
TEST_F(AssemblerMIPSTest,BareBnez)2253 TEST_F(AssemblerMIPSTest, BareBnez) {
2254 BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare */ true);
2255 }
2256
TEST_F(AssemblerMIPSTest,BareBltz)2257 TEST_F(AssemblerMIPSTest, BareBltz) {
2258 BranchCondOneRegHelper(&mips::MipsAssembler::Bltz, "Bltz", /* is_bare */ true);
2259 }
2260
TEST_F(AssemblerMIPSTest,BareBgez)2261 TEST_F(AssemblerMIPSTest, BareBgez) {
2262 BranchCondOneRegHelper(&mips::MipsAssembler::Bgez, "Bgez", /* is_bare */ true);
2263 }
2264
TEST_F(AssemblerMIPSTest,BareBlez)2265 TEST_F(AssemblerMIPSTest, BareBlez) {
2266 BranchCondOneRegHelper(&mips::MipsAssembler::Blez, "Blez", /* is_bare */ true);
2267 }
2268
TEST_F(AssemblerMIPSTest,BareBgtz)2269 TEST_F(AssemblerMIPSTest, BareBgtz) {
2270 BranchCondOneRegHelper(&mips::MipsAssembler::Bgtz, "Bgtz", /* is_bare */ true);
2271 }
2272
TEST_F(AssemblerMIPSTest,BareBlt)2273 TEST_F(AssemblerMIPSTest, BareBlt) {
2274 BranchCondTwoRegsHelper(&mips::MipsAssembler::Blt, "Blt", /* is_bare */ true);
2275 }
2276
TEST_F(AssemblerMIPSTest,BareBge)2277 TEST_F(AssemblerMIPSTest, BareBge) {
2278 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bge, "Bge", /* is_bare */ true);
2279 }
2280
TEST_F(AssemblerMIPSTest,BareBltu)2281 TEST_F(AssemblerMIPSTest, BareBltu) {
2282 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltu, "Bltu", /* is_bare */ true);
2283 }
2284
TEST_F(AssemblerMIPSTest,BareBgeu)2285 TEST_F(AssemblerMIPSTest, BareBgeu) {
2286 BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeu, "Bgeu", /* is_bare */ true);
2287 }
2288
TEST_F(AssemblerMIPSTest,BareBc1f)2289 TEST_F(AssemblerMIPSTest, BareBc1f) {
2290 BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1f, "Bc1f", /* is_bare */ true);
2291 }
2292
TEST_F(AssemblerMIPSTest,BareBc1t)2293 TEST_F(AssemblerMIPSTest, BareBc1t) {
2294 BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1t, "Bc1t", /* is_bare */ true);
2295 }
2296
TEST_F(AssemblerMIPSTest,ImpossibleReordering)2297 TEST_F(AssemblerMIPSTest, ImpossibleReordering) {
2298 mips::MipsLabel label1, label2;
2299 __ SetReorder(true);
2300
2301 __ B(&label1); // No preceding or target instruction for the delay slot.
2302
2303 __ Addu(mips::T0, mips::T1, mips::T2);
2304 __ Bind(&label1);
2305 __ B(&label1); // The preceding label prevents moving Addu into the delay slot.
2306 __ B(&label1); // No preceding or target instruction for the delay slot.
2307
2308 __ Addu(mips::T0, mips::T1, mips::T2);
2309 __ Beqz(mips::T0, &label1); // T0 dependency.
2310
2311 __ Or(mips::T1, mips::T2, mips::T3);
2312 __ Bne(mips::T2, mips::T1, &label1); // T1 dependency.
2313
2314 __ And(mips::T0, mips::T1, mips::T2);
2315 __ Blt(mips::T1, mips::T0, &label1); // T0 dependency.
2316
2317 __ Xor(mips::AT, mips::T0, mips::T1);
2318 __ Bge(mips::T1, mips::T0, &label1); // AT dependency.
2319
2320 __ Subu(mips::T0, mips::T1, mips::AT);
2321 __ Bltu(mips::T1, mips::T0, &label1); // AT dependency.
2322
2323 __ ColtS(1, mips::F2, mips::F4);
2324 __ Bc1t(1, &label1); // cc1 dependency.
2325
2326 __ Move(mips::T0, mips::RA);
2327 __ Bal(&label1); // RA dependency.
2328
2329 __ Lw(mips::RA, mips::T0, 0);
2330 __ Bal(&label1); // RA dependency.
2331
2332 __ LlR2(mips::T9, mips::T0, 0);
2333 __ Jalr(mips::T9); // T9 dependency.
2334
2335 __ Sw(mips::RA, mips::T0, 0);
2336 __ Jalr(mips::T9); // RA dependency.
2337
2338 __ Lw(mips::T1, mips::T0, 0);
2339 __ Jalr(mips::T1, mips::T9); // T1 dependency.
2340
2341 __ ScR2(mips::T9, mips::T0, 0);
2342 __ Jr(mips::T9); // T9 dependency.
2343
2344 __ Bind(&label2);
2345
2346 __ Bnez(mips::T0, &label2); // No preceding instruction for the delay slot.
2347
2348 __ Bgeu(mips::T1, mips::T0, &label2); // No preceding instruction for the delay slot.
2349
2350 __ Bc1f(2, &label2); // No preceding instruction for the delay slot.
2351
2352 __ Bal(&label2); // No preceding instruction for the delay slot.
2353
2354 __ Jalr(mips::T9); // No preceding instruction for the delay slot.
2355
2356 __ Addu(mips::T0, mips::T1, mips::T2);
2357 __ CodePosition(); // Drops the delay slot candidate (the last instruction).
2358 __ Beq(mips::T1, mips::T2, &label2); // No preceding or target instruction for the delay slot.
2359
2360 std::string expected =
2361 ".set noreorder\n"
2362 "b 1f\n"
2363 "nop\n"
2364
2365 "addu $t0, $t1, $t2\n"
2366 "1:\n"
2367 "b 1b\n"
2368 "nop\n"
2369 "b 1b\n"
2370 "nop\n"
2371
2372 "addu $t0, $t1, $t2\n"
2373 "beqz $t0, 1b\n"
2374 "nop\n"
2375
2376 "or $t1, $t2, $t3\n"
2377 "bne $t2, $t1, 1b\n"
2378 "nop\n"
2379
2380 "and $t0, $t1, $t2\n"
2381 "slt $at, $t1, $t0\n"
2382 "bnez $at, 1b\n"
2383 "nop\n"
2384
2385 "xor $at, $t0, $t1\n"
2386 "slt $at, $t1, $t0\n"
2387 "beqz $at, 1b\n"
2388 "nop\n"
2389
2390 "subu $t0, $t1, $at\n"
2391 "sltu $at, $t1, $t0\n"
2392 "bnez $at, 1b\n"
2393 "nop\n"
2394
2395 "c.olt.s $fcc1, $f2, $f4\n"
2396 "bc1t $fcc1, 1b\n"
2397 "nop\n"
2398
2399 "or $t0, $ra, $zero\n"
2400 "bal 1b\n"
2401 "nop\n"
2402
2403 "lw $ra, 0($t0)\n"
2404 "bal 1b\n"
2405 "nop\n"
2406
2407 "ll $t9, 0($t0)\n"
2408 "jalr $t9\n"
2409 "nop\n"
2410
2411 "sw $ra, 0($t0)\n"
2412 "jalr $t9\n"
2413 "nop\n"
2414
2415 "lw $t1, 0($t0)\n"
2416 "jalr $t1, $t9\n"
2417 "nop\n"
2418
2419 "sc $t9, 0($t0)\n"
2420 "jalr $zero, $t9\n"
2421 "nop\n"
2422
2423 "2:\n"
2424
2425 "bnez $t0, 2b\n"
2426 "nop\n"
2427
2428 "sltu $at, $t1, $t0\n"
2429 "beqz $at, 2b\n"
2430 "nop\n"
2431
2432 "bc1f $fcc2, 2b\n"
2433 "nop\n"
2434
2435 "bal 2b\n"
2436 "nop\n"
2437
2438 "jalr $t9\n"
2439 "nop\n"
2440
2441 "addu $t0, $t1, $t2\n"
2442 "beq $t1, $t2, 2b\n"
2443 "nop\n";
2444 DriverStr(expected, "ImpossibleReordering");
2445 }
2446
TEST_F(AssemblerMIPSTest,Reordering)2447 TEST_F(AssemblerMIPSTest, Reordering) {
2448 mips::MipsLabel label1, label2;
2449 __ SetReorder(true);
2450
2451 __ Bind(&label1);
2452 __ Bind(&label2);
2453
2454 __ Addu(mips::T0, mips::T1, mips::T2);
2455 __ Beqz(mips::T1, &label1);
2456
2457 __ Or(mips::T1, mips::T2, mips::T3);
2458 __ Bne(mips::T2, mips::T3, &label1);
2459
2460 __ And(mips::T0, mips::T1, mips::T2);
2461 __ Blt(mips::T1, mips::T2, &label1);
2462
2463 __ Xor(mips::T2, mips::T0, mips::T1);
2464 __ Bge(mips::T1, mips::T0, &label1);
2465
2466 __ Subu(mips::T2, mips::T1, mips::T0);
2467 __ Bltu(mips::T1, mips::T0, &label1);
2468
2469 __ ColtS(0, mips::F2, mips::F4);
2470 __ Bc1t(1, &label1);
2471
2472 __ Move(mips::T0, mips::T1);
2473 __ Bal(&label1);
2474
2475 __ LlR2(mips::T1, mips::T0, 0);
2476 __ Jalr(mips::T9);
2477
2478 __ ScR2(mips::T1, mips::T0, 0);
2479 __ Jr(mips::T9);
2480
2481 std::string expected =
2482 ".set noreorder\n"
2483 "1:\n"
2484
2485 "beqz $t1, 1b\n"
2486 "addu $t0, $t1, $t2\n"
2487
2488 "bne $t2, $t3, 1b\n"
2489 "or $t1, $t2, $t3\n"
2490
2491 "slt $at, $t1, $t2\n"
2492 "bnez $at, 1b\n"
2493 "and $t0, $t1, $t2\n"
2494
2495 "slt $at, $t1, $t0\n"
2496 "beqz $at, 1b\n"
2497 "xor $t2, $t0, $t1\n"
2498
2499 "sltu $at, $t1, $t0\n"
2500 "bnez $at, 1b\n"
2501 "subu $t2, $t1, $t0\n"
2502
2503 "bc1t $fcc1, 1b\n"
2504 "c.olt.s $fcc0, $f2, $f4\n"
2505
2506 "bal 1b\n"
2507 "or $t0, $t1, $zero\n"
2508
2509 "jalr $t9\n"
2510 "ll $t1, 0($t0)\n"
2511
2512 "jalr $zero, $t9\n"
2513 "sc $t1, 0($t0)\n";
2514 DriverStr(expected, "Reordering");
2515 }
2516
TEST_F(AssemblerMIPSTest,AbsorbTargetInstruction)2517 TEST_F(AssemblerMIPSTest, AbsorbTargetInstruction) {
2518 mips::MipsLabel label1, label2, label3, label4, label5, label6;
2519 mips::MipsLabel label7, label8, label9, label10, label11, label12, label13;
2520 __ SetReorder(true);
2521
2522 __ B(&label1);
2523 __ Bind(&label1);
2524 __ Addu(mips::T0, mips::T1, mips::T2);
2525
2526 __ Bind(&label2);
2527 __ Xor(mips::T0, mips::T1, mips::T2);
2528 __ Addu(mips::T0, mips::T1, mips::T2);
2529 __ Bind(&label3); // Prevents reordering ADDU above with B below.
2530 __ B(&label2);
2531
2532 __ B(&label4);
2533 __ Bind(&label4);
2534 __ Addu(mips::T0, mips::T1, mips::T2);
2535 __ CodePosition(); // Prevents absorbing ADDU above.
2536
2537 __ B(&label5);
2538 __ Bind(&label5);
2539 __ Addu(mips::T0, mips::T1, mips::T2);
2540 __ Bind(&label6);
2541 __ CodePosition(); // Even across Bind(), CodePosition() prevents absorbing the ADDU above.
2542
2543 __ Nop();
2544 __ B(&label7);
2545 __ Bind(&label7);
2546 __ Lw(mips::V0, mips::A0, 0x5678); // Possibly patchable instruction, not absorbed.
2547
2548 __ Nop();
2549 __ B(&label8);
2550 __ Bind(&label8);
2551 __ Sw(mips::V0, mips::A0, 0x5678); // Possibly patchable instruction, not absorbed.
2552
2553 __ Nop();
2554 __ B(&label9);
2555 __ Bind(&label9);
2556 __ Addiu(mips::V0, mips::A0, 0x5678); // Possibly patchable instruction, not absorbed.
2557
2558 __ Nop();
2559 __ B(&label10);
2560 __ Bind(&label10);
2561 __ Lw(mips::V0, mips::A0, 0x5680); // Immediate isn't 0x5678, absorbed.
2562
2563 __ Nop();
2564 __ B(&label11);
2565 __ Bind(&label11);
2566 __ Sw(mips::V0, mips::A0, 0x5680); // Immediate isn't 0x5678, absorbed.
2567
2568 __ Nop();
2569 __ B(&label12);
2570 __ Bind(&label12);
2571 __ Addiu(mips::V0, mips::A0, 0x5680); // Immediate isn't 0x5678, absorbed.
2572
2573 __ Nop();
2574 __ B(&label13);
2575 __ Bind(&label13);
2576 __ Andi(mips::V0, mips::A0, 0x5678); // Not one of patchable instructions, absorbed.
2577
2578 std::string expected =
2579 ".set noreorder\n"
2580 "b 1f\n"
2581 "addu $t0, $t1, $t2\n"
2582 "addu $t0, $t1, $t2\n"
2583 "1:\n"
2584
2585 "xor $t0, $t1, $t2\n"
2586 "2:\n"
2587 "addu $t0, $t1, $t2\n"
2588 "b 2b\n"
2589 "xor $t0, $t1, $t2\n"
2590
2591 "b 4f\n"
2592 "nop\n"
2593 "4:\n"
2594 "addu $t0, $t1, $t2\n"
2595
2596 "b 5f\n"
2597 "nop\n"
2598 "5:\n"
2599 "addu $t0, $t1, $t2\n"
2600
2601 "nop\n"
2602 "b 7f\n"
2603 "nop\n"
2604 "7:\n"
2605 "lw $v0, 0x5678($a0)\n"
2606
2607 "nop\n"
2608 "b 8f\n"
2609 "nop\n"
2610 "8:\n"
2611 "sw $v0, 0x5678($a0)\n"
2612
2613 "nop\n"
2614 "b 9f\n"
2615 "nop\n"
2616 "9:\n"
2617 "addiu $v0, $a0, 0x5678\n"
2618
2619 "nop\n"
2620 "b 10f\n"
2621 "lw $v0, 0x5680($a0)\n"
2622 "lw $v0, 0x5680($a0)\n"
2623 "10:\n"
2624
2625 "nop\n"
2626 "b 11f\n"
2627 "sw $v0, 0x5680($a0)\n"
2628 "sw $v0, 0x5680($a0)\n"
2629 "11:\n"
2630
2631 "nop\n"
2632 "b 12f\n"
2633 "addiu $v0, $a0, 0x5680\n"
2634 "addiu $v0, $a0, 0x5680\n"
2635 "12:\n"
2636
2637 "nop\n"
2638 "b 13f\n"
2639 "andi $v0, $a0, 0x5678\n"
2640 "andi $v0, $a0, 0x5678\n"
2641 "13:\n";
2642 DriverStr(expected, "AbsorbTargetInstruction");
2643 }
2644
TEST_F(AssemblerMIPSTest,SetReorder)2645 TEST_F(AssemblerMIPSTest, SetReorder) {
2646 mips::MipsLabel label1, label2, label3, label4, label5, label6;
2647
2648 __ SetReorder(true);
2649 __ Bind(&label1);
2650 __ Addu(mips::T0, mips::T1, mips::T2);
2651 __ B(&label1);
2652 __ B(&label5);
2653 __ B(&label6);
2654
2655 __ SetReorder(false);
2656 __ Bind(&label2);
2657 __ Addu(mips::T0, mips::T1, mips::T2);
2658 __ B(&label2);
2659 __ B(&label5);
2660 __ B(&label6);
2661
2662 __ SetReorder(true);
2663 __ Bind(&label3);
2664 __ Addu(mips::T0, mips::T1, mips::T2);
2665 __ B(&label3);
2666 __ B(&label5);
2667 __ B(&label6);
2668
2669 __ SetReorder(false);
2670 __ Bind(&label4);
2671 __ Addu(mips::T0, mips::T1, mips::T2);
2672 __ B(&label4);
2673 __ B(&label5);
2674 __ B(&label6);
2675
2676 __ SetReorder(true);
2677 __ Bind(&label5);
2678 __ Subu(mips::T0, mips::T1, mips::T2);
2679
2680 __ SetReorder(false);
2681 __ Bind(&label6);
2682 __ Xor(mips::T0, mips::T1, mips::T2);
2683
2684 std::string expected =
2685 ".set noreorder\n"
2686 "1:\n"
2687 "b 1b\n"
2688 "addu $t0, $t1, $t2\n"
2689 "b 55f\n"
2690 "subu $t0, $t1, $t2\n"
2691 "b 6f\n"
2692 "nop\n"
2693
2694 "2:\n"
2695 "addu $t0, $t1, $t2\n"
2696 "b 2b\n"
2697 "nop\n"
2698 "b 5f\n"
2699 "nop\n"
2700 "b 6f\n"
2701 "nop\n"
2702
2703 "3:\n"
2704 "b 3b\n"
2705 "addu $t0, $t1, $t2\n"
2706 "b 55f\n"
2707 "subu $t0, $t1, $t2\n"
2708 "b 6f\n"
2709 "nop\n"
2710
2711 "4:\n"
2712 "addu $t0, $t1, $t2\n"
2713 "b 4b\n"
2714 "nop\n"
2715 "b 5f\n"
2716 "nop\n"
2717 "b 6f\n"
2718 "nop\n"
2719
2720 "5:\n"
2721 "subu $t0, $t1, $t2\n"
2722 "55:\n"
2723 "6:\n"
2724 "xor $t0, $t1, $t2\n";
2725 DriverStr(expected, "SetReorder");
2726 }
2727
TEST_F(AssemblerMIPSTest,ReorderPatchedInstruction)2728 TEST_F(AssemblerMIPSTest, ReorderPatchedInstruction) {
2729 __ SetReorder(true);
2730 mips::MipsLabel label1, label2;
2731 mips::MipsLabel patcher_label1, patcher_label2, patcher_label3, patcher_label4, patcher_label5;
2732 __ Lw(mips::V0, mips::A0, 0x5678, &patcher_label1);
2733 __ Beq(mips::A0, mips::A1, &label1);
2734 constexpr uint32_t kAdduCount1 = 63;
2735 for (size_t i = 0; i != kAdduCount1; ++i) {
2736 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2737 }
2738 __ Bind(&label1);
2739 __ Sw(mips::V0, mips::A0, 0x5678, &patcher_label2);
2740 __ Bltz(mips::V1, &label2);
2741 constexpr uint32_t kAdduCount2 = 64;
2742 for (size_t i = 0; i != kAdduCount2; ++i) {
2743 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2744 }
2745 __ Bind(&label2);
2746 __ Addiu(mips::V0, mips::A0, 0x5678, &patcher_label3);
2747 __ B(&label1);
2748 __ Lw(mips::V0, mips::A0, 0x5678, &patcher_label4);
2749 __ Jalr(mips::T9);
2750 __ Sw(mips::V0, mips::A0, 0x5678, &patcher_label5);
2751 __ Blt(mips::V0, mips::V1, &label2);
2752 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2753
2754 std::string expected =
2755 ".set noreorder\n"
2756 "beq $a0, $a1, 1f\n"
2757 "lw $v0, 0x5678($a0)\n" +
2758 RepeatInsn(kAdduCount1, "addu $zero, $zero, $zero\n") +
2759 "1:\n"
2760 "bltz $v1, 2f\n"
2761 "sw $v0, 0x5678($a0)\n" +
2762 RepeatInsn(kAdduCount2, "addu $zero, $zero, $zero\n") +
2763 "2:\n"
2764 "b 1b\n"
2765 "addiu $v0, $a0, 0x5678\n"
2766 "jalr $t9\n"
2767 "lw $v0, 0x5678($a0)\n"
2768 "slt $at, $v0, $v1\n"
2769 "bnez $at, 2b\n"
2770 "sw $v0, 0x5678($a0)\n"
2771 "addu $zero, $zero, $zero\n";
2772 DriverStr(expected, "ReorderPatchedInstruction");
2773 EXPECT_EQ(__ GetLabelLocation(&patcher_label1), 1 * 4u);
2774 EXPECT_EQ(__ GetLabelLocation(&patcher_label2), (kAdduCount1 + 3) * 4u);
2775 EXPECT_EQ(__ GetLabelLocation(&patcher_label3), (kAdduCount1 + kAdduCount2 + 5) * 4u);
2776 EXPECT_EQ(__ GetLabelLocation(&patcher_label4), (kAdduCount1 + kAdduCount2 + 7) * 4u);
2777 EXPECT_EQ(__ GetLabelLocation(&patcher_label5), (kAdduCount1 + kAdduCount2 + 10) * 4u);
2778 }
2779
TEST_F(AssemblerMIPSTest,LongBranchReorder)2780 TEST_F(AssemblerMIPSTest, LongBranchReorder) {
2781 mips::MipsLabel label, patcher_label1, patcher_label2;
2782 __ SetReorder(true);
2783 __ Addiu(mips::T0, mips::T1, 0x5678, &patcher_label1);
2784 __ B(&label);
2785 constexpr uint32_t kAdduCount1 = (1u << 15) + 1;
2786 for (size_t i = 0; i != kAdduCount1; ++i) {
2787 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2788 }
2789 __ Bind(&label);
2790 constexpr uint32_t kAdduCount2 = (1u << 15) + 1;
2791 for (size_t i = 0; i != kAdduCount2; ++i) {
2792 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2793 }
2794 __ Addiu(mips::T0, mips::T1, 0x5678, &patcher_label2);
2795 __ B(&label);
2796
2797 // Account for 5 extra instructions: ori, addu, lw, jalr, addiu.
2798 uint32_t offset_forward = (kAdduCount1 + 5) * sizeof(uint32_t);
2799 // Account for 5 extra instructions: subu, addiu, sw, nal, lui.
2800 uint32_t offset_back = static_cast<uint32_t>(-(kAdduCount1 + 5) * sizeof(uint32_t));
2801
2802 std::ostringstream oss;
2803 oss <<
2804 ".set noreorder\n"
2805 "addiu $t0, $t1, 0x5678\n"
2806 "addiu $sp, $sp, -16\n"
2807 "sw $ra, 0($sp)\n"
2808 "bltzal $zero, .+4\n"
2809 "lui $at, 0x" << std::hex << High16Bits(offset_forward) << "\n"
2810 "ori $at, $at, 0x" << std::hex << Low16Bits(offset_forward) << "\n"
2811 "addu $at, $at, $ra\n"
2812 "lw $ra, 0($sp)\n"
2813 "jalr $zero, $at\n"
2814 "addiu $sp, $sp, 16\n" <<
2815 RepeatInsn(kAdduCount1, "addu $zero, $zero, $zero\n") <<
2816 RepeatInsn(kAdduCount2, "addu $zero, $zero, $zero\n") <<
2817 "addiu $t0, $t1, 0x5678\n"
2818 "addiu $sp, $sp, -16\n"
2819 "sw $ra, 0($sp)\n"
2820 "bltzal $zero, .+4\n"
2821 "lui $at, 0x" << std::hex << High16Bits(offset_back) << "\n"
2822 "ori $at, $at, 0x" << std::hex << Low16Bits(offset_back) << "\n"
2823 "addu $at, $at, $ra\n"
2824 "lw $ra, 0($sp)\n"
2825 "jalr $zero, $at\n"
2826 "addiu $sp, $sp, 16\n";
2827 std::string expected = oss.str();
2828 DriverStr(expected, "LongBranchReorder");
2829 EXPECT_EQ(__ GetLabelLocation(&patcher_label1), 0 * 4u);
2830 EXPECT_EQ(__ GetLabelLocation(&patcher_label2), (kAdduCount1 + kAdduCount2 + 10) * 4u);
2831 }
2832
2833 ///////////////////////
2834 // Loading Constants //
2835 ///////////////////////
2836
TEST_F(AssemblerMIPSTest,LoadConst32)2837 TEST_F(AssemblerMIPSTest, LoadConst32) {
2838 // IsUint<16>(value)
2839 __ LoadConst32(mips::V0, 0);
2840 __ LoadConst32(mips::V0, 65535);
2841 // IsInt<16>(value)
2842 __ LoadConst32(mips::V0, -1);
2843 __ LoadConst32(mips::V0, -32768);
2844 // Everything else
2845 __ LoadConst32(mips::V0, 65536);
2846 __ LoadConst32(mips::V0, 65537);
2847 __ LoadConst32(mips::V0, 2147483647);
2848 __ LoadConst32(mips::V0, -32769);
2849 __ LoadConst32(mips::V0, -65536);
2850 __ LoadConst32(mips::V0, -65537);
2851 __ LoadConst32(mips::V0, -2147483647);
2852 __ LoadConst32(mips::V0, -2147483648);
2853
2854 const char* expected =
2855 // IsUint<16>(value)
2856 "ori $v0, $zero, 0\n" // __ LoadConst32(mips::V0, 0);
2857 "ori $v0, $zero, 65535\n" // __ LoadConst32(mips::V0, 65535);
2858 // IsInt<16>(value)
2859 "addiu $v0, $zero, -1\n" // __ LoadConst32(mips::V0, -1);
2860 "addiu $v0, $zero, -32768\n" // __ LoadConst32(mips::V0, -32768);
2861 // Everything else
2862 "lui $v0, 1\n" // __ LoadConst32(mips::V0, 65536);
2863 "lui $v0, 1\n" // __ LoadConst32(mips::V0, 65537);
2864 "ori $v0, 1\n" // "
2865 "lui $v0, 32767\n" // __ LoadConst32(mips::V0, 2147483647);
2866 "ori $v0, 65535\n" // "
2867 "lui $v0, 65535\n" // __ LoadConst32(mips::V0, -32769);
2868 "ori $v0, 32767\n" // "
2869 "lui $v0, 65535\n" // __ LoadConst32(mips::V0, -65536);
2870 "lui $v0, 65534\n" // __ LoadConst32(mips::V0, -65537);
2871 "ori $v0, 65535\n" // "
2872 "lui $v0, 32768\n" // __ LoadConst32(mips::V0, -2147483647);
2873 "ori $v0, 1\n" // "
2874 "lui $v0, 32768\n"; // __ LoadConst32(mips::V0, -2147483648);
2875 DriverStr(expected, "LoadConst32");
2876 }
2877
TEST_F(AssemblerMIPSTest,LoadFarthestNearLabelAddress)2878 TEST_F(AssemblerMIPSTest, LoadFarthestNearLabelAddress) {
2879 mips::MipsLabel label;
2880 __ BindPcRelBaseLabel();
2881 __ LoadLabelAddress(mips::V0, mips::V1, &label);
2882 constexpr size_t kAddiuCount = 0x1FDE;
2883 for (size_t i = 0; i != kAddiuCount; ++i) {
2884 __ Addiu(mips::A0, mips::A1, 0);
2885 }
2886 __ Bind(&label);
2887
2888 std::string expected =
2889 "1:\n"
2890 "addiu $v0, $v1, %lo(2f - 1b)\n" +
2891 RepeatInsn(kAddiuCount, "addiu $a0, $a1, %hi(2f - 1b)\n") +
2892 "2:\n";
2893 DriverStr(expected, "LoadFarthestNearLabelAddress");
2894 }
2895
TEST_F(AssemblerMIPSTest,LoadNearestFarLabelAddress)2896 TEST_F(AssemblerMIPSTest, LoadNearestFarLabelAddress) {
2897 mips::MipsLabel label;
2898 __ BindPcRelBaseLabel();
2899 __ LoadLabelAddress(mips::V0, mips::V1, &label);
2900 constexpr size_t kAdduCount = 0x1FDF;
2901 for (size_t i = 0; i != kAdduCount; ++i) {
2902 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2903 }
2904 __ Bind(&label);
2905
2906 std::string expected =
2907 "1:\n"
2908 "lui $at, %hi(2f - 1b)\n"
2909 "ori $at, $at, %lo(2f - 1b)\n"
2910 "addu $v0, $at, $v1\n" +
2911 RepeatInsn(kAdduCount, "addu $zero, $zero, $zero\n") +
2912 "2:\n";
2913 DriverStr(expected, "LoadNearestFarLabelAddress");
2914 }
2915
TEST_F(AssemblerMIPSTest,LoadFarthestNearLabelAddressUsingNal)2916 TEST_F(AssemblerMIPSTest, LoadFarthestNearLabelAddressUsingNal) {
2917 mips::MipsLabel label;
2918 __ LoadLabelAddress(mips::V0, mips::ZERO, &label);
2919 constexpr size_t kAddiuCount = 0x1FDE;
2920 for (size_t i = 0; i != kAddiuCount; ++i) {
2921 __ Addiu(mips::A0, mips::A1, 0);
2922 }
2923 __ Bind(&label);
2924
2925 std::string expected =
2926 ".set noreorder\n"
2927 "bltzal $zero, .+4\n"
2928 "addiu $v0, $ra, %lo(2f - 1f)\n"
2929 "1:\n" +
2930 RepeatInsn(kAddiuCount, "addiu $a0, $a1, %hi(2f - 1b)\n") +
2931 "2:\n";
2932 DriverStr(expected, "LoadFarthestNearLabelAddressUsingNal");
2933 }
2934
TEST_F(AssemblerMIPSTest,LoadNearestFarLabelAddressUsingNal)2935 TEST_F(AssemblerMIPSTest, LoadNearestFarLabelAddressUsingNal) {
2936 mips::MipsLabel label;
2937 __ LoadLabelAddress(mips::V0, mips::ZERO, &label);
2938 constexpr size_t kAdduCount = 0x1FDF;
2939 for (size_t i = 0; i != kAdduCount; ++i) {
2940 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2941 }
2942 __ Bind(&label);
2943
2944 std::string expected =
2945 ".set noreorder\n"
2946 "bltzal $zero, .+4\n"
2947 "lui $at, %hi(2f - 1f)\n"
2948 "1:\n"
2949 "ori $at, $at, %lo(2f - 1b)\n"
2950 "addu $v0, $at, $ra\n" +
2951 RepeatInsn(kAdduCount, "addu $zero, $zero, $zero\n") +
2952 "2:\n";
2953 DriverStr(expected, "LoadNearestFarLabelAddressUsingNal");
2954 }
2955
TEST_F(AssemblerMIPSTest,LoadFarthestNearLiteral)2956 TEST_F(AssemblerMIPSTest, LoadFarthestNearLiteral) {
2957 mips::Literal* literal = __ NewLiteral<uint32_t>(0x12345678);
2958 __ BindPcRelBaseLabel();
2959 __ LoadLiteral(mips::V0, mips::V1, literal);
2960 constexpr size_t kAddiuCount = 0x1FDE;
2961 for (size_t i = 0; i != kAddiuCount; ++i) {
2962 __ Addiu(mips::A0, mips::A1, 0);
2963 }
2964
2965 std::string expected =
2966 "1:\n"
2967 "lw $v0, %lo(2f - 1b)($v1)\n" +
2968 RepeatInsn(kAddiuCount, "addiu $a0, $a1, %hi(2f - 1b)\n") +
2969 "2:\n"
2970 ".word 0x12345678\n";
2971 DriverStr(expected, "LoadFarthestNearLiteral");
2972 }
2973
TEST_F(AssemblerMIPSTest,LoadNearestFarLiteral)2974 TEST_F(AssemblerMIPSTest, LoadNearestFarLiteral) {
2975 mips::Literal* literal = __ NewLiteral<uint32_t>(0x12345678);
2976 __ BindPcRelBaseLabel();
2977 __ LoadLiteral(mips::V0, mips::V1, literal);
2978 constexpr size_t kAdduCount = 0x1FDF;
2979 for (size_t i = 0; i != kAdduCount; ++i) {
2980 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
2981 }
2982
2983 std::string expected =
2984 "1:\n"
2985 "lui $at, %hi(2f - 1b)\n"
2986 "addu $at, $at, $v1\n"
2987 "lw $v0, %lo(2f - 1b)($at)\n" +
2988 RepeatInsn(kAdduCount, "addu $zero, $zero, $zero\n") +
2989 "2:\n"
2990 ".word 0x12345678\n";
2991 DriverStr(expected, "LoadNearestFarLiteral");
2992 }
2993
TEST_F(AssemblerMIPSTest,LoadFarthestNearLiteralUsingNal)2994 TEST_F(AssemblerMIPSTest, LoadFarthestNearLiteralUsingNal) {
2995 mips::Literal* literal = __ NewLiteral<uint32_t>(0x12345678);
2996 __ LoadLiteral(mips::V0, mips::ZERO, literal);
2997 constexpr size_t kAddiuCount = 0x1FDE;
2998 for (size_t i = 0; i != kAddiuCount; ++i) {
2999 __ Addiu(mips::A0, mips::A1, 0);
3000 }
3001
3002 std::string expected =
3003 ".set noreorder\n"
3004 "bltzal $zero, .+4\n"
3005 "lw $v0, %lo(2f - 1f)($ra)\n"
3006 "1:\n" +
3007 RepeatInsn(kAddiuCount, "addiu $a0, $a1, %hi(2f - 1b)\n") +
3008 "2:\n"
3009 ".word 0x12345678\n";
3010 DriverStr(expected, "LoadFarthestNearLiteralUsingNal");
3011 }
3012
TEST_F(AssemblerMIPSTest,LoadNearestFarLiteralUsingNal)3013 TEST_F(AssemblerMIPSTest, LoadNearestFarLiteralUsingNal) {
3014 mips::Literal* literal = __ NewLiteral<uint32_t>(0x12345678);
3015 __ LoadLiteral(mips::V0, mips::ZERO, literal);
3016 constexpr size_t kAdduCount = 0x1FDF;
3017 for (size_t i = 0; i != kAdduCount; ++i) {
3018 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
3019 }
3020
3021 std::string expected =
3022 ".set noreorder\n"
3023 "bltzal $zero, .+4\n"
3024 "lui $at, %hi(2f - 1f)\n"
3025 "1:\n"
3026 "addu $at, $at, $ra\n"
3027 "lw $v0, %lo(2f - 1b)($at)\n" +
3028 RepeatInsn(kAdduCount, "addu $zero, $zero, $zero\n") +
3029 "2:\n"
3030 ".word 0x12345678\n";
3031 DriverStr(expected, "LoadNearestFarLiteralUsingNal");
3032 }
3033
3034 #undef __
3035
3036 } // namespace art
3037