1 /*
2  * Copyright 2005 Stephane Marchesin.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
27 
28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29 
30 /* reserved object handles when using deprecated object APIs - these
31  * are here so that libdrm can allow interoperability with the new
32  * object APIs
33  */
34 #define NOUVEAU_ABI16_CLIENT   0xffffffff
35 #define NOUVEAU_ABI16_DEVICE   0xdddddddd
36 #define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n))
37 
38 struct drm_nouveau_channel_alloc {
39 	uint32_t     fb_ctxdma_handle;
40 	uint32_t     tt_ctxdma_handle;
41 
42 	int          channel;
43 	uint32_t     pushbuf_domains;
44 
45 	/* Notifier memory */
46 	uint32_t     notifier_handle;
47 
48 	/* DRM-enforced subchannel assignments */
49 	struct {
50 		uint32_t handle;
51 		uint32_t grclass;
52 	} subchan[8];
53 	uint32_t nr_subchan;
54 };
55 
56 struct drm_nouveau_channel_free {
57 	int channel;
58 };
59 
60 struct drm_nouveau_grobj_alloc {
61 	int      channel;
62 	uint32_t handle;
63 	int      class;
64 };
65 
66 struct drm_nouveau_notifierobj_alloc {
67 	uint32_t channel;
68 	uint32_t handle;
69 	uint32_t size;
70 	uint32_t offset;
71 };
72 
73 struct drm_nouveau_gpuobj_free {
74 	int      channel;
75 	uint32_t handle;
76 };
77 
78 /* FIXME : maybe unify {GET,SET}PARAMs */
79 #define NOUVEAU_GETPARAM_PCI_VENDOR      3
80 #define NOUVEAU_GETPARAM_PCI_DEVICE      4
81 #define NOUVEAU_GETPARAM_BUS_TYPE        5
82 #define NOUVEAU_GETPARAM_FB_PHYSICAL     6
83 #define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
84 #define NOUVEAU_GETPARAM_FB_SIZE         8
85 #define NOUVEAU_GETPARAM_AGP_SIZE        9
86 #define NOUVEAU_GETPARAM_PCI_PHYSICAL    10
87 #define NOUVEAU_GETPARAM_CHIPSET_ID      11
88 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
89 #define NOUVEAU_GETPARAM_GRAPH_UNITS     13
90 #define NOUVEAU_GETPARAM_PTIMER_TIME     14
91 #define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
92 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
93 struct drm_nouveau_getparam {
94 	uint64_t param;
95 	uint64_t value;
96 };
97 
98 struct drm_nouveau_setparam {
99 	uint64_t param;
100 	uint64_t value;
101 };
102 
103 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
104 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
105 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
106 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
107 #define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
108 
109 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
110 #define NOUVEAU_GEM_TILE_16BPP       0x00000001
111 #define NOUVEAU_GEM_TILE_32BPP       0x00000002
112 #define NOUVEAU_GEM_TILE_ZETA        0x00000004
113 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
114 
115 struct drm_nouveau_gem_info {
116 	uint32_t handle;
117 	uint32_t domain;
118 	uint64_t size;
119 	uint64_t offset;
120 	uint64_t map_handle;
121 	uint32_t tile_mode;
122 	uint32_t tile_flags;
123 };
124 
125 struct drm_nouveau_gem_set_tiling {
126 	uint32_t handle;
127 	uint32_t tile_mode;
128 	uint32_t tile_flags;
129 };
130 
131 struct drm_nouveau_gem_new {
132 	struct drm_nouveau_gem_info info;
133 	uint32_t channel_hint;
134 	uint32_t align;
135 };
136 
137 #define NOUVEAU_GEM_MAX_BUFFERS 1024
138 struct drm_nouveau_gem_pushbuf_bo_presumed {
139 	uint32_t valid;
140 	uint32_t domain;
141 	uint64_t offset;
142 };
143 
144 struct drm_nouveau_gem_pushbuf_bo {
145 	uint64_t user_priv;
146 	uint32_t handle;
147 	uint32_t read_domains;
148 	uint32_t write_domains;
149 	uint32_t valid_domains;
150 	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
151 };
152 
153 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
154 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
155 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
156 #define NOUVEAU_GEM_MAX_RELOCS 1024
157 struct drm_nouveau_gem_pushbuf_reloc {
158 	uint32_t reloc_bo_index;
159 	uint32_t reloc_bo_offset;
160 	uint32_t bo_index;
161 	uint32_t flags;
162 	uint32_t data;
163 	uint32_t vor;
164 	uint32_t tor;
165 };
166 
167 #define NOUVEAU_GEM_MAX_PUSH 512
168 struct drm_nouveau_gem_pushbuf_push {
169 	uint32_t bo_index;
170 	uint32_t pad;
171 	uint64_t offset;
172 	uint64_t length;
173 };
174 
175 struct drm_nouveau_gem_pushbuf {
176 	uint32_t channel;
177 	uint32_t nr_buffers;
178 	uint64_t buffers;
179 	uint32_t nr_relocs;
180 	uint32_t nr_push;
181 	uint64_t relocs;
182 	uint64_t push;
183 	uint32_t suffix0;
184 	uint32_t suffix1;
185 	uint64_t vram_available;
186 	uint64_t gart_available;
187 };
188 
189 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT                             0x00000001
190 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT                             0x00000002
191 struct drm_nouveau_gem_pushbuf_2 {
192 	uint32_t channel;
193 	uint32_t flags;
194 	uint32_t nr_push;
195 	uint32_t nr_buffers;
196 	int32_t  fence; /* in/out, depends on flags */
197 	uint32_t pad;
198 	uint64_t push; /* in raw hw format */
199 	uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */
200 	uint64_t vram_available;
201 	uint64_t gart_available;
202 };
203 
204 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
205 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK                                 0x00000002
206 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
207 struct drm_nouveau_gem_cpu_prep {
208 	uint32_t handle;
209 	uint32_t flags;
210 };
211 
212 struct drm_nouveau_gem_cpu_fini {
213 	uint32_t handle;
214 };
215 
216 #define NOUVEAU_GEM_AS_SPARSE	0x00000001
217 struct drm_nouveau_gem_as_alloc {
218 	uint64_t pages;     /* in, page length */
219 	uint32_t page_size; /* in, byte page size */
220 	uint32_t flags; /* in, flags of address space */
221 	uint64_t align; /* in, requested alignment in bytes */
222 	uint64_t address; /* in/out, non-zero for fixed address allocation */
223 };
224 
225 struct drm_nouveau_gem_as_free {
226 	uint64_t address;   /* in, byte address */
227 };
228 
229 enum nouveau_bus_type {
230 	NV_AGP     = 0,
231 	NV_PCI     = 1,
232 	NV_PCIE    = 2,
233 };
234 
235 struct drm_nouveau_sarea {
236 };
237 
238 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT	8
239 #define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY		13
240 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT	31
241 #define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR			32
242 struct drm_nouveau_gem_set_error_notifier {
243 	uint32_t channel;
244 	uint32_t buffer;
245 	uint32_t offset; /* in bytes, u32-aligned */
246 };
247 
248 struct drm_nouveau_gem_map {
249 	uint32_t handle;
250 	uint32_t domain;
251 	uint64_t offset;
252 	uint64_t delta;
253 	uint64_t length;
254 	uint32_t tile_mode;
255 	uint32_t tile_flags;
256 };
257 
258 struct drm_nouveau_gem_unmap {
259 	uint32_t handle;
260 	uint32_t pad;
261 	uint64_t offset;
262 	uint64_t delta;
263 	uint64_t length;
264 };
265 
266 #define DRM_NOUVEAU_GETPARAM           0x00
267 #define DRM_NOUVEAU_SETPARAM           0x01
268 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02
269 #define DRM_NOUVEAU_CHANNEL_FREE       0x03
270 #define DRM_NOUVEAU_GROBJ_ALLOC        0x04
271 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05
272 #define DRM_NOUVEAU_GPUOBJ_FREE        0x06
273 #define DRM_NOUVEAU_NVIF               0x07
274 #define DRM_NOUVEAU_GEM_NEW            0x40
275 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
276 #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
277 #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
278 #define DRM_NOUVEAU_GEM_INFO           0x44
279 
280 /* The ioctls below are marked as staging */
281 #define DRM_NOUVEAU_GEM_SET_TILING     0x50
282 #define DRM_NOUVEAU_GEM_PUSHBUF_2      0x51
283 #define DRM_NOUVEAU_GEM_SET_INFO       0x52
284 #define DRM_NOUVEAU_GEM_AS_ALLOC       0x53
285 #define DRM_NOUVEAU_GEM_AS_FREE        0x54
286 #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER 0x55
287 #define DRM_NOUVEAU_GEM_MAP            0x56
288 #define DRM_NOUVEAU_GEM_UNMAP          0x57
289 
290 #endif /* __NOUVEAU_DRM_H__ */
291