1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAGISel class, which is used as the common 11 // base class for SelectionDAG-based instruction selectors. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H 17 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/IR/BasicBlock.h" 21 #include "llvm/Pass.h" 22 #include "llvm/Target/TargetSubtargetInfo.h" 23 24 namespace llvm { 25 class FastISel; 26 class SelectionDAGBuilder; 27 class SDValue; 28 class MachineRegisterInfo; 29 class MachineBasicBlock; 30 class MachineFunction; 31 class MachineInstr; 32 class TargetLowering; 33 class TargetLibraryInfo; 34 class FunctionLoweringInfo; 35 class ScheduleHazardRecognizer; 36 class GCFunctionInfo; 37 class ScheduleDAGSDNodes; 38 class LoadInst; 39 40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 41 /// pattern-matching instruction selectors. 42 class SelectionDAGISel : public MachineFunctionPass { 43 public: 44 TargetMachine &TM; 45 const TargetLibraryInfo *LibInfo; 46 FunctionLoweringInfo *FuncInfo; 47 MachineFunction *MF; 48 MachineRegisterInfo *RegInfo; 49 SelectionDAG *CurDAG; 50 SelectionDAGBuilder *SDB; 51 AliasAnalysis *AA; 52 GCFunctionInfo *GFI; 53 CodeGenOpt::Level OptLevel; 54 const TargetInstrInfo *TII; 55 const TargetLowering *TLI; 56 57 static char ID; 58 59 explicit SelectionDAGISel(TargetMachine &tm, 60 CodeGenOpt::Level OL = CodeGenOpt::Default); 61 ~SelectionDAGISel() override; 62 getTargetLowering()63 const TargetLowering *getTargetLowering() const { return TLI; } 64 65 void getAnalysisUsage(AnalysisUsage &AU) const override; 66 67 bool runOnMachineFunction(MachineFunction &MF) override; 68 EmitFunctionEntryCode()69 virtual void EmitFunctionEntryCode() {} 70 71 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 72 /// instruction selection starts. PreprocessISelDAG()73 virtual void PreprocessISelDAG() {} 74 75 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 76 /// right after selection. PostprocessISelDAG()77 virtual void PostprocessISelDAG() {} 78 79 /// Main hook for targets to transform nodes into machine nodes. 80 virtual void Select(SDNode *N) = 0; 81 82 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 83 /// addressing mode, according to the specified constraint. If this does 84 /// not match or is not implemented, return true. The resultant operands 85 /// (which will appear in the machine instruction) should be added to the 86 /// OutOps vector. SelectInlineAsmMemoryOperand(const SDValue & Op,unsigned ConstraintID,std::vector<SDValue> & OutOps)87 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 88 unsigned ConstraintID, 89 std::vector<SDValue> &OutOps) { 90 return true; 91 } 92 93 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 94 /// operand node N of U during instruction selection that starts at Root. 95 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 96 97 /// IsLegalToFold - Returns true if the specific operand node N of 98 /// U can be folded during instruction selection that starts at Root. 99 /// FIXME: This is a static member function because the MSP430/X86 100 /// targets, which uses it during isel. This could become a proper member. 101 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 102 CodeGenOpt::Level OptLevel, 103 bool IgnoreChains = false); 104 105 // Opcodes used by the DAG state machine: 106 enum BuiltinOpcodes { 107 OPC_Scope, 108 OPC_RecordNode, 109 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 110 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 111 OPC_RecordMemRef, 112 OPC_CaptureGlueInput, 113 OPC_MoveChild, 114 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3, 115 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7, 116 OPC_MoveParent, 117 OPC_CheckSame, 118 OPC_CheckChild0Same, OPC_CheckChild1Same, 119 OPC_CheckChild2Same, OPC_CheckChild3Same, 120 OPC_CheckPatternPredicate, 121 OPC_CheckPredicate, 122 OPC_CheckOpcode, 123 OPC_SwitchOpcode, 124 OPC_CheckType, 125 OPC_SwitchType, 126 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 127 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 128 OPC_CheckChild6Type, OPC_CheckChild7Type, 129 OPC_CheckInteger, 130 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, 131 OPC_CheckChild3Integer, OPC_CheckChild4Integer, 132 OPC_CheckCondCode, 133 OPC_CheckValueType, 134 OPC_CheckComplexPat, 135 OPC_CheckAndImm, OPC_CheckOrImm, 136 OPC_CheckFoldableChainNode, 137 138 OPC_EmitInteger, 139 OPC_EmitRegister, 140 OPC_EmitRegister2, 141 OPC_EmitConvertToTarget, 142 OPC_EmitMergeInputChains, 143 OPC_EmitMergeInputChains1_0, 144 OPC_EmitMergeInputChains1_1, 145 OPC_EmitMergeInputChains1_2, 146 OPC_EmitCopyToReg, 147 OPC_EmitNodeXForm, 148 OPC_EmitNode, 149 // Space-optimized forms that implicitly encode number of result VTs. 150 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2, 151 OPC_MorphNodeTo, 152 // Space-optimized forms that implicitly encode number of result VTs. 153 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2, 154 OPC_CompleteMatch 155 }; 156 157 enum { 158 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 159 OPFL_Chain = 1, // Node has a chain input. 160 OPFL_GlueInput = 2, // Node has a glue input. 161 OPFL_GlueOutput = 4, // Node has a glue output. 162 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 163 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 164 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 165 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 166 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 167 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 168 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 169 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 170 171 OPFL_VariadicInfo = OPFL_Variadic6 172 }; 173 174 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 175 /// number of fixed arity values that should be skipped when copying from the 176 /// root. getNumFixedFromVariadicInfo(unsigned Flags)177 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 178 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 179 } 180 181 182 protected: 183 /// DAGSize - Size of DAG being instruction selected. 184 /// 185 unsigned DAGSize; 186 187 /// ReplaceUses - replace all uses of the old node F with the use 188 /// of the new node T. ReplaceUses(SDValue F,SDValue T)189 void ReplaceUses(SDValue F, SDValue T) { 190 CurDAG->ReplaceAllUsesOfValueWith(F, T); 191 } 192 193 /// ReplaceUses - replace all uses of the old nodes F with the use 194 /// of the new nodes T. ReplaceUses(const SDValue * F,const SDValue * T,unsigned Num)195 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 196 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 197 } 198 199 /// ReplaceUses - replace all uses of the old node F with the use 200 /// of the new node T. ReplaceUses(SDNode * F,SDNode * T)201 void ReplaceUses(SDNode *F, SDNode *T) { 202 CurDAG->ReplaceAllUsesWith(F, T); 203 } 204 205 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. ReplaceNode(SDNode * F,SDNode * T)206 void ReplaceNode(SDNode *F, SDNode *T) { 207 CurDAG->ReplaceAllUsesWith(F, T); 208 CurDAG->RemoveDeadNode(F); 209 } 210 211 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 212 /// by tblgen. Others should not call it. 213 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 214 const SDLoc &DL); 215 216 public: 217 // Calls to these predicates are generated by tblgen. 218 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 219 int64_t DesiredMaskS) const; 220 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 221 int64_t DesiredMaskS) const; 222 223 224 /// CheckPatternPredicate - This function is generated by tblgen in the 225 /// target. It runs the specified pattern predicate and returns true if it 226 /// succeeds or false if it fails. The number is a private implementation 227 /// detail to the code tblgen produces. CheckPatternPredicate(unsigned PredNo)228 virtual bool CheckPatternPredicate(unsigned PredNo) const { 229 llvm_unreachable("Tblgen should generate the implementation of this!"); 230 } 231 232 /// CheckNodePredicate - This function is generated by tblgen in the target. 233 /// It runs node predicate number PredNo and returns true if it succeeds or 234 /// false if it fails. The number is a private implementation 235 /// detail to the code tblgen produces. CheckNodePredicate(SDNode * N,unsigned PredNo)236 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 237 llvm_unreachable("Tblgen should generate the implementation of this!"); 238 } 239 CheckComplexPattern(SDNode * Root,SDNode * Parent,SDValue N,unsigned PatternNo,SmallVectorImpl<std::pair<SDValue,SDNode * >> & Result)240 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 241 unsigned PatternNo, 242 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 243 llvm_unreachable("Tblgen should generate the implementation of this!"); 244 } 245 RunSDNodeXForm(SDValue V,unsigned XFormNo)246 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 247 llvm_unreachable("Tblgen should generate this!"); 248 } 249 250 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 251 unsigned TableSize); 252 253 /// \brief Return true if complex patterns for this target can mutate the 254 /// DAG. ComplexPatternFuncMutatesDAG()255 virtual bool ComplexPatternFuncMutatesDAG() const { 256 return false; 257 } 258 259 private: 260 261 // Calls to these functions are generated by tblgen. 262 void Select_INLINEASM(SDNode *N); 263 void Select_READ_REGISTER(SDNode *N); 264 void Select_WRITE_REGISTER(SDNode *N); 265 void Select_UNDEF(SDNode *N); 266 void CannotYetSelect(SDNode *N); 267 268 private: 269 void DoInstructionSelection(); 270 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs, 271 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 272 273 /// Prepares the landing pad to take incoming values or do other EH 274 /// personality specific tasks. Returns true if the block should be 275 /// instruction selected, false if no code should be emitted for it. 276 bool PrepareEHLandingPad(); 277 278 /// \brief Perform instruction selection on all basic blocks in the function. 279 void SelectAllBasicBlocks(const Function &Fn); 280 281 /// \brief Perform instruction selection on a single basic block, for 282 /// instructions between \p Begin and \p End. \p HadTailCall will be set 283 /// to true if a call in the block was translated as a tail call. 284 void SelectBasicBlock(BasicBlock::const_iterator Begin, 285 BasicBlock::const_iterator End, 286 bool &HadTailCall); 287 void FinishBasicBlock(); 288 289 void CodeGenAndEmitDAG(); 290 291 /// \brief Generate instructions for lowering the incoming arguments of the 292 /// given function. 293 void LowerArguments(const Function &F); 294 295 void ComputeLiveOutVRegInfo(); 296 297 /// Create the scheduler. If a specific scheduler was specified 298 /// via the SchedulerRegistry, use it, otherwise select the 299 /// one preferred by the target. 300 /// 301 ScheduleDAGSDNodes *CreateScheduler(); 302 303 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 304 /// state machines that start with a OPC_SwitchOpcode node. 305 std::vector<unsigned> OpcodeOffset; 306 307 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 308 const SmallVectorImpl<SDNode *> &ChainNodesMatched, 309 bool isMorphNodeTo); 310 }; 311 312 } 313 314 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 315