1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "opcode/ppc.h"
25 #include "opintl.h"
26
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37
38 /* Local insertion and extraction functions. */
39
40 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41 static long extract_arx (unsigned long, ppc_cpu_t, int *);
42 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43 static long extract_ary (unsigned long, ppc_cpu_t, int *);
44 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45 static long extract_bat (unsigned long, ppc_cpu_t, int *);
46 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47 static long extract_bba (unsigned long, ppc_cpu_t, int *);
48 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53 static long extract_bo (unsigned long, ppc_cpu_t, int *);
54 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55 static long extract_boe (unsigned long, ppc_cpu_t, int *);
56 static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
57 static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
58 static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
59 static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
60 static long extract_dxd (unsigned long, ppc_cpu_t, int *);
61 static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
62 static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
63 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
64 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
65 static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
66 static long extract_l0 (unsigned long, ppc_cpu_t, int *);
67 static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
68 static long extract_l1 (unsigned long, ppc_cpu_t, int *);
69 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
70 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
71 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
72 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
73 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
74 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
75 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
76 static long extract_nb (unsigned long, ppc_cpu_t, int *);
77 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
78 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
79 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
80 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
81 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
82 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
83 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
84 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
85 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
86 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
87 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
88 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
89 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
90 static long extract_rx (unsigned long, ppc_cpu_t, int *);
91 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
92 static long extract_ry (unsigned long, ppc_cpu_t, int *);
93 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
94 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
95 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
96 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
97 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
98 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
99 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
100 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
101 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
102 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
103 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
104 static long extract_spr (unsigned long, ppc_cpu_t, int *);
105 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
106 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
107 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
108 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
109 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
110 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
111 static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
112 static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
113 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
114 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
115 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
116 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
117 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
118 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
119 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
120 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
121 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
122 static long extract_dm (unsigned long, ppc_cpu_t, int *);
123 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
124 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
125 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
126 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
127 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
128 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
129 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
130 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
131
132 /* The operands table.
133
134 The fields are bitm, shift, insert, extract, flags.
135
136 We used to put parens around the various additions, like the one
137 for BA just below. However, that caused trouble with feeble
138 compilers with a limit on depth of a parenthesized expression, like
139 (reportedly) the compiler in Microsoft Developer Studio 5. So we
140 omit the parens, since the macros are never used in a context where
141 the addition will be ambiguous. */
142
143 const struct powerpc_operand powerpc_operands[] =
144 {
145 /* The zero index is used to indicate the end of the list of
146 operands. */
147 #define UNUSED 0
148 { 0, 0, NULL, NULL, 0 },
149
150 /* The BA field in an XL form instruction. */
151 #define BA UNUSED + 1
152 /* The BI field in a B form or XL form instruction. */
153 #define BI BA
154 #define BI_MASK (0x1f << 16)
155 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
156
157 /* The BA field in an XL form instruction when it must be the same
158 as the BT field in the same instruction. */
159 #define BAT BA + 1
160 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
161
162 /* The BB field in an XL form instruction. */
163 #define BB BAT + 1
164 #define BB_MASK (0x1f << 11)
165 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
166
167 /* The BB field in an XL form instruction when it must be the same
168 as the BA field in the same instruction. */
169 #define BBA BB + 1
170 /* The VB field in a VX form instruction when it must be the same
171 as the VA field in the same instruction. */
172 #define VBA BBA
173 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
174
175 /* The BD field in a B form instruction. The lower two bits are
176 forced to zero. */
177 #define BD BBA + 1
178 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
179
180 /* The BD field in a B form instruction when absolute addressing is
181 used. */
182 #define BDA BD + 1
183 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
184
185 /* The BD field in a B form instruction when the - modifier is used.
186 This sets the y bit of the BO field appropriately. */
187 #define BDM BDA + 1
188 { 0xfffc, 0, insert_bdm, extract_bdm,
189 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
190
191 /* The BD field in a B form instruction when the - modifier is used
192 and absolute address is used. */
193 #define BDMA BDM + 1
194 { 0xfffc, 0, insert_bdm, extract_bdm,
195 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
196
197 /* The BD field in a B form instruction when the + modifier is used.
198 This sets the y bit of the BO field appropriately. */
199 #define BDP BDMA + 1
200 { 0xfffc, 0, insert_bdp, extract_bdp,
201 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
202
203 /* The BD field in a B form instruction when the + modifier is used
204 and absolute addressing is used. */
205 #define BDPA BDP + 1
206 { 0xfffc, 0, insert_bdp, extract_bdp,
207 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
208
209 /* The BF field in an X or XL form instruction. */
210 #define BF BDPA + 1
211 /* The CRFD field in an X form instruction. */
212 #define CRFD BF
213 /* The CRD field in an XL form instruction. */
214 #define CRD BF
215 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
216
217 /* The BF field in an X or XL form instruction. */
218 #define BFF BF + 1
219 { 0x7, 23, NULL, NULL, 0 },
220
221 /* An optional BF field. This is used for comparison instructions,
222 in which an omitted BF field is taken as zero. */
223 #define OBF BFF + 1
224 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
225
226 /* The BFA field in an X or XL form instruction. */
227 #define BFA OBF + 1
228 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
229
230 /* The BO field in a B form instruction. Certain values are
231 illegal. */
232 #define BO BFA + 1
233 #define BO_MASK (0x1f << 21)
234 { 0x1f, 21, insert_bo, extract_bo, 0 },
235
236 /* The BO field in a B form instruction when the + or - modifier is
237 used. This is like the BO field, but it must be even. */
238 #define BOE BO + 1
239 { 0x1e, 21, insert_boe, extract_boe, 0 },
240
241 /* The RM field in an X form instruction. */
242 #define RM BOE + 1
243 { 0x3, 11, NULL, NULL, 0 },
244
245 #define BH RM + 1
246 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
247
248 /* The BT field in an X or XL form instruction. */
249 #define BT BH + 1
250 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
251
252 /* The BI16 field in a BD8 form instruction. */
253 #define BI16 BT + 1
254 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
255
256 /* The BI32 field in a BD15 form instruction. */
257 #define BI32 BI16 + 1
258 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
259
260 /* The BO32 field in a BD15 form instruction. */
261 #define BO32 BI32 + 1
262 { 0x3, 20, NULL, NULL, 0 },
263
264 /* The B8 field in a BD8 form instruction. */
265 #define B8 BO32 + 1
266 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
267
268 /* The B15 field in a BD15 form instruction. The lowest bit is
269 forced to zero. */
270 #define B15 B8 + 1
271 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
272
273 /* The B24 field in a BD24 form instruction. The lowest bit is
274 forced to zero. */
275 #define B24 B15 + 1
276 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
277
278 /* The condition register number portion of the BI field in a B form
279 or XL form instruction. This is used for the extended
280 conditional branch mnemonics, which set the lower two bits of the
281 BI field. This field is optional. */
282 #define CR B24 + 1
283 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
284
285 /* The CRB field in an X form instruction. */
286 #define CRB CR + 1
287 /* The MB field in an M form instruction. */
288 #define MB CRB
289 #define MB_MASK (0x1f << 6)
290 { 0x1f, 6, NULL, NULL, 0 },
291
292 /* The CRD32 field in an XL form instruction. */
293 #define CRD32 CRB + 1
294 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
295
296 /* The CRFS field in an X form instruction. */
297 #define CRFS CRD32 + 1
298 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
299
300 #define CRS CRFS + 1
301 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
302
303 /* The CT field in an X form instruction. */
304 #define CT CRS + 1
305 /* The MO field in an mbar instruction. */
306 #define MO CT
307 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
308
309 /* The D field in a D form instruction. This is a displacement off
310 a register, and implies that the next operand is a register in
311 parentheses. */
312 #define D CT + 1
313 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
314
315 /* The D8 field in a D form instruction. This is a displacement off
316 a register, and implies that the next operand is a register in
317 parentheses. */
318 #define D8 D + 1
319 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
320
321 /* The DCMX field in an X form instruction. */
322 #define DCMX D8 + 1
323 { 0x7f, 16, NULL, NULL, 0 },
324
325 /* The split DCMX field in an X form instruction. */
326 #define DCMXS DCMX + 1
327 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
328
329 /* The DQ field in a DQ form instruction. This is like D, but the
330 lower four bits are forced to zero. */
331 #define DQ DCMXS + 1
332 { 0xfff0, 0, NULL, NULL,
333 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
334
335 /* The DS field in a DS form instruction. This is like D, but the
336 lower two bits are forced to zero. */
337 #define DS DQ + 1
338 { 0xfffc, 0, NULL, NULL,
339 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
340
341 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
342 unsigned imediate */
343 #define DUIS DS + 1
344 #define BHRBE DUIS
345 { 0x3ff, 11, NULL, NULL, 0 },
346
347 /* The split D field in a DX form instruction. */
348 #define DXD DUIS + 1
349 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
350 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
351
352 /* The split ND field in a DX form instruction.
353 This is the same as the DX field, only negated. */
354 #define NDXD DXD + 1
355 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
356 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
357
358 /* The E field in a wrteei instruction. */
359 /* And the W bit in the pair singles instructions. */
360 /* And the ST field in a VX form instruction. */
361 #define E NDXD + 1
362 #define PSW E
363 #define ST E
364 { 0x1, 15, NULL, NULL, 0 },
365
366 /* The FL1 field in a POWER SC form instruction. */
367 #define FL1 E + 1
368 /* The U field in an X form instruction. */
369 #define U FL1
370 { 0xf, 12, NULL, NULL, 0 },
371
372 /* The FL2 field in a POWER SC form instruction. */
373 #define FL2 FL1 + 1
374 { 0x7, 2, NULL, NULL, 0 },
375
376 /* The FLM field in an XFL form instruction. */
377 #define FLM FL2 + 1
378 { 0xff, 17, NULL, NULL, 0 },
379
380 /* The FRA field in an X or A form instruction. */
381 #define FRA FLM + 1
382 #define FRA_MASK (0x1f << 16)
383 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
384
385 /* The FRAp field of DFP instructions. */
386 #define FRAp FRA + 1
387 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
388
389 /* The FRB field in an X or A form instruction. */
390 #define FRB FRAp + 1
391 #define FRB_MASK (0x1f << 11)
392 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
393
394 /* The FRBp field of DFP instructions. */
395 #define FRBp FRB + 1
396 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
397
398 /* The FRC field in an A form instruction. */
399 #define FRC FRBp + 1
400 #define FRC_MASK (0x1f << 6)
401 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
402
403 /* The FRS field in an X form instruction or the FRT field in a D, X
404 or A form instruction. */
405 #define FRS FRC + 1
406 #define FRT FRS
407 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
408
409 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
410 instructions. */
411 #define FRSp FRS + 1
412 #define FRTp FRSp
413 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
414
415 /* The FXM field in an XFX instruction. */
416 #define FXM FRSp + 1
417 { 0xff, 12, insert_fxm, extract_fxm, 0 },
418
419 /* Power4 version for mfcr. */
420 #define FXM4 FXM + 1
421 { 0xff, 12, insert_fxm, extract_fxm,
422 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
423 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
424 { -1, -1, NULL, NULL, 0},
425
426 /* The IMM20 field in an LI instruction. */
427 #define IMM20 FXM4 + 2
428 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
429
430 /* The L field in a D or X form instruction. */
431 #define L IMM20 + 1
432 /* The R field in a HTM X form instruction. */
433 #define HTM_R L
434 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
435
436 /* The L field in an X form instruction which must be zero. */
437 #define L0 L + 1
438 { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
439
440 /* The L field in an X form instruction which must be one. */
441 #define L1 L0 + 1
442 { 0x1, 21, insert_l1, extract_l1, 0 },
443
444 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
445 #define SVC_LEV L1 + 1
446 { 0x7f, 5, NULL, NULL, 0 },
447
448 /* The LEV field in an SC form instruction. */
449 #define LEV SVC_LEV + 1
450 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
451
452 /* The LI field in an I form instruction. The lower two bits are
453 forced to zero. */
454 #define LI LEV + 1
455 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
456
457 /* The LI field in an I form instruction when used as an absolute
458 address. */
459 #define LIA LI + 1
460 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
461
462 /* The LS or WC field in an X (sync or wait) form instruction. */
463 #define LS LIA + 1
464 #define WC LS
465 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
466
467 /* The ME field in an M form instruction. */
468 #define ME LS + 1
469 #define ME_MASK (0x1f << 1)
470 { 0x1f, 1, NULL, NULL, 0 },
471
472 /* The MB and ME fields in an M form instruction expressed a single
473 operand which is a bitmask indicating which bits to select. This
474 is a two operand form using PPC_OPERAND_NEXT. See the
475 description in opcode/ppc.h for what this means. */
476 #define MBE ME + 1
477 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
478 { -1, 0, insert_mbe, extract_mbe, 0 },
479
480 /* The MB or ME field in an MD or MDS form instruction. The high
481 bit is wrapped to the low end. */
482 #define MB6 MBE + 2
483 #define ME6 MB6
484 #define MB6_MASK (0x3f << 5)
485 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
486
487 /* The NB field in an X form instruction. The value 32 is stored as
488 0. */
489 #define NB MB6 + 1
490 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
491
492 /* The NBI field in an lswi instruction, which has special value
493 restrictions. The value 32 is stored as 0. */
494 #define NBI NB + 1
495 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
496
497 /* The NSI field in a D form instruction. This is the same as the
498 SI field, only negated. */
499 #define NSI NBI + 1
500 { 0xffff, 0, insert_nsi, extract_nsi,
501 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
502
503 /* The NSI field in a D form instruction when we accept a wide range
504 of positive values. */
505 #define NSISIGNOPT NSI + 1
506 { 0xffff, 0, insert_nsi, extract_nsi,
507 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
508
509 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
510 #define RA NSISIGNOPT + 1
511 #define RA_MASK (0x1f << 16)
512 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
513
514 /* As above, but 0 in the RA field means zero, not r0. */
515 #define RA0 RA + 1
516 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
517
518 /* The RA field in the DQ form lq or an lswx instruction, which have special
519 value restrictions. */
520 #define RAQ RA0 + 1
521 #define RAX RAQ
522 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
523
524 /* The RA field in a D or X form instruction which is an updating
525 load, which means that the RA field may not be zero and may not
526 equal the RT field. */
527 #define RAL RAQ + 1
528 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
529
530 /* The RA field in an lmw instruction, which has special value
531 restrictions. */
532 #define RAM RAL + 1
533 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
534
535 /* The RA field in a D or X form instruction which is an updating
536 store or an updating floating point load, which means that the RA
537 field may not be zero. */
538 #define RAS RAM + 1
539 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
540
541 /* The RA field of the tlbwe, dccci and iccci instructions,
542 which are optional. */
543 #define RAOPT RAS + 1
544 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
545
546 /* The RB field in an X, XO, M, or MDS form instruction. */
547 #define RB RAOPT + 1
548 #define RB_MASK (0x1f << 11)
549 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
550
551 /* The RB field in an X form instruction when it must be the same as
552 the RS field in the instruction. This is used for extended
553 mnemonics like mr. */
554 #define RBS RB + 1
555 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
556
557 /* The RB field in an lswx instruction, which has special value
558 restrictions. */
559 #define RBX RBS + 1
560 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
561
562 /* The RB field of the dccci and iccci instructions, which are optional. */
563 #define RBOPT RBX + 1
564 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
565
566 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
567 #define RC RBOPT + 1
568 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
569
570 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
571 instruction or the RT field in a D, DS, X, XFX or XO form
572 instruction. */
573 #define RS RC + 1
574 #define RT RS
575 #define RT_MASK (0x1f << 21)
576 #define RD RS
577 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
578
579 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
580 which have special value restrictions. */
581 #define RSQ RS + 1
582 #define RTQ RSQ
583 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
584
585 /* The RS field of the tlbwe instruction, which is optional. */
586 #define RSO RSQ + 1
587 #define RTO RSO
588 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
589
590 /* The RX field of the SE_RR form instruction. */
591 #define RX RSO + 1
592 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
593
594 /* The ARX field of the SE_RR form instruction. */
595 #define ARX RX + 1
596 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
597
598 /* The RY field of the SE_RR form instruction. */
599 #define RY ARX + 1
600 #define RZ RY
601 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
602
603 /* The ARY field of the SE_RR form instruction. */
604 #define ARY RY + 1
605 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
606
607 /* The SCLSCI8 field in a D form instruction. */
608 #define SCLSCI8 ARY + 1
609 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
610
611 /* The SCLSCI8N field in a D form instruction. This is the same as the
612 SCLSCI8 field, only negated. */
613 #define SCLSCI8N SCLSCI8 + 1
614 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
615 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
616
617 /* The SD field of the SD4 form instruction. */
618 #define SE_SD SCLSCI8N + 1
619 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
620
621 /* The SD field of the SD4 form instruction, for halfword. */
622 #define SE_SDH SE_SD + 1
623 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
624
625 /* The SD field of the SD4 form instruction, for word. */
626 #define SE_SDW SE_SDH + 1
627 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
628
629 /* The SH field in an X or M form instruction. */
630 #define SH SE_SDW + 1
631 #define SH_MASK (0x1f << 11)
632 /* The other UIMM field in a EVX form instruction. */
633 #define EVUIMM SH
634 /* The FC field in an atomic X form instruction. */
635 #define FC SH
636 { 0x1f, 11, NULL, NULL, 0 },
637
638 /* The SI field in a HTM X form instruction. */
639 #define HTM_SI SH + 1
640 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
641
642 /* The SH field in an MD form instruction. This is split. */
643 #define SH6 HTM_SI + 1
644 #define SH6_MASK ((0x1f << 11) | (1 << 1))
645 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
646
647 /* The SH field of the tlbwe instruction, which is optional. */
648 #define SHO SH6 + 1
649 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
650
651 /* The SI field in a D form instruction. */
652 #define SI SHO + 1
653 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
654
655 /* The SI field in a D form instruction when we accept a wide range
656 of positive values. */
657 #define SISIGNOPT SI + 1
658 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
659
660 /* The SI8 field in a D form instruction. */
661 #define SI8 SISIGNOPT + 1
662 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
663
664 /* The SPR field in an XFX form instruction. This is flipped--the
665 lower 5 bits are stored in the upper 5 and vice- versa. */
666 #define SPR SI8 + 1
667 #define PMR SPR
668 #define TMR SPR
669 #define SPR_MASK (0x3ff << 11)
670 { 0x3ff, 11, insert_spr, extract_spr, 0 },
671
672 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
673 #define SPRBAT SPR + 1
674 #define SPRBAT_MASK (0x3 << 17)
675 { 0x3, 17, NULL, NULL, 0 },
676
677 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
678 #define SPRG SPRBAT + 1
679 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
680
681 /* The SR field in an X form instruction. */
682 #define SR SPRG + 1
683 /* The 4-bit UIMM field in a VX form instruction. */
684 #define UIMM4 SR
685 { 0xf, 16, NULL, NULL, 0 },
686
687 /* The STRM field in an X AltiVec form instruction. */
688 #define STRM SR + 1
689 /* The T field in a tlbilx form instruction. */
690 #define T STRM
691 { 0x3, 21, NULL, NULL, 0 },
692
693 /* The ESYNC field in an X (sync) form instruction. */
694 #define ESYNC STRM + 1
695 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
696
697 /* The SV field in a POWER SC form instruction. */
698 #define SV ESYNC + 1
699 { 0x3fff, 2, NULL, NULL, 0 },
700
701 /* The TBR field in an XFX form instruction. This is like the SPR
702 field, but it is optional. */
703 #define TBR SV + 1
704 { 0x3ff, 11, insert_tbr, extract_tbr,
705 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
706 /* If the TBR operand is ommitted, use the value 268. */
707 { -1, 268, NULL, NULL, 0},
708
709 /* The TO field in a D or X form instruction. */
710 #define TO TBR + 2
711 #define DUI TO
712 #define TO_MASK (0x1f << 21)
713 { 0x1f, 21, NULL, NULL, 0 },
714
715 /* The UI field in a D form instruction. */
716 #define UI TO + 1
717 { 0xffff, 0, NULL, NULL, 0 },
718
719 #define UISIGNOPT UI + 1
720 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
721
722 /* The IMM field in an SE_IM5 instruction. */
723 #define UI5 UISIGNOPT + 1
724 { 0x1f, 4, NULL, NULL, 0 },
725
726 /* The OIMM field in an SE_OIM5 instruction. */
727 #define OIMM5 UI5 + 1
728 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
729
730 /* The UI7 field in an SE_LI instruction. */
731 #define UI7 OIMM5 + 1
732 { 0x7f, 4, NULL, NULL, 0 },
733
734 /* The VA field in a VA, VX or VXR form instruction. */
735 #define VA UI7 + 1
736 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
737
738 /* The VB field in a VA, VX or VXR form instruction. */
739 #define VB VA + 1
740 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
741
742 /* The VC field in a VA form instruction. */
743 #define VC VB + 1
744 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
745
746 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
747 #define VD VC + 1
748 #define VS VD
749 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
750
751 /* The SIMM field in a VX form instruction, and TE in Z form. */
752 #define SIMM VD + 1
753 #define TE SIMM
754 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
755
756 /* The UIMM field in a VX form instruction. */
757 #define UIMM SIMM + 1
758 #define DCTL UIMM
759 { 0x1f, 16, NULL, NULL, 0 },
760
761 /* The 3-bit UIMM field in a VX form instruction. */
762 #define UIMM3 UIMM + 1
763 { 0x7, 16, NULL, NULL, 0 },
764
765 /* The 6-bit UIM field in a X form instruction. */
766 #define UIM6 UIMM3 + 1
767 { 0x3f, 16, NULL, NULL, 0 },
768
769 /* The SIX field in a VX form instruction. */
770 #define SIX UIM6 + 1
771 { 0xf, 11, NULL, NULL, 0 },
772
773 /* The PS field in a VX form instruction. */
774 #define PS SIX + 1
775 { 0x1, 9, NULL, NULL, 0 },
776
777 /* The SHB field in a VA form instruction. */
778 #define SHB PS + 1
779 { 0xf, 6, NULL, NULL, 0 },
780
781 /* The other UIMM field in a half word EVX form instruction. */
782 #define EVUIMM_2 SHB + 1
783 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
784
785 /* The other UIMM field in a word EVX form instruction. */
786 #define EVUIMM_4 EVUIMM_2 + 1
787 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
788
789 /* The other UIMM field in a double EVX form instruction. */
790 #define EVUIMM_8 EVUIMM_4 + 1
791 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
792
793 /* The WS or DRM field in an X form instruction. */
794 #define WS EVUIMM_8 + 1
795 #define DRM WS
796 { 0x7, 11, NULL, NULL, 0 },
797
798 /* PowerPC paired singles extensions. */
799 /* W bit in the pair singles instructions for x type instructions. */
800 #define PSWM WS + 1
801 /* The BO16 field in a BD8 form instruction. */
802 #define BO16 PSWM
803 { 0x1, 10, 0, 0, 0 },
804
805 /* IDX bits for quantization in the pair singles instructions. */
806 #define PSQ PSWM + 1
807 { 0x7, 12, 0, 0, 0 },
808
809 /* IDX bits for quantization in the pair singles x-type instructions. */
810 #define PSQM PSQ + 1
811 { 0x7, 7, 0, 0, 0 },
812
813 /* Smaller D field for quantization in the pair singles instructions. */
814 #define PSD PSQM + 1
815 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
816
817 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
818 #define A_L PSD + 1
819 #define W A_L
820 #define X_R A_L
821 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
822
823 /* The RMC or CY field in a Z23 form instruction. */
824 #define RMC A_L + 1
825 #define CY RMC
826 { 0x3, 9, NULL, NULL, 0 },
827
828 #define R RMC + 1
829 { 0x1, 16, NULL, NULL, 0 },
830
831 #define RIC R + 1
832 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
833
834 #define PRS RIC + 1
835 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
836
837 #define SP PRS + 1
838 { 0x3, 19, NULL, NULL, 0 },
839
840 #define S SP + 1
841 { 0x1, 20, NULL, NULL, 0 },
842
843 /* The S field in a XL form instruction. */
844 #define SXL S + 1
845 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
846 /* If the SXL operand is ommitted, use the value 1. */
847 { -1, 1, NULL, NULL, 0},
848
849 /* SH field starting at bit position 16. */
850 #define SH16 SXL + 2
851 /* The DCM and DGM fields in a Z form instruction. */
852 #define DCM SH16
853 #define DGM DCM
854 { 0x3f, 10, NULL, NULL, 0 },
855
856 /* The EH field in larx instruction. */
857 #define EH SH16 + 1
858 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
859
860 /* The L field in an mtfsf or XFL form instruction. */
861 /* The A field in a HTM X form instruction. */
862 #define XFL_L EH + 1
863 #define HTM_A XFL_L
864 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
865
866 /* Xilinx APU related masks and macros */
867 #define FCRT XFL_L + 1
868 #define FCRT_MASK (0x1f << 21)
869 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
870
871 /* Xilinx FSL related masks and macros */
872 #define FSL FCRT + 1
873 #define FSL_MASK (0x1f << 11)
874 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
875
876 /* Xilinx UDI related masks and macros */
877 #define URT FSL + 1
878 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
879
880 #define URA URT + 1
881 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
882
883 #define URB URA + 1
884 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
885
886 #define URC URB + 1
887 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
888
889 /* The VLESIMM field in a D form instruction. */
890 #define VLESIMM URC + 1
891 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
892 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
893
894 /* The VLENSIMM field in a D form instruction. */
895 #define VLENSIMM VLESIMM + 1
896 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
897 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
898
899 /* The VLEUIMM field in a D form instruction. */
900 #define VLEUIMM VLENSIMM + 1
901 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
902
903 /* The VLEUIMML field in a D form instruction. */
904 #define VLEUIMML VLEUIMM + 1
905 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
906
907 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
908 #define XS6 VLEUIMML + 1
909 #define XT6 XS6
910 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
911
912 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
913 #define XSQ6 XT6 + 1
914 #define XTQ6 XSQ6
915 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
916
917 /* The XA field in an XX3 form instruction. This is split. */
918 #define XA6 XTQ6 + 1
919 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
920
921 /* The XB field in an XX2 or XX3 form instruction. This is split. */
922 #define XB6 XA6 + 1
923 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
924
925 /* The XB field in an XX3 form instruction when it must be the same as
926 the XA field in the instruction. This is used in extended mnemonics
927 like xvmovdp. This is split. */
928 #define XB6S XB6 + 1
929 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
930
931 /* The XC field in an XX4 form instruction. This is split. */
932 #define XC6 XB6S + 1
933 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
934
935 /* The DM or SHW field in an XX3 form instruction. */
936 #define DM XC6 + 1
937 #define SHW DM
938 { 0x3, 8, NULL, NULL, 0 },
939
940 /* The DM field in an extended mnemonic XX3 form instruction. */
941 #define DMEX DM + 1
942 { 0x3, 8, insert_dm, extract_dm, 0 },
943
944 /* The UIM field in an XX2 form instruction. */
945 #define UIM DMEX + 1
946 /* The 2-bit UIMM field in a VX form instruction. */
947 #define UIMM2 UIM
948 /* The 2-bit L field in a darn instruction. */
949 #define LRAND UIM
950 { 0x3, 16, NULL, NULL, 0 },
951
952 #define ERAT_T UIM + 1
953 { 0x7, 21, NULL, NULL, 0 },
954
955 #define IH ERAT_T + 1
956 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
957
958 /* The 8-bit IMM8 field in a XX1 form instruction. */
959 #define IMM8 IH + 1
960 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
961 };
962
963 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
964 / sizeof (powerpc_operands[0]));
965
966 /* The functions used to insert and extract complicated operands. */
967
968 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
969
970 static unsigned long
insert_arx(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)971 insert_arx (unsigned long insn,
972 long value,
973 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
974 const char **errmsg ATTRIBUTE_UNUSED)
975 {
976 if (value >= 8 && value < 24)
977 return insn | ((value - 8) & 0xf);
978 else
979 {
980 *errmsg = _("invalid register");
981 return 0;
982 }
983 }
984
985 static long
extract_arx(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)986 extract_arx (unsigned long insn,
987 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
988 int *invalid ATTRIBUTE_UNUSED)
989 {
990 return (insn & 0xf) + 8;
991 }
992
993 static unsigned long
insert_ary(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)994 insert_ary (unsigned long insn,
995 long value,
996 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
997 const char **errmsg ATTRIBUTE_UNUSED)
998 {
999 if (value >= 8 && value < 24)
1000 return insn | (((value - 8) & 0xf) << 4);
1001 else
1002 {
1003 *errmsg = _("invalid register");
1004 return 0;
1005 }
1006 }
1007
1008 static long
extract_ary(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1009 extract_ary (unsigned long insn,
1010 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1011 int *invalid ATTRIBUTE_UNUSED)
1012 {
1013 return ((insn >> 4) & 0xf) + 8;
1014 }
1015
1016 static unsigned long
insert_rx(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1017 insert_rx (unsigned long insn,
1018 long value,
1019 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1020 const char **errmsg)
1021 {
1022 if (value >= 0 && value < 8)
1023 return insn | value;
1024 else if (value >= 24 && value <= 31)
1025 return insn | (value - 16);
1026 else
1027 {
1028 *errmsg = _("invalid register");
1029 return 0;
1030 }
1031 }
1032
1033 static long
extract_rx(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1034 extract_rx (unsigned long insn,
1035 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1036 int *invalid ATTRIBUTE_UNUSED)
1037 {
1038 int value = insn & 0xf;
1039 if (value >= 0 && value < 8)
1040 return value;
1041 else
1042 return value + 16;
1043 }
1044
1045 static unsigned long
insert_ry(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1046 insert_ry (unsigned long insn,
1047 long value,
1048 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1049 const char **errmsg)
1050 {
1051 if (value >= 0 && value < 8)
1052 return insn | (value << 4);
1053 else if (value >= 24 && value <= 31)
1054 return insn | ((value - 16) << 4);
1055 else
1056 {
1057 *errmsg = _("invalid register");
1058 return 0;
1059 }
1060 }
1061
1062 static long
extract_ry(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1063 extract_ry (unsigned long insn,
1064 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1065 int *invalid ATTRIBUTE_UNUSED)
1066 {
1067 int value = (insn >> 4) & 0xf;
1068 if (value >= 0 && value < 8)
1069 return value;
1070 else
1071 return value + 16;
1072 }
1073
1074 /* The BA field in an XL form instruction when it must be the same as
1075 the BT field in the same instruction. This operand is marked FAKE.
1076 The insertion function just copies the BT field into the BA field,
1077 and the extraction function just checks that the fields are the
1078 same. */
1079
1080 static unsigned long
insert_bat(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1081 insert_bat (unsigned long insn,
1082 long value ATTRIBUTE_UNUSED,
1083 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1084 const char **errmsg ATTRIBUTE_UNUSED)
1085 {
1086 return insn | (((insn >> 21) & 0x1f) << 16);
1087 }
1088
1089 static long
extract_bat(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1090 extract_bat (unsigned long insn,
1091 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1092 int *invalid)
1093 {
1094 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
1095 *invalid = 1;
1096 return 0;
1097 }
1098
1099 /* The BB field in an XL form instruction when it must be the same as
1100 the BA field in the same instruction. This operand is marked FAKE.
1101 The insertion function just copies the BA field into the BB field,
1102 and the extraction function just checks that the fields are the
1103 same. */
1104
1105 static unsigned long
insert_bba(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1106 insert_bba (unsigned long insn,
1107 long value ATTRIBUTE_UNUSED,
1108 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1109 const char **errmsg ATTRIBUTE_UNUSED)
1110 {
1111 return insn | (((insn >> 16) & 0x1f) << 11);
1112 }
1113
1114 static long
extract_bba(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1115 extract_bba (unsigned long insn,
1116 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1117 int *invalid)
1118 {
1119 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1120 *invalid = 1;
1121 return 0;
1122 }
1123
1124 /* The BD field in a B form instruction when the - modifier is used.
1125 This modifier means that the branch is not expected to be taken.
1126 For chips built to versions of the architecture prior to version 2
1127 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1128 if the offset is negative. When extracting, we require that the y
1129 bit be 1 and that the offset be positive, since if the y bit is 0
1130 we just want to print the normal form of the instruction.
1131 Power4 compatible targets use two bits, "a", and "t", instead of
1132 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1133 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1134 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1135 for branch on CTR. We only handle the taken/not-taken hint here.
1136 Note that we don't relax the conditions tested here when
1137 disassembling with -Many because insns using extract_bdm and
1138 extract_bdp always occur in pairs. One or the other will always
1139 be valid. */
1140
1141 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1142
1143 static unsigned long
insert_bdm(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg ATTRIBUTE_UNUSED)1144 insert_bdm (unsigned long insn,
1145 long value,
1146 ppc_cpu_t dialect,
1147 const char **errmsg ATTRIBUTE_UNUSED)
1148 {
1149 if ((dialect & ISA_V2) == 0)
1150 {
1151 if ((value & 0x8000) != 0)
1152 insn |= 1 << 21;
1153 }
1154 else
1155 {
1156 if ((insn & (0x14 << 21)) == (0x04 << 21))
1157 insn |= 0x02 << 21;
1158 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1159 insn |= 0x08 << 21;
1160 }
1161 return insn | (value & 0xfffc);
1162 }
1163
1164 static long
extract_bdm(unsigned long insn,ppc_cpu_t dialect,int * invalid)1165 extract_bdm (unsigned long insn,
1166 ppc_cpu_t dialect,
1167 int *invalid)
1168 {
1169 if ((dialect & ISA_V2) == 0)
1170 {
1171 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1172 *invalid = 1;
1173 }
1174 else
1175 {
1176 if ((insn & (0x17 << 21)) != (0x06 << 21)
1177 && (insn & (0x1d << 21)) != (0x18 << 21))
1178 *invalid = 1;
1179 }
1180
1181 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1182 }
1183
1184 /* The BD field in a B form instruction when the + modifier is used.
1185 This is like BDM, above, except that the branch is expected to be
1186 taken. */
1187
1188 static unsigned long
insert_bdp(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg ATTRIBUTE_UNUSED)1189 insert_bdp (unsigned long insn,
1190 long value,
1191 ppc_cpu_t dialect,
1192 const char **errmsg ATTRIBUTE_UNUSED)
1193 {
1194 if ((dialect & ISA_V2) == 0)
1195 {
1196 if ((value & 0x8000) == 0)
1197 insn |= 1 << 21;
1198 }
1199 else
1200 {
1201 if ((insn & (0x14 << 21)) == (0x04 << 21))
1202 insn |= 0x03 << 21;
1203 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1204 insn |= 0x09 << 21;
1205 }
1206 return insn | (value & 0xfffc);
1207 }
1208
1209 static long
extract_bdp(unsigned long insn,ppc_cpu_t dialect,int * invalid)1210 extract_bdp (unsigned long insn,
1211 ppc_cpu_t dialect,
1212 int *invalid)
1213 {
1214 if ((dialect & ISA_V2) == 0)
1215 {
1216 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1217 *invalid = 1;
1218 }
1219 else
1220 {
1221 if ((insn & (0x17 << 21)) != (0x07 << 21)
1222 && (insn & (0x1d << 21)) != (0x19 << 21))
1223 *invalid = 1;
1224 }
1225
1226 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1227 }
1228
1229 static inline int
valid_bo_pre_v2(long value)1230 valid_bo_pre_v2 (long value)
1231 {
1232 /* Certain encodings have bits that are required to be zero.
1233 These are (z must be zero, y may be anything):
1234 0000y
1235 0001y
1236 001zy
1237 0100y
1238 0101y
1239 011zy
1240 1z00y
1241 1z01y
1242 1z1zz
1243 */
1244 if ((value & 0x14) == 0)
1245 return 1;
1246 else if ((value & 0x14) == 0x4)
1247 return (value & 0x2) == 0;
1248 else if ((value & 0x14) == 0x10)
1249 return (value & 0x8) == 0;
1250 else
1251 return value == 0x14;
1252 }
1253
1254 static inline int
valid_bo_post_v2(long value)1255 valid_bo_post_v2 (long value)
1256 {
1257 /* Certain encodings have bits that are required to be zero.
1258 These are (z must be zero, a & t may be anything):
1259 0000z
1260 0001z
1261 001at
1262 0100z
1263 0101z
1264 011at
1265 1a00t
1266 1a01t
1267 1z1zz
1268 */
1269 if ((value & 0x14) == 0)
1270 return (value & 0x1) == 0;
1271 else if ((value & 0x14) == 0x14)
1272 return value == 0x14;
1273 else
1274 return 1;
1275 }
1276
1277 /* Check for legal values of a BO field. */
1278
1279 static int
valid_bo(long value,ppc_cpu_t dialect,int extract)1280 valid_bo (long value, ppc_cpu_t dialect, int extract)
1281 {
1282 int valid_y = valid_bo_pre_v2 (value);
1283 int valid_at = valid_bo_post_v2 (value);
1284
1285 /* When disassembling with -Many, accept either encoding on the
1286 second pass through opcodes. */
1287 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1288 return valid_y || valid_at;
1289 if ((dialect & ISA_V2) == 0)
1290 return valid_y;
1291 else
1292 return valid_at;
1293 }
1294
1295 /* The BO field in a B form instruction. Warn about attempts to set
1296 the field to an illegal value. */
1297
1298 static unsigned long
insert_bo(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1299 insert_bo (unsigned long insn,
1300 long value,
1301 ppc_cpu_t dialect,
1302 const char **errmsg)
1303 {
1304 if (!valid_bo (value, dialect, 0))
1305 *errmsg = _("invalid conditional option");
1306 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1307 *errmsg = _("invalid counter access");
1308 return insn | ((value & 0x1f) << 21);
1309 }
1310
1311 static long
extract_bo(unsigned long insn,ppc_cpu_t dialect,int * invalid)1312 extract_bo (unsigned long insn,
1313 ppc_cpu_t dialect,
1314 int *invalid)
1315 {
1316 long value;
1317
1318 value = (insn >> 21) & 0x1f;
1319 if (!valid_bo (value, dialect, 1))
1320 *invalid = 1;
1321 return value;
1322 }
1323
1324 /* The BO field in a B form instruction when the + or - modifier is
1325 used. This is like the BO field, but it must be even. When
1326 extracting it, we force it to be even. */
1327
1328 static unsigned long
insert_boe(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1329 insert_boe (unsigned long insn,
1330 long value,
1331 ppc_cpu_t dialect,
1332 const char **errmsg)
1333 {
1334 if (!valid_bo (value, dialect, 0))
1335 *errmsg = _("invalid conditional option");
1336 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1337 *errmsg = _("invalid counter access");
1338 else if ((value & 1) != 0)
1339 *errmsg = _("attempt to set y bit when using + or - modifier");
1340
1341 return insn | ((value & 0x1f) << 21);
1342 }
1343
1344 static long
extract_boe(unsigned long insn,ppc_cpu_t dialect,int * invalid)1345 extract_boe (unsigned long insn,
1346 ppc_cpu_t dialect,
1347 int *invalid)
1348 {
1349 long value;
1350
1351 value = (insn >> 21) & 0x1f;
1352 if (!valid_bo (value, dialect, 1))
1353 *invalid = 1;
1354 return value & 0x1e;
1355 }
1356
1357 /* The DCMX field in a X form instruction when the field is split
1358 into separate DC, DM and DX fields. */
1359
1360 static unsigned long
insert_dcmxs(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1361 insert_dcmxs (unsigned long insn,
1362 long value,
1363 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1364 const char **errmsg ATTRIBUTE_UNUSED)
1365 {
1366 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1367 }
1368
1369 static long
extract_dcmxs(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1370 extract_dcmxs (unsigned long insn,
1371 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1372 int *invalid ATTRIBUTE_UNUSED)
1373 {
1374 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1375 }
1376
1377 /* The D field in a DX form instruction when the field is split
1378 into separate D0, D1 and D2 fields. */
1379
1380 static unsigned long
insert_dxd(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1381 insert_dxd (unsigned long insn,
1382 long value,
1383 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1384 const char **errmsg ATTRIBUTE_UNUSED)
1385 {
1386 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1387 }
1388
1389 static long
extract_dxd(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1390 extract_dxd (unsigned long insn,
1391 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1392 int *invalid ATTRIBUTE_UNUSED)
1393 {
1394 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1395 return (dxd ^ 0x8000) - 0x8000;
1396 }
1397
1398 static unsigned long
insert_dxdn(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1399 insert_dxdn (unsigned long insn,
1400 long value,
1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1402 const char **errmsg ATTRIBUTE_UNUSED)
1403 {
1404 return insert_dxd (insn, -value, dialect, errmsg);
1405 }
1406
1407 static long
extract_dxdn(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1408 extract_dxdn (unsigned long insn,
1409 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1410 int *invalid ATTRIBUTE_UNUSED)
1411 {
1412 return -extract_dxd (insn, dialect, invalid);
1413 }
1414
1415 /* FXM mask in mfcr and mtcrf instructions. */
1416
1417 static unsigned long
insert_fxm(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1418 insert_fxm (unsigned long insn,
1419 long value,
1420 ppc_cpu_t dialect,
1421 const char **errmsg)
1422 {
1423 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1424 one bit of the mask field is set. */
1425 if ((insn & (1 << 20)) != 0)
1426 {
1427 if (value == 0 || (value & -value) != value)
1428 {
1429 *errmsg = _("invalid mask field");
1430 value = 0;
1431 }
1432 }
1433
1434 /* If only one bit of the FXM field is set, we can use the new form
1435 of the instruction, which is faster. Unlike the Power4 branch hint
1436 encoding, this is not backward compatible. Do not generate the
1437 new form unless -mpower4 has been given, or -many and the two
1438 operand form of mfcr was used. */
1439 else if (value > 0
1440 && (value & -value) == value
1441 && ((dialect & PPC_OPCODE_POWER4) != 0
1442 || ((dialect & PPC_OPCODE_ANY) != 0
1443 && (insn & (0x3ff << 1)) == 19 << 1)))
1444 insn |= 1 << 20;
1445
1446 /* Any other value on mfcr is an error. */
1447 else if ((insn & (0x3ff << 1)) == 19 << 1)
1448 {
1449 /* A value of -1 means we used the one operand form of
1450 mfcr which is valid. */
1451 if (value != -1)
1452 *errmsg = _("invalid mfcr mask");
1453 value = 0;
1454 }
1455
1456 return insn | ((value & 0xff) << 12);
1457 }
1458
1459 static long
extract_fxm(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1460 extract_fxm (unsigned long insn,
1461 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1462 int *invalid)
1463 {
1464 long mask = (insn >> 12) & 0xff;
1465
1466 /* Is this a Power4 insn? */
1467 if ((insn & (1 << 20)) != 0)
1468 {
1469 /* Exactly one bit of MASK should be set. */
1470 if (mask == 0 || (mask & -mask) != mask)
1471 *invalid = 1;
1472 }
1473
1474 /* Check that non-power4 form of mfcr has a zero MASK. */
1475 else if ((insn & (0x3ff << 1)) == 19 << 1)
1476 {
1477 if (mask != 0)
1478 *invalid = 1;
1479 else
1480 mask = -1;
1481 }
1482
1483 return mask;
1484 }
1485
1486 /* The L field in an X form instruction which must have the value zero. */
1487
1488 static unsigned long
insert_l0(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1489 insert_l0 (unsigned long insn,
1490 long value,
1491 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1492 const char **errmsg)
1493 {
1494 if (value != 0)
1495 *errmsg = _("invalid operand constant");
1496 return insn & ~(0x1 << 21);
1497 }
1498
1499 static long
extract_l0(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1500 extract_l0 (unsigned long insn,
1501 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1502 int *invalid)
1503 {
1504 long value;
1505
1506 value = (insn >> 21) & 0x1;
1507 if (value != 0)
1508 *invalid = 1;
1509 return value;
1510 }
1511
1512 /* The L field in an X form instruction which must have the value one. */
1513
1514 static unsigned long
insert_l1(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1515 insert_l1 (unsigned long insn,
1516 long value,
1517 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1518 const char **errmsg)
1519 {
1520 if (value != 1)
1521 *errmsg = _("invalid operand constant");
1522 return insn | (0x1 << 21);
1523 }
1524
1525 static long
extract_l1(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1526 extract_l1 (unsigned long insn,
1527 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1528 int *invalid)
1529 {
1530 long value;
1531
1532 value = (insn >> 21) & 0x1;
1533 if (value != 1)
1534 *invalid = 1;
1535 return value;
1536 }
1537
1538 static unsigned long
insert_li20(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1539 insert_li20 (unsigned long insn,
1540 long value,
1541 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1542 const char **errmsg ATTRIBUTE_UNUSED)
1543 {
1544 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1545 }
1546
1547 static long
extract_li20(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1548 extract_li20 (unsigned long insn,
1549 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1550 int *invalid ATTRIBUTE_UNUSED)
1551 {
1552 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1553
1554 return ext
1555 | (((insn >> 11) & 0xf) << 16)
1556 | (((insn >> 17) & 0xf) << 12)
1557 | (((insn >> 16) & 0x1) << 11)
1558 | (insn & 0x7ff);
1559 }
1560
1561 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1562 For SYNC, some L values are reserved:
1563 * Value 3 is reserved on newer server cpus.
1564 * Values 2 and 3 are reserved on all other cpus. */
1565
1566 static unsigned long
insert_ls(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1567 insert_ls (unsigned long insn,
1568 long value,
1569 ppc_cpu_t dialect,
1570 const char **errmsg)
1571 {
1572 /* For SYNC, some L values are illegal. */
1573 if (((insn >> 1) & 0x3ff) == 598)
1574 {
1575 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1576 if (value > max_lvalue)
1577 {
1578 *errmsg = _("illegal L operand value");
1579 return insn;
1580 }
1581 }
1582
1583 return insn | ((value & 0x3) << 21);
1584 }
1585
1586 /* The 4-bit E field in a sync instruction that accepts 2 operands.
1587 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1588 the complement of ESYNC-bit2. */
1589
1590 static unsigned long
insert_esync(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1591 insert_esync (unsigned long insn,
1592 long value,
1593 ppc_cpu_t dialect,
1594 const char **errmsg)
1595 {
1596 unsigned long ls = (insn >> 21) & 0x03;
1597
1598 if (value == 0)
1599 {
1600 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1601 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1602 *errmsg = _("illegal L operand value");
1603 return insn;
1604 }
1605
1606 if ((ls & ~0x1)
1607 || (((value >> 1) & 0x1) ^ ls) == 0)
1608 *errmsg = _("incompatible L operand value");
1609
1610 return insn | ((value & 0xf) << 16);
1611 }
1612
1613 /* The MB and ME fields in an M form instruction expressed as a single
1614 operand which is itself a bitmask. The extraction function always
1615 marks it as invalid, since we never want to recognize an
1616 instruction which uses a field of this type. */
1617
1618 static unsigned long
insert_mbe(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1619 insert_mbe (unsigned long insn,
1620 long value,
1621 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1622 const char **errmsg)
1623 {
1624 unsigned long uval, mask;
1625 int mb, me, mx, count, last;
1626
1627 uval = value;
1628
1629 if (uval == 0)
1630 {
1631 *errmsg = _("illegal bitmask");
1632 return insn;
1633 }
1634
1635 mb = 0;
1636 me = 32;
1637 if ((uval & 1) != 0)
1638 last = 1;
1639 else
1640 last = 0;
1641 count = 0;
1642
1643 /* mb: location of last 0->1 transition */
1644 /* me: location of last 1->0 transition */
1645 /* count: # transitions */
1646
1647 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1648 {
1649 if ((uval & mask) && !last)
1650 {
1651 ++count;
1652 mb = mx;
1653 last = 1;
1654 }
1655 else if (!(uval & mask) && last)
1656 {
1657 ++count;
1658 me = mx;
1659 last = 0;
1660 }
1661 }
1662 if (me == 0)
1663 me = 32;
1664
1665 if (count != 2 && (count != 0 || ! last))
1666 *errmsg = _("illegal bitmask");
1667
1668 return insn | (mb << 6) | ((me - 1) << 1);
1669 }
1670
1671 static long
extract_mbe(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1672 extract_mbe (unsigned long insn,
1673 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1674 int *invalid)
1675 {
1676 long ret;
1677 int mb, me;
1678 int i;
1679
1680 *invalid = 1;
1681
1682 mb = (insn >> 6) & 0x1f;
1683 me = (insn >> 1) & 0x1f;
1684 if (mb < me + 1)
1685 {
1686 ret = 0;
1687 for (i = mb; i <= me; i++)
1688 ret |= 1L << (31 - i);
1689 }
1690 else if (mb == me + 1)
1691 ret = ~0;
1692 else /* (mb > me + 1) */
1693 {
1694 ret = ~0;
1695 for (i = me + 1; i < mb; i++)
1696 ret &= ~(1L << (31 - i));
1697 }
1698 return ret;
1699 }
1700
1701 /* The MB or ME field in an MD or MDS form instruction. The high bit
1702 is wrapped to the low end. */
1703
1704 static unsigned long
insert_mb6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1705 insert_mb6 (unsigned long insn,
1706 long value,
1707 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1708 const char **errmsg ATTRIBUTE_UNUSED)
1709 {
1710 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1711 }
1712
1713 static long
extract_mb6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1714 extract_mb6 (unsigned long insn,
1715 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1716 int *invalid ATTRIBUTE_UNUSED)
1717 {
1718 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1719 }
1720
1721 /* The NB field in an X form instruction. The value 32 is stored as
1722 0. */
1723
1724 static long
extract_nb(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1725 extract_nb (unsigned long insn,
1726 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1727 int *invalid ATTRIBUTE_UNUSED)
1728 {
1729 long ret;
1730
1731 ret = (insn >> 11) & 0x1f;
1732 if (ret == 0)
1733 ret = 32;
1734 return ret;
1735 }
1736
1737 /* The NB field in an lswi instruction, which has special value
1738 restrictions. The value 32 is stored as 0. */
1739
1740 static unsigned long
insert_nbi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1741 insert_nbi (unsigned long insn,
1742 long value,
1743 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1744 const char **errmsg ATTRIBUTE_UNUSED)
1745 {
1746 long rtvalue = (insn & RT_MASK) >> 21;
1747 long ravalue = (insn & RA_MASK) >> 16;
1748
1749 if (value == 0)
1750 value = 32;
1751 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1752 : ravalue))
1753 *errmsg = _("address register in load range");
1754 return insn | ((value & 0x1f) << 11);
1755 }
1756
1757 /* The NSI field in a D form instruction. This is the same as the SI
1758 field, only negated. The extraction function always marks it as
1759 invalid, since we never want to recognize an instruction which uses
1760 a field of this type. */
1761
1762 static unsigned long
insert_nsi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1763 insert_nsi (unsigned long insn,
1764 long value,
1765 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1766 const char **errmsg ATTRIBUTE_UNUSED)
1767 {
1768 return insn | (-value & 0xffff);
1769 }
1770
1771 static long
extract_nsi(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1772 extract_nsi (unsigned long insn,
1773 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1774 int *invalid)
1775 {
1776 *invalid = 1;
1777 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1778 }
1779
1780 /* The RA field in a D or X form instruction which is an updating
1781 load, which means that the RA field may not be zero and may not
1782 equal the RT field. */
1783
1784 static unsigned long
insert_ral(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1785 insert_ral (unsigned long insn,
1786 long value,
1787 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1788 const char **errmsg)
1789 {
1790 if (value == 0
1791 || (unsigned long) value == ((insn >> 21) & 0x1f))
1792 *errmsg = "invalid register operand when updating";
1793 return insn | ((value & 0x1f) << 16);
1794 }
1795
1796 /* The RA field in an lmw instruction, which has special value
1797 restrictions. */
1798
1799 static unsigned long
insert_ram(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1800 insert_ram (unsigned long insn,
1801 long value,
1802 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1803 const char **errmsg)
1804 {
1805 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1806 *errmsg = _("index register in load range");
1807 return insn | ((value & 0x1f) << 16);
1808 }
1809
1810 /* The RA field in the DQ form lq or an lswx instruction, which have special
1811 value restrictions. */
1812
1813 static unsigned long
insert_raq(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1814 insert_raq (unsigned long insn,
1815 long value,
1816 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1817 const char **errmsg)
1818 {
1819 long rtvalue = (insn & RT_MASK) >> 21;
1820
1821 if (value == rtvalue)
1822 *errmsg = _("source and target register operands must be different");
1823 return insn | ((value & 0x1f) << 16);
1824 }
1825
1826 /* The RA field in a D or X form instruction which is an updating
1827 store or an updating floating point load, which means that the RA
1828 field may not be zero. */
1829
1830 static unsigned long
insert_ras(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1831 insert_ras (unsigned long insn,
1832 long value,
1833 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1834 const char **errmsg)
1835 {
1836 if (value == 0)
1837 *errmsg = _("invalid register operand when updating");
1838 return insn | ((value & 0x1f) << 16);
1839 }
1840
1841 /* The RB field in an X form instruction when it must be the same as
1842 the RS field in the instruction. This is used for extended
1843 mnemonics like mr. This operand is marked FAKE. The insertion
1844 function just copies the BT field into the BA field, and the
1845 extraction function just checks that the fields are the same. */
1846
1847 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1848 insert_rbs (unsigned long insn,
1849 long value ATTRIBUTE_UNUSED,
1850 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1851 const char **errmsg ATTRIBUTE_UNUSED)
1852 {
1853 return insn | (((insn >> 21) & 0x1f) << 11);
1854 }
1855
1856 static long
extract_rbs(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1857 extract_rbs (unsigned long insn,
1858 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1859 int *invalid)
1860 {
1861 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1862 *invalid = 1;
1863 return 0;
1864 }
1865
1866 /* The RB field in an lswx instruction, which has special value
1867 restrictions. */
1868
1869 static unsigned long
insert_rbx(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1870 insert_rbx (unsigned long insn,
1871 long value,
1872 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1873 const char **errmsg)
1874 {
1875 long rtvalue = (insn & RT_MASK) >> 21;
1876
1877 if (value == rtvalue)
1878 *errmsg = _("source and target register operands must be different");
1879 return insn | ((value & 0x1f) << 11);
1880 }
1881
1882 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1883 static unsigned long
insert_sci8(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1884 insert_sci8 (unsigned long insn,
1885 long value,
1886 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1887 const char **errmsg)
1888 {
1889 unsigned int fill_scale = 0;
1890 unsigned long ui8 = value;
1891
1892 if ((ui8 & 0xffffff00) == 0)
1893 ;
1894 else if ((ui8 & 0xffffff00) == 0xffffff00)
1895 fill_scale = 0x400;
1896 else if ((ui8 & 0xffff00ff) == 0)
1897 {
1898 fill_scale = 1 << 8;
1899 ui8 >>= 8;
1900 }
1901 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1902 {
1903 fill_scale = 0x400 | (1 << 8);
1904 ui8 >>= 8;
1905 }
1906 else if ((ui8 & 0xff00ffff) == 0)
1907 {
1908 fill_scale = 2 << 8;
1909 ui8 >>= 16;
1910 }
1911 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1912 {
1913 fill_scale = 0x400 | (2 << 8);
1914 ui8 >>= 16;
1915 }
1916 else if ((ui8 & 0x00ffffff) == 0)
1917 {
1918 fill_scale = 3 << 8;
1919 ui8 >>= 24;
1920 }
1921 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1922 {
1923 fill_scale = 0x400 | (3 << 8);
1924 ui8 >>= 24;
1925 }
1926 else
1927 {
1928 *errmsg = _("illegal immediate value");
1929 ui8 = 0;
1930 }
1931
1932 return insn | fill_scale | (ui8 & 0xff);
1933 }
1934
1935 static long
extract_sci8(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1936 extract_sci8 (unsigned long insn,
1937 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1938 int *invalid ATTRIBUTE_UNUSED)
1939 {
1940 int fill = insn & 0x400;
1941 int scale_factor = (insn & 0x300) >> 5;
1942 long value = (insn & 0xff) << scale_factor;
1943
1944 if (fill != 0)
1945 value |= ~((long) 0xff << scale_factor);
1946 return value;
1947 }
1948
1949 static unsigned long
insert_sci8n(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1950 insert_sci8n (unsigned long insn,
1951 long value,
1952 ppc_cpu_t dialect,
1953 const char **errmsg)
1954 {
1955 return insert_sci8 (insn, -value, dialect, errmsg);
1956 }
1957
1958 static long
extract_sci8n(unsigned long insn,ppc_cpu_t dialect,int * invalid)1959 extract_sci8n (unsigned long insn,
1960 ppc_cpu_t dialect,
1961 int *invalid)
1962 {
1963 return -extract_sci8 (insn, dialect, invalid);
1964 }
1965
1966 static unsigned long
insert_sd4h(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1967 insert_sd4h (unsigned long insn,
1968 long value,
1969 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1970 const char **errmsg ATTRIBUTE_UNUSED)
1971 {
1972 return insn | ((value & 0x1e) << 7);
1973 }
1974
1975 static long
extract_sd4h(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1976 extract_sd4h (unsigned long insn,
1977 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1978 int *invalid ATTRIBUTE_UNUSED)
1979 {
1980 return ((insn >> 8) & 0xf) << 1;
1981 }
1982
1983 static unsigned long
insert_sd4w(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1984 insert_sd4w (unsigned long insn,
1985 long value,
1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1987 const char **errmsg ATTRIBUTE_UNUSED)
1988 {
1989 return insn | ((value & 0x3c) << 6);
1990 }
1991
1992 static long
extract_sd4w(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1993 extract_sd4w (unsigned long insn,
1994 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1995 int *invalid ATTRIBUTE_UNUSED)
1996 {
1997 return ((insn >> 8) & 0xf) << 2;
1998 }
1999
2000 static unsigned long
insert_oimm(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2001 insert_oimm (unsigned long insn,
2002 long value,
2003 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2004 const char **errmsg ATTRIBUTE_UNUSED)
2005 {
2006 return insn | (((value - 1) & 0x1f) << 4);
2007 }
2008
2009 static long
extract_oimm(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2010 extract_oimm (unsigned long insn,
2011 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2012 int *invalid ATTRIBUTE_UNUSED)
2013 {
2014 return ((insn >> 4) & 0x1f) + 1;
2015 }
2016
2017 /* The SH field in an MD form instruction. This is split. */
2018
2019 static unsigned long
insert_sh6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2020 insert_sh6 (unsigned long insn,
2021 long value,
2022 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2023 const char **errmsg ATTRIBUTE_UNUSED)
2024 {
2025 /* SH6 operand in the rldixor instructions. */
2026 if (PPC_OP (insn) == 4)
2027 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
2028 else
2029 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2030 }
2031
2032 static long
extract_sh6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2033 extract_sh6 (unsigned long insn,
2034 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2035 int *invalid ATTRIBUTE_UNUSED)
2036 {
2037 /* SH6 operand in the rldixor instructions. */
2038 if (PPC_OP (insn) == 4)
2039 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
2040 else
2041 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
2042 }
2043
2044 /* The SPR field in an XFX form instruction. This is flipped--the
2045 lower 5 bits are stored in the upper 5 and vice- versa. */
2046
2047 static unsigned long
insert_spr(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2048 insert_spr (unsigned long insn,
2049 long value,
2050 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2051 const char **errmsg ATTRIBUTE_UNUSED)
2052 {
2053 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2054 }
2055
2056 static long
extract_spr(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2057 extract_spr (unsigned long insn,
2058 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2059 int *invalid ATTRIBUTE_UNUSED)
2060 {
2061 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2062 }
2063
2064 /* Some dialects have 8 SPRG registers instead of the standard 4. */
2065 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
2066
2067 static unsigned long
insert_sprg(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)2068 insert_sprg (unsigned long insn,
2069 long value,
2070 ppc_cpu_t dialect,
2071 const char **errmsg)
2072 {
2073 if (value > 7
2074 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
2075 *errmsg = _("invalid sprg number");
2076
2077 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2078 user mode. Anything else must use spr 272..279. */
2079 if (value <= 3 || (insn & 0x100) != 0)
2080 value |= 0x10;
2081
2082 return insn | ((value & 0x17) << 16);
2083 }
2084
2085 static long
extract_sprg(unsigned long insn,ppc_cpu_t dialect,int * invalid)2086 extract_sprg (unsigned long insn,
2087 ppc_cpu_t dialect,
2088 int *invalid)
2089 {
2090 unsigned long val = (insn >> 16) & 0x1f;
2091
2092 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
2093 If not BOOKE, 405 or VLE, then both use only 272..275. */
2094 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
2095 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2096 || val <= 3
2097 || (val & 8) != 0)
2098 *invalid = 1;
2099 return val & 7;
2100 }
2101
2102 /* The TBR field in an XFX instruction. This is just like SPR, but it
2103 is optional. */
2104
2105 static unsigned long
insert_tbr(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)2106 insert_tbr (unsigned long insn,
2107 long value,
2108 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2109 const char **errmsg)
2110 {
2111 if (value != 268 && value != 269)
2112 *errmsg = _("invalid tbr number");
2113 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2114 }
2115
2116 static long
extract_tbr(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)2117 extract_tbr (unsigned long insn,
2118 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2119 int *invalid)
2120 {
2121 long ret;
2122
2123 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2124 if (ret != 268 && ret != 269)
2125 *invalid = 1;
2126 return ret;
2127 }
2128
2129 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2130
2131 static unsigned long
insert_xt6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2132 insert_xt6 (unsigned long insn,
2133 long value,
2134 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2135 const char **errmsg ATTRIBUTE_UNUSED)
2136 {
2137 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2138 }
2139
2140 static long
extract_xt6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2141 extract_xt6 (unsigned long insn,
2142 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2143 int *invalid ATTRIBUTE_UNUSED)
2144 {
2145 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2146 }
2147
2148 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2149 static unsigned long
insert_xtq6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2150 insert_xtq6 (unsigned long insn,
2151 long value,
2152 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2153 const char **errmsg ATTRIBUTE_UNUSED)
2154 {
2155 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2156 }
2157
2158 static long
extract_xtq6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2159 extract_xtq6 (unsigned long insn,
2160 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2161 int *invalid ATTRIBUTE_UNUSED)
2162 {
2163 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2164 }
2165
2166 /* The XA field in an XX3 form instruction. This is split. */
2167
2168 static unsigned long
insert_xa6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2169 insert_xa6 (unsigned long insn,
2170 long value,
2171 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2172 const char **errmsg ATTRIBUTE_UNUSED)
2173 {
2174 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2175 }
2176
2177 static long
extract_xa6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2178 extract_xa6 (unsigned long insn,
2179 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2180 int *invalid ATTRIBUTE_UNUSED)
2181 {
2182 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2183 }
2184
2185 /* The XB field in an XX3 form instruction. This is split. */
2186
2187 static unsigned long
insert_xb6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2188 insert_xb6 (unsigned long insn,
2189 long value,
2190 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2191 const char **errmsg ATTRIBUTE_UNUSED)
2192 {
2193 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2194 }
2195
2196 static long
extract_xb6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2197 extract_xb6 (unsigned long insn,
2198 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2199 int *invalid ATTRIBUTE_UNUSED)
2200 {
2201 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2202 }
2203
2204 /* The XB field in an XX3 form instruction when it must be the same as
2205 the XA field in the instruction. This is used for extended
2206 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2207 function just copies the XA field into the XB field, and the
2208 extraction function just checks that the fields are the same. */
2209
2210 static unsigned long
insert_xb6s(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2211 insert_xb6s (unsigned long insn,
2212 long value ATTRIBUTE_UNUSED,
2213 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2214 const char **errmsg ATTRIBUTE_UNUSED)
2215 {
2216 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2217 }
2218
2219 static long
extract_xb6s(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)2220 extract_xb6s (unsigned long insn,
2221 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2222 int *invalid)
2223 {
2224 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2225 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2226 *invalid = 1;
2227 return 0;
2228 }
2229
2230 /* The XC field in an XX4 form instruction. This is split. */
2231
2232 static unsigned long
insert_xc6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2233 insert_xc6 (unsigned long insn,
2234 long value,
2235 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2236 const char **errmsg ATTRIBUTE_UNUSED)
2237 {
2238 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2239 }
2240
2241 static long
extract_xc6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2242 extract_xc6 (unsigned long insn,
2243 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2244 int *invalid ATTRIBUTE_UNUSED)
2245 {
2246 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2247 }
2248
2249 static unsigned long
insert_dm(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)2250 insert_dm (unsigned long insn,
2251 long value,
2252 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2253 const char **errmsg)
2254 {
2255 if (value != 0 && value != 1)
2256 *errmsg = _("invalid constant");
2257 return insn | (((value) ? 3 : 0) << 8);
2258 }
2259
2260 static long
extract_dm(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)2261 extract_dm (unsigned long insn,
2262 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2263 int *invalid)
2264 {
2265 long value;
2266
2267 value = (insn >> 8) & 3;
2268 if (value != 0 && value != 3)
2269 *invalid = 1;
2270 return (value) ? 1 : 0;
2271 }
2272
2273 /* The VLESIMM field in an I16A form instruction. This is split. */
2274
2275 static unsigned long
insert_vlesi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2276 insert_vlesi (unsigned long insn,
2277 long value,
2278 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2279 const char **errmsg ATTRIBUTE_UNUSED)
2280 {
2281 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2282 }
2283
2284 static long
extract_vlesi(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2285 extract_vlesi (unsigned long insn,
2286 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2287 int *invalid ATTRIBUTE_UNUSED)
2288 {
2289 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2290 value = (value ^ 0x8000) - 0x8000;
2291 return value;
2292 }
2293
2294 static unsigned long
insert_vlensi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2295 insert_vlensi (unsigned long insn,
2296 long value,
2297 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2298 const char **errmsg ATTRIBUTE_UNUSED)
2299 {
2300 value = -value;
2301 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2302 }
2303 static long
extract_vlensi(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2304 extract_vlensi (unsigned long insn,
2305 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2306 int *invalid ATTRIBUTE_UNUSED)
2307 {
2308 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2309 value = (value ^ 0x8000) - 0x8000;
2310 /* Don't use for disassembly. */
2311 *invalid = 1;
2312 return -value;
2313 }
2314
2315 /* The VLEUIMM field in an I16A form instruction. This is split. */
2316
2317 static unsigned long
insert_vleui(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2318 insert_vleui (unsigned long insn,
2319 long value,
2320 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2321 const char **errmsg ATTRIBUTE_UNUSED)
2322 {
2323 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2324 }
2325
2326 static long
extract_vleui(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2327 extract_vleui (unsigned long insn,
2328 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2329 int *invalid ATTRIBUTE_UNUSED)
2330 {
2331 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2332 }
2333
2334 /* The VLEUIMML field in an I16L form instruction. This is split. */
2335
2336 static unsigned long
insert_vleil(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2337 insert_vleil (unsigned long insn,
2338 long value,
2339 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2340 const char **errmsg ATTRIBUTE_UNUSED)
2341 {
2342 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2343 }
2344
2345 static long
extract_vleil(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2346 extract_vleil (unsigned long insn,
2347 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2348 int *invalid ATTRIBUTE_UNUSED)
2349 {
2350 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2351 }
2352
2353
2354 /* Macros used to form opcodes. */
2355
2356 /* The main opcode. */
2357 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2358 #define OP_MASK OP (0x3f)
2359
2360 /* The main opcode combined with a trap code in the TO field of a D
2361 form instruction. Used for extended mnemonics for the trap
2362 instructions. */
2363 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2364 #define OPTO_MASK (OP_MASK | TO_MASK)
2365
2366 /* The main opcode combined with a comparison size bit in the L field
2367 of a D form or X form instruction. Used for extended mnemonics for
2368 the comparison instructions. */
2369 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2370 #define OPL_MASK OPL (0x3f,1)
2371
2372 /* The main opcode combined with an update code in D form instruction.
2373 Used for extended mnemonics for VLE memory instructions. */
2374 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2375 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2376
2377 /* An A form instruction. */
2378 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2379 #define A_MASK A (0x3f, 0x1f, 1)
2380
2381 /* An A_MASK with the FRB field fixed. */
2382 #define AFRB_MASK (A_MASK | FRB_MASK)
2383
2384 /* An A_MASK with the FRC field fixed. */
2385 #define AFRC_MASK (A_MASK | FRC_MASK)
2386
2387 /* An A_MASK with the FRA and FRC fields fixed. */
2388 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2389
2390 /* An AFRAFRC_MASK, but with L bit clear. */
2391 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2392
2393 /* A B form instruction. */
2394 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2395 #define B_MASK B (0x3f, 1, 1)
2396
2397 /* A BD8 form instruction. This is a 16-bit instruction. */
2398 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2399 #define BD8_MASK BD8 (0x3f, 1, 1)
2400
2401 /* Another BD8 form instruction. This is a 16-bit instruction. */
2402 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2403 #define BD8IO_MASK BD8IO (0x1f)
2404
2405 /* A BD8 form instruction for simplified mnemonics. */
2406 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2407 /* A mask that excludes BO32 and BI32. */
2408 #define EBD8IO1_MASK 0xf800
2409 /* A mask that includes BO32 and excludes BI32. */
2410 #define EBD8IO2_MASK 0xfc00
2411 /* A mask that include BO32 AND BI32. */
2412 #define EBD8IO3_MASK 0xff00
2413
2414 /* A BD15 form instruction. */
2415 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2416 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2417
2418 /* A BD15 form instruction for extended conditional branch mnemonics. */
2419 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2420 #define EBD15_MASK 0xfff00001
2421
2422 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2423 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2424 | (((aa) & 0xf) << 22) \
2425 | (((bo) & 0x3) << 20) \
2426 | (((bi) & 0x3) << 16) \
2427 | ((lk) & 1)
2428 #define EBD15BI_MASK 0xfff30001
2429
2430 /* A BD24 form instruction. */
2431 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2432 #define BD24_MASK BD24 (0x3f, 1, 1)
2433
2434 /* A B form instruction setting the BO field. */
2435 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2436 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2437
2438 /* A BBO_MASK with the y bit of the BO field removed. This permits
2439 matching a conditional branch regardless of the setting of the y
2440 bit. Similarly for the 'at' bits used for power4 branch hints. */
2441 #define Y_MASK (((unsigned long) 1) << 21)
2442 #define AT1_MASK (((unsigned long) 3) << 21)
2443 #define AT2_MASK (((unsigned long) 9) << 21)
2444 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2445 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2446
2447 /* A B form instruction setting the BO field and the condition bits of
2448 the BI field. */
2449 #define BBOCB(op, bo, cb, aa, lk) \
2450 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2451 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2452
2453 /* A BBOCB_MASK with the y bit of the BO field removed. */
2454 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2455 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2456 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2457
2458 /* A BBOYCB_MASK in which the BI field is fixed. */
2459 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2460 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2461
2462 /* A VLE C form instruction. */
2463 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2464 #define C_LK_MASK C_LK(0x7fff, 1)
2465 #define C(x) ((((unsigned long)(x)) & 0xffff))
2466 #define C_MASK C(0xffff)
2467
2468 /* An Context form instruction. */
2469 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2470 #define CTX_MASK CTX(0x3f, 0x7)
2471
2472 /* An User Context form instruction. */
2473 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2474 #define UCTX_MASK UCTX(0x3f, 0x1f)
2475
2476 /* The main opcode mask with the RA field clear. */
2477 #define DRA_MASK (OP_MASK | RA_MASK)
2478
2479 /* A DQ form VSX instruction. */
2480 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2481 #define DQX_MASK DQX (0x3f, 7)
2482
2483 /* A DS form instruction. */
2484 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2485 #define DS_MASK DSO (0x3f, 3)
2486
2487 /* An DX form instruction. */
2488 #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2489 #define DX_MASK DX (0x3f, 0x1f)
2490 /* An DX form instruction with the D bits specified. */
2491 #define NODX_MASK (DX_MASK | 0x1fffc1)
2492
2493 /* An EVSEL form instruction. */
2494 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2495 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2496
2497 /* An IA16 form instruction. */
2498 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2499 #define IA16_MASK IA16(0x3f, 0x1f)
2500
2501 /* An I16A form instruction. */
2502 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2503 #define I16A_MASK I16A(0x3f, 0x1f)
2504
2505 /* An I16L form instruction. */
2506 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2507 #define I16L_MASK I16L(0x3f, 0x1f)
2508
2509 /* An IM7 form instruction. */
2510 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2511 #define IM7_MASK IM7(0x1f)
2512
2513 /* An M form instruction. */
2514 #define M(op, rc) (OP (op) | ((rc) & 1))
2515 #define M_MASK M (0x3f, 1)
2516
2517 /* An LI20 form instruction. */
2518 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2519 #define LI20_MASK LI20(0x3f, 0x1)
2520
2521 /* An M form instruction with the ME field specified. */
2522 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2523
2524 /* An M_MASK with the MB and ME fields fixed. */
2525 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2526
2527 /* An M_MASK with the SH and ME fields fixed. */
2528 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2529
2530 /* An MD form instruction. */
2531 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2532 #define MD_MASK MD (0x3f, 0x7, 1)
2533
2534 /* An MD_MASK with the MB field fixed. */
2535 #define MDMB_MASK (MD_MASK | MB6_MASK)
2536
2537 /* An MD_MASK with the SH field fixed. */
2538 #define MDSH_MASK (MD_MASK | SH6_MASK)
2539
2540 /* An MDS form instruction. */
2541 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2542 #define MDS_MASK MDS (0x3f, 0xf, 1)
2543
2544 /* An MDS_MASK with the MB field fixed. */
2545 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2546
2547 /* An SC form instruction. */
2548 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2549 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2550
2551 /* An SCI8 form instruction. */
2552 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2553 #define SCI8_MASK SCI8(0x3f, 0x1f)
2554
2555 /* An SCI8 form instruction. */
2556 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2557 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2558
2559 /* An SD4 form instruction. This is a 16-bit instruction. */
2560 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2561 #define SD4_MASK SD4(0xf)
2562
2563 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2564 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2565 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2566
2567 /* An SE_R form instruction. This is a 16-bit instruction. */
2568 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2569 #define SE_R_MASK SE_R(0x3f, 0x3f)
2570
2571 /* An SE_RR form instruction. This is a 16-bit instruction. */
2572 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2573 #define SE_RR_MASK SE_RR(0x3f, 3)
2574
2575 /* A VX form instruction. */
2576 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2577
2578 /* The mask for an VX form instruction. */
2579 #define VX_MASK VX(0x3f, 0x7ff)
2580
2581 /* A VX_MASK with the VA field fixed. */
2582 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2583
2584 /* A VX_MASK with the VB field fixed. */
2585 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2586
2587 /* A VX_MASK with the VA and VB fields fixed. */
2588 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2589
2590 /* A VX_MASK with the VD and VA fields fixed. */
2591 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2592
2593 /* A VX_MASK with a UIMM4 field. */
2594 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2595
2596 /* A VX_MASK with a UIMM3 field. */
2597 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2598
2599 /* A VX_MASK with a UIMM2 field. */
2600 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2601
2602 /* A VX_MASK with a PS field. */
2603 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2604
2605 /* A VX_MASK with the VA field fixed with a PS field. */
2606 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2607
2608 /* A VA form instruction. */
2609 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2610
2611 /* The mask for an VA form instruction. */
2612 #define VXA_MASK VXA(0x3f, 0x3f)
2613
2614 /* A VXA_MASK with a SHB field. */
2615 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2616
2617 /* A VXR form instruction. */
2618 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2619
2620 /* The mask for a VXR form instruction. */
2621 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2622
2623 /* A VX form instruction with a VA tertiary opcode. */
2624 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2625
2626 #define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2627 #define VXASH_MASK VXASH (0x3f, 0x1f)
2628
2629 /* An X form instruction. */
2630 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2631
2632 /* A X form instruction for Quad-Precision FP Instructions. */
2633 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2634
2635 /* An EX form instruction. */
2636 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2637
2638 /* The mask for an EX form instruction. */
2639 #define EX_MASK EX (0x3f, 0x7ff)
2640
2641 /* An XX2 form instruction. */
2642 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2643
2644 /* A XX2 form instruction with the VA bits specified. */
2645 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2646
2647 /* An XX3 form instruction. */
2648 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2649
2650 /* An XX3 form instruction with the RC bit specified. */
2651 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2652
2653 /* An XX4 form instruction. */
2654 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2655
2656 /* A Z form instruction. */
2657 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2658
2659 /* An X form instruction with the RC bit specified. */
2660 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2661
2662 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2663 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2664
2665 /* An X form instruction with the RA bits specified as two ops. */
2666 #define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2667
2668 /* A Z form instruction with the RC bit specified. */
2669 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2670
2671 /* The mask for an X form instruction. */
2672 #define X_MASK XRC (0x3f, 0x3ff, 1)
2673
2674 /* The mask for an X form instruction with the BF bits specified. */
2675 #define XBF_MASK (X_MASK | (3 << 21))
2676
2677 /* An X form wait instruction with everything filled in except the WC field. */
2678 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2679
2680 /* The mask for an XX1 form instruction. */
2681 #define XX1_MASK X (0x3f, 0x3ff)
2682
2683 /* An XX1_MASK with the RB field fixed. */
2684 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2685
2686 /* The mask for an XX2 form instruction. */
2687 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2688
2689 /* The mask for an XX2 form instruction with the UIM bits specified. */
2690 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2691
2692 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2693 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2694
2695 /* The mask for an XX2 form instruction with the BF bits specified. */
2696 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2697
2698 /* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2699 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2700
2701 /* The mask for an XX2 form instruction with a split DCMX bits specified. */
2702 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2703
2704 /* The mask for an XX3 form instruction. */
2705 #define XX3_MASK XX3 (0x3f, 0xff)
2706
2707 /* The mask for an XX3 form instruction with the BF bits specified. */
2708 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2709
2710 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2711 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2712 #define XX3SHW_MASK XX3DM_MASK
2713
2714 /* The mask for an XX4 form instruction. */
2715 #define XX4_MASK XX4 (0x3f, 0x3)
2716
2717 /* An X form wait instruction with everything filled in except the WC field. */
2718 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2719
2720 /* The mask for an XMMF form instruction. */
2721 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2722
2723 /* The mask for a Z form instruction. */
2724 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2725 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2726
2727 /* An X_MASK with the RA/VA field fixed. */
2728 #define XRA_MASK (X_MASK | RA_MASK)
2729 #define XVA_MASK XRA_MASK
2730
2731 /* An XRA_MASK with the A_L/W field clear. */
2732 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2733 #define XRLA_MASK XWRA_MASK
2734
2735 /* An X_MASK with the RB field fixed. */
2736 #define XRB_MASK (X_MASK | RB_MASK)
2737
2738 /* An X_MASK with the RT field fixed. */
2739 #define XRT_MASK (X_MASK | RT_MASK)
2740
2741 /* An XRT_MASK mask with the L bits clear. */
2742 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2743
2744 /* An X_MASK with the RA and RB fields fixed. */
2745 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2746
2747 /* An XBF_MASK with the RA and RB fields fixed. */
2748 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2749
2750 /* An XRARB_MASK, but with the L bit clear. */
2751 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2752
2753 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2754 #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2755
2756 /* An X_MASK with the RT and RA fields fixed. */
2757 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2758
2759 /* An X_MASK with the RT and RB fields fixed. */
2760 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2761
2762 /* An XRTRA_MASK, but with L bit clear. */
2763 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2764
2765 /* An X_MASK with the RT, RA and RB fields fixed. */
2766 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2767
2768 /* An XRTRARB_MASK, but with L bit clear. */
2769 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2770
2771 /* An XRTRARB_MASK, but with A bit clear. */
2772 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2773
2774 /* An XRTRARB_MASK, but with BF bits clear. */
2775 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2776
2777 /* An X form instruction with the L bit specified. */
2778 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2779
2780 /* An X form instruction with the L bits specified. */
2781 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2782
2783 /* An X form instruction with the L bit and RC bit specified. */
2784 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2785
2786 /* An X form instruction with RT fields specified */
2787 #define XRT(op, xop, rt) (X ((op), (xop)) \
2788 | ((((unsigned long)(rt)) & 0x1f) << 21))
2789
2790 /* An X form instruction with RT and RA fields specified */
2791 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2792 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2793 | ((((unsigned long)(ra)) & 0x1f) << 16))
2794
2795 /* The mask for an X form comparison instruction. */
2796 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2797
2798 /* The mask for an X form comparison instruction with the L field
2799 fixed. */
2800 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2801
2802 /* An X form trap instruction with the TO field specified. */
2803 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2804 #define XTO_MASK (X_MASK | TO_MASK)
2805
2806 /* An X form tlb instruction with the SH field specified. */
2807 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2808 #define XTLB_MASK (X_MASK | SH_MASK)
2809
2810 /* An X form sync instruction. */
2811 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2812
2813 /* An X form sync instruction with everything filled in except the LS field. */
2814 #define XSYNC_MASK (0xff9fffff)
2815
2816 /* An X form sync instruction with everything filled in except the L and E fields. */
2817 #define XSYNCLE_MASK (0xff90ffff)
2818
2819 /* An X_MASK, but with the EH bit clear. */
2820 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2821
2822 /* An X form AltiVec dss instruction. */
2823 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2824 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2825
2826 /* An XFL form instruction. */
2827 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2828 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2829
2830 /* An X form isel instruction. */
2831 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2832 #define XISEL_MASK XISEL(0x3f, 0x1f)
2833
2834 /* An XL form instruction with the LK field set to 0. */
2835 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2836
2837 /* An XL form instruction which uses the LK field. */
2838 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2839
2840 /* The mask for an XL form instruction. */
2841 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2842
2843 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2844 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2845
2846 /* An XL form instruction which explicitly sets the BO field. */
2847 #define XLO(op, bo, xop, lk) \
2848 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2849 #define XLO_MASK (XL_MASK | BO_MASK)
2850
2851 /* An XL form instruction which explicitly sets the y bit of the BO
2852 field. */
2853 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2854 #define XLYLK_MASK (XL_MASK | Y_MASK)
2855
2856 /* An XL form instruction which sets the BO field and the condition
2857 bits of the BI field. */
2858 #define XLOCB(op, bo, cb, xop, lk) \
2859 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2860 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2861
2862 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2863 #define XLBB_MASK (XL_MASK | BB_MASK)
2864 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2865 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2866
2867 /* A mask for branch instructions using the BH field. */
2868 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2869
2870 /* An XL_MASK with the BO and BB fields fixed. */
2871 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2872
2873 /* An XL_MASK with the BO, BI and BB fields fixed. */
2874 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2875
2876 /* An X form mbar instruction with MO field. */
2877 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2878
2879 /* An XO form instruction. */
2880 #define XO(op, xop, oe, rc) \
2881 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2882 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2883
2884 /* An XO_MASK with the RB field fixed. */
2885 #define XORB_MASK (XO_MASK | RB_MASK)
2886
2887 /* An XOPS form instruction for paired singles. */
2888 #define XOPS(op, xop, rc) \
2889 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2890 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2891
2892
2893 /* An XS form instruction. */
2894 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2895 #define XS_MASK XS (0x3f, 0x1ff, 1)
2896
2897 /* A mask for the FXM version of an XFX form instruction. */
2898 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2899
2900 /* An XFX form instruction with the FXM field filled in. */
2901 #define XFXM(op, xop, fxm, p4) \
2902 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2903 | ((unsigned long)(p4) << 20))
2904
2905 /* An XFX form instruction with the SPR field filled in. */
2906 #define XSPR(op, xop, spr) \
2907 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2908 #define XSPR_MASK (X_MASK | SPR_MASK)
2909
2910 /* An XFX form instruction with the SPR field filled in except for the
2911 SPRBAT field. */
2912 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2913
2914 /* An XFX form instruction with the SPR field filled in except for the
2915 SPRG field. */
2916 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2917
2918 /* An X form instruction with everything filled in except the E field. */
2919 #define XE_MASK (0xffff7fff)
2920
2921 /* An X form user context instruction. */
2922 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2923 #define XUC_MASK XUC(0x3f, 0x1f)
2924
2925 /* An XW form instruction. */
2926 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2927 /* The mask for a G form instruction. rc not supported at present. */
2928 #define XW_MASK XW (0x3f, 0x3f, 0)
2929
2930 /* An APU form instruction. */
2931 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2932
2933 /* The mask for an APU form instruction. */
2934 #define APU_MASK APU (0x3f, 0x3ff, 1)
2935 #define APU_RT_MASK (APU_MASK | RT_MASK)
2936 #define APU_RA_MASK (APU_MASK | RA_MASK)
2937
2938 /* The BO encodings used in extended conditional branch mnemonics. */
2939 #define BODNZF (0x0)
2940 #define BODNZFP (0x1)
2941 #define BODZF (0x2)
2942 #define BODZFP (0x3)
2943 #define BODNZT (0x8)
2944 #define BODNZTP (0x9)
2945 #define BODZT (0xa)
2946 #define BODZTP (0xb)
2947
2948 #define BOF (0x4)
2949 #define BOFP (0x5)
2950 #define BOFM4 (0x6)
2951 #define BOFP4 (0x7)
2952 #define BOT (0xc)
2953 #define BOTP (0xd)
2954 #define BOTM4 (0xe)
2955 #define BOTP4 (0xf)
2956
2957 #define BODNZ (0x10)
2958 #define BODNZP (0x11)
2959 #define BODZ (0x12)
2960 #define BODZP (0x13)
2961 #define BODNZM4 (0x18)
2962 #define BODNZP4 (0x19)
2963 #define BODZM4 (0x1a)
2964 #define BODZP4 (0x1b)
2965
2966 #define BOU (0x14)
2967
2968 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2969 #define BO16F (0x0)
2970 #define BO16T (0x1)
2971
2972 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2973 #define BO32F (0x0)
2974 #define BO32T (0x1)
2975 #define BO32DNZ (0x2)
2976 #define BO32DZ (0x3)
2977
2978 /* The BI condition bit encodings used in extended conditional branch
2979 mnemonics. */
2980 #define CBLT (0)
2981 #define CBGT (1)
2982 #define CBEQ (2)
2983 #define CBSO (3)
2984
2985 /* The TO encodings used in extended trap mnemonics. */
2986 #define TOLGT (0x1)
2987 #define TOLLT (0x2)
2988 #define TOEQ (0x4)
2989 #define TOLGE (0x5)
2990 #define TOLNL (0x5)
2991 #define TOLLE (0x6)
2992 #define TOLNG (0x6)
2993 #define TOGT (0x8)
2994 #define TOGE (0xc)
2995 #define TONL (0xc)
2996 #define TOLT (0x10)
2997 #define TOLE (0x14)
2998 #define TONG (0x14)
2999 #define TONE (0x18)
3000 #define TOU (0x1f)
3001
3002 /* Smaller names for the flags so each entry in the opcodes table will
3003 fit on a single line. */
3004 #undef PPC
3005 #define PPC PPC_OPCODE_PPC
3006 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3007 #define POWER4 PPC_OPCODE_POWER4
3008 #define POWER5 PPC_OPCODE_POWER5
3009 #define POWER6 PPC_OPCODE_POWER6
3010 #define POWER7 PPC_OPCODE_POWER7
3011 #define POWER8 PPC_OPCODE_POWER8
3012 #define POWER9 PPC_OPCODE_POWER9
3013 #define CELL PPC_OPCODE_CELL
3014 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
3015 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
3016 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
3017 #define PPC403 PPC_OPCODE_403
3018 #define PPC405 PPC_OPCODE_405
3019 #define PPC440 PPC_OPCODE_440
3020 #define PPC464 PPC440
3021 #define PPC476 PPC_OPCODE_476
3022 #define PPC750 PPC_OPCODE_750
3023 #define PPC7450 PPC_OPCODE_7450
3024 #define PPC860 PPC_OPCODE_860
3025 #define PPCPS PPC_OPCODE_PPCPS
3026 #define PPCVEC PPC_OPCODE_ALTIVEC
3027 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
3028 #define PPCVEC3 PPC_OPCODE_ALTIVEC2
3029 #define PPCVSX PPC_OPCODE_VSX
3030 #define PPCVSX2 PPC_OPCODE_VSX
3031 #define PPCVSX3 PPC_OPCODE_VSX3
3032 #define POWER PPC_OPCODE_POWER
3033 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3034 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3035 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3036 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3037 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3038 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3039 #define MFDEC1 PPC_OPCODE_POWER
3040 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
3041 #define BOOKE PPC_OPCODE_BOOKE
3042 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
3043 #define PPCE300 PPC_OPCODE_E300
3044 #define PPCSPE PPC_OPCODE_SPE
3045 #define PPCISEL PPC_OPCODE_ISEL
3046 #define PPCEFS PPC_OPCODE_EFS
3047 #define PPCBRLK PPC_OPCODE_BRLOCK
3048 #define PPCPMR PPC_OPCODE_PMR
3049 #define PPCTMR PPC_OPCODE_TMR
3050 #define PPCCHLK PPC_OPCODE_CACHELCK
3051 #define PPCRFMCI PPC_OPCODE_RFMCI
3052 #define E500MC PPC_OPCODE_E500MC
3053 #define PPCA2 PPC_OPCODE_A2
3054 #define TITAN PPC_OPCODE_TITAN
3055 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
3056 #define E500 PPC_OPCODE_E500
3057 #define E6500 PPC_OPCODE_E6500
3058 #define PPCVLE PPC_OPCODE_VLE
3059 #define PPCHTM PPC_OPCODE_HTM
3060 /* The list of embedded processors that use the embedded operand ordering
3061 for the 3 operand dcbt and dcbtst instructions. */
3062 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3063 | PPC_OPCODE_A2)
3064
3065
3066
3067 /* The opcode table.
3068
3069 The format of the opcode table is:
3070
3071 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3072
3073 NAME is the name of the instruction.
3074 OPCODE is the instruction opcode.
3075 MASK is the opcode mask; this is used to tell the disassembler
3076 which bits in the actual opcode must match OPCODE.
3077 FLAGS are flags indicating which processors support the instruction.
3078 ANTI indicates which processors don't support the instruction.
3079 OPERANDS is the list of operands.
3080
3081 The disassembler reads the table in order and prints the first
3082 instruction which matches, so this table is sorted to put more
3083 specific instructions before more general instructions.
3084
3085 This table must be sorted by major opcode. Please try to keep it
3086 vaguely sorted within major opcode too, except of course where
3087 constrained otherwise by disassembler operation. */
3088
3089 const struct powerpc_opcode powerpc_opcodes[] = {
3090 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3091 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3092 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3093 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3094 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3095 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3096 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3097 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3098 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3099 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3100 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3101 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3102 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3103 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3104 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3105 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3106 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3107
3108 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3109 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3110 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3111 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3112 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3113 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3114 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3115 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3116 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3117 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3118 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3119 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3120 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3121 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3122 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3123 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3124 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3125 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3126 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3127 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3128 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3129 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3130 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3131 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3132 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3133 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3134 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3135 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3136 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3137 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3138 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3139 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3140
3141 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3142 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3143 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3144 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3145 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3146 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3147 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3148 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3149 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3150 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3151 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3152 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3153 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3154 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3155 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3156 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3157 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3158 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3159 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3160 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3161 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3162 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3163 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3164 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3165 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3166 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3167 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3168 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3169 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3170 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3171 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3172 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3173 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3174 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3175 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3176 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3177 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3178 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3179 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3180 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3181 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3182 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3183 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3184 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3185 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3186 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3187 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3188 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3189 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3190 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3191 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3192 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3193 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3194 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3195 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3196 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3197 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3198 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3199 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3200 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3201 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3202 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3203 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3204 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3205 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3206 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3207 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3208 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3209 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3210 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3211 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3212 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3213 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3214 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3215 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3216 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3217 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3218 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3219 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3220 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3221 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3222 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3223 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3224 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3225 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3226 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3227 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3228 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3229 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3230 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3231 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3232 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3233 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3234 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3235 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3236 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3237 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3238 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3239 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3240 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3241 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3242 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3243 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3244 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3245 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3246 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3247 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3248 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3249 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3250 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3251 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3252 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3253 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3254 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3255 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3256 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3257 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3258 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3259 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3260 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3261 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3262 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3263 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3264 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3265 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3266 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3267 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3268 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3269 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3270 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3271 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3272 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3273 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3274 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3275 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3276 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3277 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3278 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3279 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3280 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3281 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3282 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3283 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3284 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3285 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3286 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3287 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3288 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3289 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3290 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3291 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3292 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3293 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3294 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3295 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3296 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3297 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3298 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3299 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3300 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3301 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3302 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3303 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3304 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3305 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3306 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3307 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3308 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3309 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3310 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3311 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3312 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3313 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3314 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3315 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3316 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3317 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3318 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3319 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3320 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3321 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3322 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3323 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3324 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3325 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3326 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3327 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3328 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3329 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3330 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3331 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3332 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3333 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3334 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3335 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3336 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3337 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3338 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3339 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3340 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3341 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3342 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3343 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3344 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3345 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3346 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3347 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3348 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3349 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3350 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3351 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3352 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3353 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3354 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3355 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3356 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3357 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3358 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3359 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3360 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3361 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3362 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3363 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3364 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3365 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3366 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3367 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3368 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3369 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3370 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3371 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3372 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3373 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3374 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3375 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3376 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3377 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3378 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3379 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3380 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3381 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3382 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3383 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3384 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3385 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3386 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3387 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3388 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3389 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3390 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3391 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3392 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3393 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3394 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3395 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3396 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3397 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3398 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3399 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3400 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3401 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3402 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3403 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3404 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3405 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3406 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3407 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3408 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3409 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3410 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3411 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3412 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3413 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3414 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3415 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3416 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3417 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3418 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3419 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3420 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3421 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3422 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3423 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3424 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3425 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3426 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3427 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3428 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3429 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3430 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3431 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3432 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3433 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3434 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3435 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3436 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3437 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3438 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3439 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3440 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3441 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3442 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3443 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3444 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3445 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3446 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3447 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3448 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3449 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3450 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3451 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3452 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3453 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3454 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3455 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3456 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3457 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3458 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3459 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3460 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3461 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3462 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3463 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3464 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3465 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3466 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3467 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3468 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3469 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3470 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3471 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3472 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3473 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3474 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3475 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3476 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3477 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3478 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3479 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3480 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3481 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3482 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3483 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3484 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3485 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3486 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3487 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3488 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3489 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3490 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3491 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3492 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3493 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3494 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3495 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3496 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3497 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3498 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3499 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3500 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3501 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3502 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3503 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3504 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3505 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3506 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3507 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3508 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3509 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3510 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3511 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3512 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3513 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3514 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3515 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3516 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3517 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3518 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3519 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3520 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3521 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3522 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3523 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3524 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3525 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3526 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3527 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3528 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3529 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3530 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3531 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3532 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3533 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3534 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3535 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3536 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3537 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3538 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3539 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3540 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3541 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3542 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3543 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3544 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3545 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3546 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3547 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3548 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3549 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3550 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3551 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3552 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3553 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3554 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3555 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3556 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3557 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3558 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3559 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3560 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3561 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3562 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3563 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3564 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3565 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3566 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3567 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3568 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3569 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3570 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3571 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3572 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3573 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3574 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3575 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3576 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3577 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3578 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3579 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3580 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3581 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3582 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3583 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3584 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3585 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3586 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3588 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3589 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3590 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3591 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3592 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3593 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3594 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3595 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3596 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3597 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3598 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3599 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3600 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3601 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3602 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3603 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3604 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3605 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3606 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3607 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3608 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3609 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3610 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3611 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3612 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3613 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3614 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3615 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3616 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3617 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3618 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3619 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3620 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3621 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3622 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3623 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3624 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3625 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3626 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3627 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3628 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3629 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3630 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3631 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3632 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3633 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3634 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3635 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3636 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3637 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3638 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3639 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3640 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3641 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3642 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3643 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3644 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3645 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3646 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3647 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3648 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3649 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3650 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3651 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3652 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3653 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3654 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3655 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3656 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3657 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3658 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3659 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3660 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3661 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3662 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3663 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3664 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3665 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3666 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3667 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3668 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3669 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3670 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3671 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3672 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3673 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3674 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3675 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3676 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3677 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3678 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3679 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3680 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3681 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3682 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3683 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3684 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3685 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3686 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3687 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3688 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3689 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3690 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3691 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3692 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3693 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3694 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3695 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3696 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3697 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3698 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3699 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3700 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3702 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3703 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3704 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3705 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3706 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3707 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3708 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3709 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3710 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3711 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3712 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3713 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3714 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3715 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3716 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3717 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3718 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3719 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3720 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3721 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3722 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3723 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3724 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3725 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3726 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3727 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3728 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3729 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3730 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3731 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3732 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3733 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3734 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3735 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3736 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3737 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3738 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3739 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3740 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3741 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3742 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3743 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3744 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3745 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3746 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3747 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3748 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3749 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3750 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3751 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3752 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3753 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3754 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3755 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3756 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3757 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3758 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3759 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3760 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3761 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3762 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3763 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3764 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3765 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3766 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3767 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3768 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3769 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3770 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3771 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3772 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3773 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3774 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3775 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3776 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3777 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3778 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3779 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3780 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3781 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3782 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3783 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3784 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3785 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3786 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3787 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3788 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3789 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3790 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3791 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3792 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3793 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3794 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3795 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3796 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3797 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3798 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3799 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3800 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3801 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3802 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3803 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3804 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3805 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3806 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3807 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3808 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3809 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3810 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3811 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3812 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3813 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3814 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3815 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3816 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3817 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3818 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3819 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3820 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3821 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3822 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3823 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3824 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3825 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3826 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3827 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3828 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3829 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3830 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3831 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3832 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3833 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3834 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3835 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3836 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3837 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3838 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3839 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3840 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3841 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3842 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3843 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3844 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3845 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3846 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3847 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3848 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3849 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3850 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3851 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3852 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3853 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3854 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3855 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3856 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3857 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3858 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3859 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3860 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3861 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3862 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3863 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3864 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3865 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3866 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3867 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3868 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3869 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3870 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3871 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3872 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3873 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3874 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3875 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3876 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3877
3878 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3879 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3880
3881 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3882 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3883
3884 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3885
3886 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3887 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
3888 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
3889 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3890
3891 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3892 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
3893 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
3894 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3895
3896 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3897 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3898 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3899
3900 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3901 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3902 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3903
3904 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3905 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3906 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3907 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3908 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3909 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3910
3911 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3912 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3913 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3914 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3915 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3916
3917 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3918 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3919 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3920 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3921 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3922 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3923 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3924 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3925 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3926 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3927 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3928 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3929 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3930 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3931 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3932 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3933 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3934 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3935 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
3936 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3937 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3938 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
3939 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3940 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3941 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3942 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3943 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3944 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3945
3946 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3947 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3948 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3949 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3950 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3951 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3952 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3953 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3954 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3955 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3956 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3957 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3958 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3959 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3960 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3961 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3962 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3963 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3964 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3965 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3966 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3967 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3968 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3969 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3970 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3971 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3972 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3973 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3974 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3975 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3976 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3977 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3978 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3979 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3980 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3981 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3982 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3983 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3984 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3985 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3986 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3987 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3988 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3989 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3990 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3991 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3992 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3993 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3994 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3995 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3996 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3997 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3998 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3999 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4000 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4001 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4002 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4003 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4004 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4005 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4006 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4007 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4008 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4009 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4010 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4011 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4012 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4013 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4014 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4015 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4016 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4017 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4018 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4019 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4020 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4021 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4022 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4023 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4024 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4025 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4026 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4027 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4028 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4029 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4030
4031 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4032 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4033 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4034 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4035 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4036 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4037 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4038 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4039 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4040 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4041 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4042 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4043 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4044 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4045 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4046 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4047 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4048 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4049 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4050 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4051 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4052 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4053 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4054 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4055 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4056 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4057 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4058 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4059 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4060 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4061 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4062 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4063 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4064 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4065 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4066 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4067 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4068 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4069 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4070 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4071 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4072 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4073 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4074 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4075 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4076 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4077 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4078 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4079 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4080 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4081 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4082 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4083 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4084 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4085 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4086 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4087 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4088 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4089 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4090 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4091
4092 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4093 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4094 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4095 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4096 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4097 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4098 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4099 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4100 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4101 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4102 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4103 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4104 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4105 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4106 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4107 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4108 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4109 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4110 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4111 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4112 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4113 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4114 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4115 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4116
4117 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4118 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4119 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4120 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4121 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4122 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4123 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4124 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4125 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4126 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4127 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4128 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4129 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4130 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4131 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4132 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4133
4134 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4135 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4136 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4137 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4138 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4139 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4140 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4141 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4142 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4143 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4144 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4145 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4146 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4147 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4148 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4149 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4150 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4151 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4152 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4153 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4154 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4155 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4156 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4157 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4158
4159 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4160 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4161 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4162 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4163 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4164 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4165 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4166 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4167 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4168 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4169 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4170 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4171 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4172 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4173 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4174 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4175
4176 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4177 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4178 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4179 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4180 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4181 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4182 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4183 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4184 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4185 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4186 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4187 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4188
4189 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4190 {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
4191 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4192 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4193 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4194 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4195
4196 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4197 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4198 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4199 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4200
4201 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4202
4203 {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
4204 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4205 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4206
4207 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4208 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4209 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4210 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4211 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4212 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4213 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4214 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4215 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4216 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4217 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4218 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4219 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4220 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4221 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4222 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4223 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4224 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4225 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4226 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4227 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4228 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4229 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4230 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4231
4232 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4233 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4234 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4235 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4236 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4237 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4238 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4239 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4240 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4241 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4242 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4243 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4244 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4245 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4246 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4247 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4248 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4249 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4250 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4251 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4252 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4253 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4254 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4255 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4256 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4257 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4258 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4259 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4260 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4261 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4262 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4263 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4264 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4265 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4266 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4267 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4268 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4269 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4270 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4271 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4272 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4273 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4274 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4275 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4276 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4277 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4278 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4279 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4280 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4281 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4282 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4283 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4284 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4285 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4286 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4287 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4288 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4289 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4290 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4291 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4292 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4293 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4294 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4295 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4296 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4297 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4298 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4299 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4300 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4301 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4302 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4303 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4304 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4305 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4306 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4307 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4308 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4309 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4310 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4311 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4312 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4313 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4314 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4315 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4316 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4317 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4318 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4319 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4320 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4321 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4322 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4323 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4324 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4325 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4326 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4327 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4328 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4329 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4330 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4331 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4332 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4333 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4334 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4335 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4336 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4337 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4338 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4339 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4340 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4341 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4342 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4343 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4344 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4345 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4346 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4347 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4348 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4349 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4350 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4351 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4352 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4353 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4354 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4355 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4356 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4357 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4358 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4359 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4360 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4361 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4362 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4363 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4364 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4365 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4366 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4367 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4368 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4369 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4370 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4371 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4372
4373 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4374 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4375 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4376 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4377 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4378 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4379 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4380 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4381 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4382 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4383 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4384 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4385 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4386 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4387 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4388 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4389 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4390 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4391 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4392 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4393 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4394 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4395 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4396 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4397 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4398 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4399 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4400 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4401 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4402 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4403 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4404 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4405 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4406 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4407 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4408 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4409 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4410 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4411 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4412 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4413 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4414 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4415 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4416 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4417 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4418 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4419 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4420 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4421
4422 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4423 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4424 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4425 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4426 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4427 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4428 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4429 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4430
4431 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4432
4433 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4434 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4435 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4436
4437 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4438 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4439 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4440
4441 {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
4442 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4443
4444 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4445
4446 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4447
4448 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4449
4450 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4451 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4452
4453 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4454 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4455
4456 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4457
4458 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4459
4460 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4461
4462 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4463
4464 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4465 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4466
4467 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4468 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4469
4470 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4471
4472 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4473
4474 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4475
4476 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4477 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4478
4479 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4480 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4481
4482 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4483 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4484
4485 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4486 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4487 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4488 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4489 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4490 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4491 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4492 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4493 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4494 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4495 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4496 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4497 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4498 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4499 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4500 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4501 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4502 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4503 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4504 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4505 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4506 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4507 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4508 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4509 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4510 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4511 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4512 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4513 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4514 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4515 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4516 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4517 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4518 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4519 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4520 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4521 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4522 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4523 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4524 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4525 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4526 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4527 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4528 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4529 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4530 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4531 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4532 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4533 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4534 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4535 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4536 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4537 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4538 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4539 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4540 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4541 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4542 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4543 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4544 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4545 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4546 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4547 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4548 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4549 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4550 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4551 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4552 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4553 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4554 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4556 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4557 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4558 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4559 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4560 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4561 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4562 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4563 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4564 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4565 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4566 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4567 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4568 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4569 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4570 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4571 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4572 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4573 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4574 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4575 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4576 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4577 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4578 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4579 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4580 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4581 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4582 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4583 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4584 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4585 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4586 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4587 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4588 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4589 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4590 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4591 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4592 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4593 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4594 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4595 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4596 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4597 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4598 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4599 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4600 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4601 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4602 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4603 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4604 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4605
4606 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4607 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4608 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4609 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4610 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4611 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4612 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4613 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4614 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4615 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4616 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4617 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4618 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4619 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4620 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4621 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4622 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4623 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4624 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4625 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4626
4627 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4628 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4629 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4630 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4631 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4632 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4633 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4634 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4635
4636 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4637 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4638 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4639 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4640 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4641 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4642
4643 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4644 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4645
4646 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4647 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4648
4649 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4650 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4651 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4652 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4653 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4654 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4655 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4656 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4657
4658 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4659 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4660
4661 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4662 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4663 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4664 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4665 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4666 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4667
4668 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4669 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4670 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4671
4672 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4673 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4674
4675 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4676 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4677 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4678
4679 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4680 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4681
4682 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4683 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4684
4685 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4686 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4687
4688 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4689 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4690 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4691 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4692 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4693 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4694
4695 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4696 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4697
4698 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4699 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4700
4701 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4702 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4703
4704 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4705 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4706 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4707 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4708
4709 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4710 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4711
4712 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4713 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4714 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
4715 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4716
4717 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4718 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4719 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4720 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4721 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4722 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4723 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4724 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4725 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4726 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4727 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4728 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4729 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4730 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4731 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4732 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4733 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4734 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4735 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4736 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4737 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4738 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4739 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4740 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4741 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4742 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4743 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4744 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4745 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4746 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4747 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4748 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4749 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4750
4751 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4752 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4753 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4754
4755 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4756 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4757 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4758 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4759 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4760 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4761
4762 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4763 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4764
4765 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4766 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4767 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4768 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4769
4770 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4771 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4772
4773 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4774
4775 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4776
4777 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4778 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4779 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4780 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4781
4782 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4783 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4784
4785 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4786
4787 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4788
4789 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4790
4791 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4792 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4793
4794 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4795 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4796 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4797 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4798
4799 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4800 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4801 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4802 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4803
4804 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4805 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4806
4807 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4808 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4809
4810 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4811 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4812
4813 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4814
4815 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4816 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4817
4818 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4819
4820 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4821 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4822 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
4823 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4824
4825 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4826 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4827 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4828
4829 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4830
4831 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4832
4833 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4834
4835 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4836
4837 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4838
4839 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4840
4841 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4842
4843 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4844 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4845 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4846 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4847
4848 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4849 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4850 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4851 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4852
4853 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4854
4855 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4856
4857 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4858
4859 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4860 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4861
4862 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4863 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4864
4865 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4866 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4867
4868 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4869 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4870 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4871
4872 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4873
4874 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4875 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4876 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4877 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4878 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4879 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4880 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4881 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4882 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4883 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4884 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4885 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4886 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4887 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4888 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4889 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4890
4891 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4892 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4893 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4894
4895 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4896 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4897
4898 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4899 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4900
4901 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4902
4903 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4904
4905 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4906
4907 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4908 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
4909
4910 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4911
4912 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4913
4914 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
4915
4916 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4917 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4918
4919 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4920 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4921
4922 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4923 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4924
4925 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4926
4927 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4928
4929 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4930 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4931 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4932
4933 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4934
4935 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4936
4937 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4938
4939 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
4940
4941 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4942 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4943 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4944 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4945
4946 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4947
4948 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4949
4950 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
4951
4952 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4953
4954 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4955 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4956
4957 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4958 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4959 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4960 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4961
4962 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4963 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4964 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4965 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4966
4967 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4968
4969 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4970 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4971
4972 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4973 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4974 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
4975
4976 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
4977
4978 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
4979
4980 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4981 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4982
4983 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
4984
4985 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
4986
4987 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4988 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
4989
4990 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4991 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
4992
4993 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4994 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
4995
4996 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
4997
4998 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4999
5000 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5001
5002 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
5003
5004 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5005
5006 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5007 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5008
5009 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
5010
5011 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5012 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
5013
5014 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
5015
5016 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5017 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5018 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5019 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
5020
5021 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
5022
5023 {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
5024 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
5025
5026 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5027 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5028
5029 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5030 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
5031
5032 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
5033
5034 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
5035
5036 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5037
5038 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5039 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5040
5041 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5042 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5043 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5044 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5045
5046 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5047 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5048 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5049 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5050
5051 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5052
5053 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
5054
5055 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5056 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5057 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5058 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
5059
5060 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5061
5062 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
5063
5064 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
5065
5066 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5067 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
5068
5069 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5070 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
5071
5072 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5073
5074 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
5075
5076 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5077
5078 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5079 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5080
5081 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5082 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5083 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5084 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5085
5086 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5087 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5088
5089 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5090 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5091 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5092 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5093
5094 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5095 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5096 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5097 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5098
5099 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5100 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5101 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5102 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
5103
5104 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5105 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5106 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5107
5108 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5109 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5110 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5111 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5112
5113 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
5114
5115 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5116 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
5117
5118 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
5119
5120 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5121
5122 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5123 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
5124
5125 {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5126
5127 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
5128
5129 {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5130
5131 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5132 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5133 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5134
5135 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5136
5137 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5138 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5139 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5140 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5141
5142 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5143
5144 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5145 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5146
5147 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
5148
5149 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5150 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
5151
5152 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
5153
5154 {"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
5155
5156 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5157 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5158
5159 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5160 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5161 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5162 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5163
5164 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5165
5166 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
5167
5168 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5169 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
5170
5171 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5172
5173 {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
5174
5175 {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5176 {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5177
5178 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5179
5180 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5181
5182 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5183 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5184 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
5185 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5186
5187 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5188
5189 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5190
5191 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5192
5193 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5194
5195 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5196
5197 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5198 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5199
5200 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5201
5202 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5203 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5204 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5205 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5206 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5207 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5208 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5209 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5210 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5211 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5212 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5213 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5214 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5215 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5216 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5217 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5218 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5219 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5220 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5221 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5222 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5223 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5224 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5225 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5226 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5227 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5228 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5229 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5230 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5231 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5232 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5233 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5234 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5235 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5236 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5237 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5238
5239 {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5240
5241 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5242
5243 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5244 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5245
5246 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5247
5248 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5249 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5250
5251 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5252
5253 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5254 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5255 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5256 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5257 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5258 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5259 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5260 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5261 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5262 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5263 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5264 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5265 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5266 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5267 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5268 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5269 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5270 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5271 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5272 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5273 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5274 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5275 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5276 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5277 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5278 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5279 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5280 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5281 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5282 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5283 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5284 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5285 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5286 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5287 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5288 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5289 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5290 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5291 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5292 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5293 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5294 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5295 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5296 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5297 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5298 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5299 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5300 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5301 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5302 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5303 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5304 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5305 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5306 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5307 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5308 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5309 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5310 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5311 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5312 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5313 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5314 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5315 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5316 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5317 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5318 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5319 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5320 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5321 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5322 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5323 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5324 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5325 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5326 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5327 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5328 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5329 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5330 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5331 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5332 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5333 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5334 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5335 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5336 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5337 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5338 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5339 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5340 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5341 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5342 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5343 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5344 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5345 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5346 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5347 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5348 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5349 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5350 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5351 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5352 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5353 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5354 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5355 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5356 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5357 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5358 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5359 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5360 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5361 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5362 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5363 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5364 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5365 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5366 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5367 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5368 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5369 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5370 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5371 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5372 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5373 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5374 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5375 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5376 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5377 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5378 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5379 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5380 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5381 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5382 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5383 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5384 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5385 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5386 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5387 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5388 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5389 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5390 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5391 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5392 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5393 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5394 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5395 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5396 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5397 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5398 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5399 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5400 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5401 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5402 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5403 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5404 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5405 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5406 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5407 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5408 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5409 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5410 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5411 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5412 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5413 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5414 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5415 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5416 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5417 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5418 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5419 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5420 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5421 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5422 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5423 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5424 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5425 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5426 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5427 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5428 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5429 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5430 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5431 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5432 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5433 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5434 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5435 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5436 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5437 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5438 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5439 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5440 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5441 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5442 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5443 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5444 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5445 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5446 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5447 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5448 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5449 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5450 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5451 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5452 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5453 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5454
5455 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5456
5457 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5458
5459 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5460
5461 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5462
5463 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5464 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5465
5466 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5467 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5468
5469 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5470
5471 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5472
5473 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5474 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5475 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5476
5477 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5478
5479 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5480
5481 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5482
5483 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5484
5485 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5486 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5487
5488 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5489
5490 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5491 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5492
5493 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5494 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5495 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5496 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5497
5498 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5499 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5500
5501 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5502
5503 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5504
5505 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5506
5507 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5508
5509 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5510 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5511
5512 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5513
5514 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5515 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5516
5517 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5518
5519 {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5520
5521 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5522
5523 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5524
5525 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5526 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5527 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5528 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5529
5530 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5531
5532 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5533
5534 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5535
5536 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5537
5538 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5539
5540 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5541
5542 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
5543
5544 {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
5545
5546 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5547 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5548 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5549 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5550 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5551 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5552 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5553 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5554 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5555
5556 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5557 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5558 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5559 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5560 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5561 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5562 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5563 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5564 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5565 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5566 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5567 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5568 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5569 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5570 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5571 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5572 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5573 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5574 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5575 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5576 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5577 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5578 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5579 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5580 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5581 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5582 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5583 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5584 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5585 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5586 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5587 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5588 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5589 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5590 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5591 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5592
5593 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5594
5595 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5596 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5597
5598 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5599 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5600
5601 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5602 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5603
5604 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5605 {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5606
5607 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5608
5609 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5610 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5611 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5612 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5613 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5614 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5615 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5616 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5617 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5618 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5619 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5620 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5621 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5622 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5623 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5624 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5625 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5626 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5627 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5628 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5629 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5630 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5631 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5632 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5633 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5634 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5635 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5636 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5637 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5638 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5639 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5640 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5641 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5642 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5643 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5644 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5645 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5646 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5647 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5648 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5649 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5650 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5651 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5652 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5653 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5654 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5655 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5656 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5657 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5658 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5659 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5660 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5661 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5662 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5663 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5664 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5665 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5666 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5667 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5668 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5669 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5670 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5671 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5672 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5673 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5674 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5675 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5676 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5677 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5678 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5679 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5680 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5681 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5682 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5683 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5684 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5685 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5686 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5687 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5688 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5689 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5690 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5691 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5692 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5693 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5694 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5695 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5696 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5697 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5698 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5699 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5700 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5701 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5702 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5703 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5704 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5705 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5706 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5707 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5708 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5709 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5710 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5711 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5712 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5713 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5714 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5715 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5716 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5717 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5718 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5719 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5720 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5721 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5722 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5723 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5724 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5725 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5726 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5727 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5728 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5729 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5730 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5731 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5732 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5733 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5734 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5735 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5736 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5737 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5738 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5739 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5740 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5741 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5742 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5743 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5744 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5745 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5746 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5747 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5748 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5749 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5750 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5751 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5752 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5753 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5754 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5755 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5756 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5757 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5758 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5759 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5760 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5761 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5762 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5763 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5764 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5765 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5766 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5767 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5768 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5769 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5770 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5771 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5772 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5773 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5774
5775 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5776
5777 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5778 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5779
5780 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5781
5782 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5783
5784 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5785
5786 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5787
5788 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5789 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5790
5791 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5792 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5793
5794 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5795 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5796
5797 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5798
5799 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5800 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5801
5802 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5803
5804 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5805
5806 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5807
5808 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5809
5810 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
5811
5812 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
5813
5814 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5815 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5816
5817 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5818 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5819 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5820 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5821 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5822 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5823
5824 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5825 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5826 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5827 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5828
5829 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5830
5831 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
5832
5833 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
5834
5835 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5836 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5837
5838 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5839 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5840
5841 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5842
5843 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5844 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5845 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5846 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5847
5848 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5849 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
5850
5851 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5852 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
5853
5854 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5855 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5856
5857 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5858 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
5859
5860 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
5861
5862 {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5863
5864 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
5865
5866 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5867 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5868
5869 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5870 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5871 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5872 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5873
5874 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
5875
5876 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5877
5878 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5879 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
5880
5881 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
5882
5883 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
5884
5885 {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5886
5887 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
5888
5889 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5890
5891 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5892
5893 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
5894
5895 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5896 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
5897
5898 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
5899 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5900 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5901 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5902 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
5903 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5904 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5905 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5906 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
5907
5908 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5909
5910 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5911 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
5912
5913 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
5914
5915 {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5916
5917 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
5918
5919 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5920
5921 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5922 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
5923
5924 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5925 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
5926
5927 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
5928
5929 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
5930
5931 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5932
5933 {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
5934
5935 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5936 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5937
5938 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
5939
5940 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5941
5942 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5943 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5944 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5945 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5946
5947 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5948 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5949 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5950 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5951
5952 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5953
5954 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
5955
5956 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5957 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5958
5959 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5960 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5961
5962 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5963
5964 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5965 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
5966
5967 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5968 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
5969
5970 {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
5971
5972 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5973
5974 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5975 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5976
5977 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5978 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5979
5980 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5981
5982 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5983
5984 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5985 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
5986
5987 {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
5988
5989 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5990
5991 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
5992
5993 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5994
5995 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
5996
5997 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5998
5999 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6000 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6001 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6002 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6003
6004 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6005 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6006 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6007 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6008
6009 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
6010 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
6011
6012 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
6013
6014 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
6015
6016 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
6017 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
6018
6019 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
6020 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
6021
6022 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
6023 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
6024
6025 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
6026
6027 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6028
6029 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
6030
6031 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6032
6033 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6034 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6035 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6036 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6037
6038 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6039 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6040
6041 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6042 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6043 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6044 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6045
6046 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6047 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6048 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6049 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6050
6051 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6052 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6053 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
6054
6055 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
6056
6057 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6058 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
6059
6060 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6061
6062 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6063 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
6064
6065 {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6066
6067 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6068
6069 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6070 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6071 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6072
6073 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6074 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6075
6076 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6077 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6078 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6079 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6080
6081 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6082 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6083
6084 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6085 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6086
6087 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6088
6089 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6090
6091 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6092
6093 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6094
6095 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6096 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
6097
6098 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6099 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6100 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6101 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6102
6103 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6104 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6105
6106 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
6107
6108 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6109 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6110 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
6111
6112 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6113 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6114
6115 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6116
6117 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6118
6119 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
6120
6121 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6122
6123 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
6124
6125 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
6126
6127 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6128 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6129 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6130 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6131
6132 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6133 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6134
6135 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6136
6137 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
6138
6139 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6140 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6141
6142 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6143 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
6144
6145 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6146
6147 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
6148
6149 {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6150 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6151 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6152
6153 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6154
6155 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6156 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6157 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6158 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
6159
6160 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
6161
6162 {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6163
6164 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6165 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
6166
6167 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6168 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6169
6170 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6171
6172 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6173
6174 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
6175
6176 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6177
6178 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
6179
6180 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
6181
6182 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6183 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6184
6185 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6186
6187 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6188 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6189
6190 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6191 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6192 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6193 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6194
6195 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6196 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6197
6198 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6199
6200 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6201 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6202
6203 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6204 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6205
6206 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
6207
6208 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
6209
6210 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6211 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6212
6213 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6214 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
6215
6216 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6217 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
6218
6219 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6220 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6221 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6222 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
6223
6224 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
6225
6226 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6227
6228 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6229 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
6230 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
6231
6232 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6233
6234 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6235 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6236 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6237 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6238
6239 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6240 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6241
6242 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6243
6244 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6245 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6246 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6247
6248 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
6249
6250 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6251 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
6252
6253 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
6254
6255 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6256 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
6257
6258 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6259 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
6260
6261 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6262
6263 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6264 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
6265
6266 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6267 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6268
6269 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6270 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6271
6272 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6273 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
6274
6275 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6276 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6277 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6278 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6279
6280 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6281
6282 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
6283
6284 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
6285
6286 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
6287
6288 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6289 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
6290
6291 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6292
6293 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6294
6295 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
6296
6297 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6298 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
6299
6300 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6301 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6302
6303 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6304 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6305
6306 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6307
6308 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6309
6310 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
6311
6312 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
6313
6314 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6315 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6316
6317 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6318
6319 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
6320
6321 {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6322 {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6323 {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
6324
6325 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6326 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6327 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
6328
6329 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6330 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6331 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6332 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
6333
6334 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6335 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6336
6337 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6338 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6339
6340 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6341
6342 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6343
6344 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6345 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6346
6347 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6348 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6349
6350 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6351
6352 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6353
6354 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6355
6356 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6357
6358 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6359
6360 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6361
6362 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6363
6364 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6365
6366 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6367 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6368
6369 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6370 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6371
6372 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6373
6374 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6375
6376 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6377
6378 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6379
6380 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6381
6382 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6383
6384 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6385
6386 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6387
6388 {"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6389 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6390 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6391
6392 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6393 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6394 {"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6395 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6396 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6397
6398 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6399 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6400 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6401
6402 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6403 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6404
6405 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6406 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6407
6408 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6409 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6410
6411 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6412 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6413
6414 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6415 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6416
6417 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6418 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6419
6420 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6421 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6422 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6423 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6424
6425 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6426 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6427
6428 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6429 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6430 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6431 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6432
6433 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6434 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6435
6436 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6437 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6438
6439 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6440 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6441
6442 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6443 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6444
6445 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6446 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6447
6448 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6449 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6450
6451 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6452 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6453
6454 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6455 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6456
6457 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6458 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6459
6460 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6461 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6462
6463 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6464
6465 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6466 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6467 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6468
6469 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6470 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6471
6472 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6473 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6474
6475 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6476 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6477
6478 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6479 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6480
6481 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6482 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6483
6484 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6485 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6486
6487 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6488 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6489
6490 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6491
6492 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6493 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6494
6495 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6496 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6497
6498 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6499 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6500
6501 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6502 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6503
6504 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6505 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6506
6507 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6508 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6509
6510 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6511 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6512
6513 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6514 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6515 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6516 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6517 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6518 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6519 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6520 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6521 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6522 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6523 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6524 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6525 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6526 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6527 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6528 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6529 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6530 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6531 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6532 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6533 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6534 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6535 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6536 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6537 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6538 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6539 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6540 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6541 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6542 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6543 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6544 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6545 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6546 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6547 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6548 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6549 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6550 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6551 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6552 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6553 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6554 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6555 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6556 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6557 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6558 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6559 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6560 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6561 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6562 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6563 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6564 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6565 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6566 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6567 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6568 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6569 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6570 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6571 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6572 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6573 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6574 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6575 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6576 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6577 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6578 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6579 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6580 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6581 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6582 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6583 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6584 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6585 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6586 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6587 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6588 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6589 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6590 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6591 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6592 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6593 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6594 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6596 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6597 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6598 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6599 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6600 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6601 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6602 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6603 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6605 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6606 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6607 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6608 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6609 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6610 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6611 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6612 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6613 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6614 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6615 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6616 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6617 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6619 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6620 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6621 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6622 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6623 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6624 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6625 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6626 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6627 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6628 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6629 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6630 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6631 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6632 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6634 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6635 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6636 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6637 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6638 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6639 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6640 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6641 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6642 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6644 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6645 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6648 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6649 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6650 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6651 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6652 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6653 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6654 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6655 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6656 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6657 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6658 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6659 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6660 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6661 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6662 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6663 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6664 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6665 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6666 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6667 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6669 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6670 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6671 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6672 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6673 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6674 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6675 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6676 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6677 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6678 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6679 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6680 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6681 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6682 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6683 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6684 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6685 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6686 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6687 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6688 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6689 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6690 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6691 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6692 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6693 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6694 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6695 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6696 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6697 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6698 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6699 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6700 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6701 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6702 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6703 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6704 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6705 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6706 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6707 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6708 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6709 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6710 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6711
6712 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6713 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6714
6715 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6716 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6717 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6718 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6719 {"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6720 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6721 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6722
6723 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6724 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6725 {"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6726
6727 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6728
6729 {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6730 {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6731
6732 {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6733 {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6734
6735 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6736 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6737
6738 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6739 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6740
6741 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6742 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6743
6744 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6745 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6746
6747 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6748 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6749 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6750 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6751
6752 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6753 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6754 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6755 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6756
6757 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6758 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6759 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6760 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6761
6762 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6763 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6764 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6765 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6766
6767 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6768 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6769 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6770 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6771
6772 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6773 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6774
6775 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6776 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6777
6778 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6779 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6780 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6781 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6782
6783 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6784 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6785 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6786 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6787
6788 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6789 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6790 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6791 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6792
6793 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6794 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6795 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6796 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6797
6798 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6799 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6800 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6801 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6802
6803 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6804 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6805 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6806 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6807
6808 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6809 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6810 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6811 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6812
6813 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6814
6815 {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6816 {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6817
6818 {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6819 {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6820
6821 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6822 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6823
6824 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6825
6826 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6827 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
6828
6829 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6830 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6831
6832 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6833
6834 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6835 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6836
6837 {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6838 {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6839
6840 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6841 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
6842
6843 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6844 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6845
6846 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6847 {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6848
6849 {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6850 {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6851
6852 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6853
6854 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
6855
6856 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6857
6858 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6859
6860 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6861 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6862 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6863 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6864
6865 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6866 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6867
6868 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6869 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6870 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6871 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6872
6873 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
6874
6875 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6876
6877 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6878
6879 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6880 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
6881
6882 {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6883 {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6884
6885 {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6886 {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6887
6888 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6889 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6890
6891 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6892 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6893
6894 {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6895 {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6896
6897 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6898 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6899
6900 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6901 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6902
6903 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6904 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6905
6906 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6907 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6908
6909 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6910 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6911
6912 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6913 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6914
6915 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6916 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6917
6918 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6919 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6920
6921 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6922 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6923
6924 {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6925 {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6926
6927 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6928 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6929
6930 {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6931 {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6932
6933 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6934 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6935
6936 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6937 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6938
6939 {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6940 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6941 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6942 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6943 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6944 {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6945
6946 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6947
6948 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6949
6950 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6951 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
6952
6953 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
6954
6955 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6956 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6957 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6958 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6959
6960 {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6961 {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6962
6963 {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6964 {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6965
6966 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6967 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6968 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6969 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6970 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6971 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6972 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6973
6974 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6975 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6976 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6977 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6978
6979 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6980 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6981 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6982 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6983
6984 {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6985 {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6986
6987 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6988 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6989 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6990 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6991 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6992 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6993 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6994 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6995 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6996
6997 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6998
6999 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7000 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7001 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7002 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7003
7004 {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7005 {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7006
7007 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7008
7009 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7010 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7011
7012 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7013 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7014
7015 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
7016
7017 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7018 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7019 };
7020
7021 const int powerpc_num_opcodes =
7022 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
7023
7024 /* The VLE opcode table.
7025
7026 The format of this opcode table is the same as the main opcode table. */
7027
7028 const struct powerpc_opcode vle_opcodes[] = {
7029 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7030 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7031 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7032 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7033 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7034 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7035 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7036 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7037 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7038 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7039 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7040 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7041 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7042 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7043 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7044 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7045 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7046 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7047 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7048 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7049 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7050 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7051 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7052 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7053 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7054 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7055 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7056 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7057 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7058 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7059 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7060 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7061
7062 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7063 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7064 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7065 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7066 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7067 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7068 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7069 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7070 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7071 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7072 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7073 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7074 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7075 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7076 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7077 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7078 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7079 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7080 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7081 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7082 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7083 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7084 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7085 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7086 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7087 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7088 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7089 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7090 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7091 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7092 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7093
7094 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7095 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7096 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7097 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7098 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7099 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7100 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7101
7102 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7103 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7104 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7105
7106 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7107 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7108 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7109 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7110 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7111 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7112 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7113 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7114 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7115
7116 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7117 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7118 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7119 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7120
7121 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7122 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7123 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7124 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7125 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7126 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7127 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7128
7129 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7130 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7131 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7132 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7133 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7134 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7135 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7136 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7137 {"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7138 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7139 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7140 {"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7141 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7142 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7143 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7144 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7145 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7146 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7147 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7148 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7149 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7150 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7151 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7152 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7153 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7154 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7155 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7156 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7157 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7158 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7159 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7160 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7161 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7162 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7163 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7164 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7165 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7166 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7167 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7168 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7169 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7170 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7171 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7172 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7173 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7174 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7175 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7176 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7177 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7178 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7179 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7180
7181 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7182 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7183 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7184 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7185
7186 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7187 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7188 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7189 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7190 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7191 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7192 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7193 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7194 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7195 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7196 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7197
7198 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7199
7200 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7201 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7202
7203 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7204 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7205
7206 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7207 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7208
7209 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7210
7211 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7212 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7213
7214 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7215
7216 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7217 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7218
7219 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7220
7221 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7222
7223 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7224
7225 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7226
7227 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7228
7229 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7230
7231 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7232 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7233 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7234 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7235 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7236 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7237 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7238 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7239 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7240 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7241 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7242 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7243 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7244 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7245 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7246 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7247 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
7248 };
7249
7250 const int vle_num_opcodes =
7251 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7252
7253 /* The macro table. This is only used by the assembler. */
7254
7255 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7256 when x=0; 32-x when x is between 1 and 31; are negative if x is
7257 negative; and are 32 or more otherwise. This is what you want
7258 when, for instance, you are emulating a right shift by a
7259 rotate-left-and-mask, because the underlying instructions support
7260 shifts of size 0 but not shifts of size 32. By comparison, when
7261 extracting x bits from some word you want to use just 32-x, because
7262 the underlying instructions don't support extracting 0 bits but do
7263 support extracting the whole word (32 bits in this case). */
7264
7265 const struct powerpc_macro powerpc_macros[] = {
7266 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7267 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
7268 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7269 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7270 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7271 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7272 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7273 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7274 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7275 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7276 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7277 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7278 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7279 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7280 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
7281 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
7282
7283 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7284 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7285 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7286 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7287 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7288 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7289 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7290 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7291 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7292 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7293 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7294 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7295 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7296 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7297 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7298 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7299 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7300 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7301 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7302 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7303 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7304 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7305
7306 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7307 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7308 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7309 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7310 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7311 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7312 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7313 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7314 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7315 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7316 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7317 };
7318
7319 const int powerpc_num_macros =
7320 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
7321