1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 struct MachineSchedContext; 24 class MCAsmInfo; 25 class raw_ostream; 26 class ScheduleDAGInstrs; 27 class Target; 28 class TargetMachine; 29 30 // R600 Passes 31 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 32 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 33 FunctionPass *createR600EmitClauseMarkers(); 34 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 35 FunctionPass *createR600Packetizer(TargetMachine &tm); 36 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 37 FunctionPass *createAMDGPUCFGStructurizerPass(); 38 39 // SI Passes 40 FunctionPass *createSITypeRewriter(); 41 FunctionPass *createSIAnnotateControlFlowPass(); 42 FunctionPass *createSIFoldOperandsPass(); 43 FunctionPass *createSILowerI1CopiesPass(); 44 FunctionPass *createSIShrinkInstructionsPass(); 45 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 46 FunctionPass *createSIWholeQuadModePass(); 47 FunctionPass *createSILowerControlFlowPass(); 48 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 49 FunctionPass *createSIFixSGPRCopiesPass(); 50 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 51 FunctionPass *createSIDebuggerInsertNopsPass(); 52 FunctionPass *createSIInsertWaitsPass(); 53 FunctionPass *createAMDGPUCodeGenPreparePass(const TargetMachine *TM = nullptr); 54 55 ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C); 56 57 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 58 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 59 extern char &AMDGPUAnnotateKernelFeaturesID; 60 61 void initializeSIFoldOperandsPass(PassRegistry &); 62 extern char &SIFoldOperandsID; 63 64 void initializeSIShrinkInstructionsPass(PassRegistry&); 65 extern char &SIShrinkInstructionsID; 66 67 void initializeSIFixSGPRCopiesPass(PassRegistry &); 68 extern char &SIFixSGPRCopiesID; 69 70 void initializeSILowerI1CopiesPass(PassRegistry &); 71 extern char &SILowerI1CopiesID; 72 73 void initializeSILoadStoreOptimizerPass(PassRegistry &); 74 extern char &SILoadStoreOptimizerID; 75 76 void initializeSIWholeQuadModePass(PassRegistry &); 77 extern char &SIWholeQuadModeID; 78 79 void initializeSILowerControlFlowPass(PassRegistry &); 80 extern char &SILowerControlFlowPassID; 81 82 83 // Passes common to R600 and SI 84 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr); 85 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 86 extern char &AMDGPUPromoteAllocaID; 87 88 FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST); 89 Pass *createAMDGPUStructurizeCFGPass(); 90 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 91 ModulePass *createAMDGPUAlwaysInlinePass(); 92 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 93 FunctionPass *createAMDGPUAnnotateUniformValues(); 94 95 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 96 extern char &SIFixControlFlowLiveIntervalsID; 97 98 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 99 extern char &AMDGPUAnnotateUniformValuesPassID; 100 101 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 102 extern char &AMDGPUCodeGenPrepareID; 103 104 void initializeSIAnnotateControlFlowPass(PassRegistry&); 105 extern char &SIAnnotateControlFlowPassID; 106 107 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 108 extern char &SIDebuggerInsertNopsID; 109 110 void initializeSIInsertWaitsPass(PassRegistry&); 111 extern char &SIInsertWaitsID; 112 113 extern Target TheAMDGPUTarget; 114 extern Target TheGCNTarget; 115 116 namespace AMDGPU { 117 enum TargetIndex { 118 TI_CONSTDATA_START, 119 TI_SCRATCH_RSRC_DWORD0, 120 TI_SCRATCH_RSRC_DWORD1, 121 TI_SCRATCH_RSRC_DWORD2, 122 TI_SCRATCH_RSRC_DWORD3 123 }; 124 } 125 126 } // End namespace llvm 127 128 /// OpenCL uses address spaces to differentiate between 129 /// various memory regions on the hardware. On the CPU 130 /// all of the address spaces point to the same memory, 131 /// however on the GPU, each address space points to 132 /// a separate piece of memory that is unique from other 133 /// memory locations. 134 namespace AMDGPUAS { 135 enum AddressSpaces : unsigned { 136 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 137 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 138 CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2) 139 LOCAL_ADDRESS = 3, ///< Address space for local memory. 140 FLAT_ADDRESS = 4, ///< Address space for flat memory. 141 REGION_ADDRESS = 5, ///< Address space for region memory. 142 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 143 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 144 145 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 146 // order to be able to dynamically index a constant buffer, for example: 147 // 148 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 149 150 CONSTANT_BUFFER_0 = 8, 151 CONSTANT_BUFFER_1 = 9, 152 CONSTANT_BUFFER_2 = 10, 153 CONSTANT_BUFFER_3 = 11, 154 CONSTANT_BUFFER_4 = 12, 155 CONSTANT_BUFFER_5 = 13, 156 CONSTANT_BUFFER_6 = 14, 157 CONSTANT_BUFFER_7 = 15, 158 CONSTANT_BUFFER_8 = 16, 159 CONSTANT_BUFFER_9 = 17, 160 CONSTANT_BUFFER_10 = 18, 161 CONSTANT_BUFFER_11 = 19, 162 CONSTANT_BUFFER_12 = 20, 163 CONSTANT_BUFFER_13 = 21, 164 CONSTANT_BUFFER_14 = 22, 165 CONSTANT_BUFFER_15 = 23, 166 167 // Some places use this if the address space can't be determined. 168 UNKNOWN_ADDRESS_SPACE = ~0u 169 }; 170 171 } // namespace AMDGPUAS 172 173 #endif 174