1 /* v850.h -- Header file for NEC V850 opcode table
2    Copyright (C) 1996-2016 Free Software Foundation, Inc.
3    Written by J.T. Conklin, Cygnus Support
4 
5    This file is part of GDB, GAS, and the GNU binutils.
6 
7    GDB, GAS, and the GNU binutils are free software; you can redistribute
8    them and/or modify them under the terms of the GNU General Public
9    License as published by the Free Software Foundation; either version 3,
10    or (at your option) any later version.
11 
12    GDB, GAS, and the GNU binutils are distributed in the hope that they
13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
15    the GNU General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with this file; see the file COPYING3.  If not, write to the Free
19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20    MA 02110-1301, USA.  */
21 
22 #ifndef V850_H
23 #define V850_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 /* The opcode table is an array of struct v850_opcode.  */
30 
31 struct v850_opcode
32 {
33   /* The opcode name.  */
34   const char *name;
35 
36   /* The opcode itself.  Those bits which will be filled in with
37      operands are zeroes.  */
38   unsigned long opcode;
39 
40   /* The opcode mask.  This is used by the disassembler.  This is a
41      mask containing ones indicating those bits which must match the
42      opcode field, and zeroes indicating those bits which need not
43      match (and are presumably filled in by operands).  */
44   unsigned long mask;
45 
46   /* An array of operand codes.  Each code is an index into the
47      operand table.  They appear in the order which the operands must
48      appear in assembly code, and are terminated by a zero.  */
49   unsigned char operands[8];
50 
51   /* Which (if any) operand is a memory operand.  */
52   unsigned int memop;
53 
54   /* Target processor(s).  A bit field of processors which support
55      this instruction.  Note a bit field is used as some instructions
56      are available on multiple, different processor types, whereas
57      other instructions are only available on one specific type.  */
58   unsigned int processors;
59 };
60 
61 /* Values for architecture number.  */
62 #define arch_V850      0
63 #define arch_V850E     (arch_V850 + 1)
64 #define arch_V850E1    (arch_V850E + 1)
65 #define arch_V850E2    (arch_V850E1 + 1)
66 #define arch_V850E2V3  (arch_V850E2 + 1)
67 #define arch_V850E3V5  (arch_V850E2V3 + 1)
68 #define arch_separator (arch_V850E3V5 + 1)
69 
70 #define opt_EXTENSION  (arch_separator)
71 #define opt_ALIAS      (opt_EXTENSION + 1)
72 
73 /* Values for the processors field in the v850_opcode structure.  */
74 #define PROCESSOR_V850       (1 << (arch_V850))     /* Just the V850.  */
75 #define PROCESSOR_V850E      (1 << (arch_V850E))    /* Just the V850E.  */
76 #define PROCESSOR_V850E1     (1 << (arch_V850E1))   /* Just the V850E1.  */
77 #define PROCESSOR_V850E2     (1 << (arch_V850E2))   /* Just the V850E2.  */
78 #define PROCESSOR_V850E2V3   (1 << (arch_V850E2V3)) /* Just the V850E2V3.  */
79 #define PROCESSOR_V850E3V5   (1 << (arch_V850E3V5)) /* Just the V850E3V5.  */
80 
81 /* UPPERS */
82 #define PROCESSOR_V850E3V5_UP (PROCESSOR_V850E3V5)
83 #define PROCESSOR_V850E2V3_UP (PROCESSOR_V850E2V3 | PROCESSOR_V850E3V5_UP)
84 #define PROCESSOR_V850E2_UP   (PROCESSOR_V850E2   | PROCESSOR_V850E2V3_UP)
85 #define PROCESSOR_V850E_UP    (PROCESSOR_V850E    | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
86 #define PROCESSOR_ALL         (PROCESSOR_V850     | PROCESSOR_V850E_UP)
87 
88 #define PROCESSOR_MASK        (PROCESSOR_ALL)
89 #define PROCESSOR_NOT_V850    (PROCESSOR_ALL & (~ PROCESSOR_V850))         /* Any processor except the V850.  */
90 
91 #define PROCESSOR_UNKNOWN    ~(PROCESSOR_MASK)
92 
93 /* OPTIONS */
94 #define PROCESSOR_OPTION_EXTENSION (1 << (opt_EXTENSION))                  /* Enable extension opcodes.  */
95 #define PROCESSOR_OPTION_ALIAS     (1 << (opt_ALIAS))                      /* Enable alias opcodes.  */
96 
97 #define SET_PROCESSOR_MASK(mask,set)	((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
98 
99 /* The table itself is sorted by major opcode number, and is otherwise
100    in the order in which the disassembler should consider
101    instructions.  */
102 extern const struct v850_opcode v850_opcodes[];
103 extern const int v850_num_opcodes;
104 
105 
106 /* The operands table is an array of struct v850_operand.  */
107 
108 struct v850_operand
109 {
110   /* The number of bits in the operand.  */
111   /* If this value is -1 then the operand's bits are in a discontinous
112      distribution in the instruction. */
113   int bits;
114 
115   /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
116   /* (bits == -1): Bit mask of the bits in the operand.  */
117   int shift;
118 
119   /* Insertion function.  This is used by the assembler.  To insert an
120      operand value into an instruction, check this field.
121 
122      If it is NULL, execute
123          i |= (op & ((1 << o->bits) - 1)) << o->shift;
124      (i is the instruction which we are filling in, o is a pointer to
125      this structure, and op is the opcode value; this assumes twos
126      complement arithmetic).
127 
128      If this field is not NULL, then simply call it with the
129      instruction and the operand value.  It will return the new value
130      of the instruction.  If the ERRMSG argument is not NULL, then if
131      the operand value is illegal, *ERRMSG will be set to a warning
132      string (the operand will be inserted in any case).  If the
133      operand value is legal, *ERRMSG will be unchanged (most operands
134      can accept any value).  */
135   unsigned long (* insert)
136     (unsigned long instruction, long op, const char ** errmsg);
137 
138   /* Extraction function.  This is used by the disassembler.  To
139      extract this operand type from an instruction, check this field.
140 
141      If it is NULL, compute
142          op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
143 	 if (o->flags & V850_OPERAND_SIGNED)
144 	     op = (op << (32 - o->bits)) >> (32 - o->bits);
145      (i is the instruction, o is a pointer to this structure, and op
146      is the result; this assumes twos complement arithmetic).
147 
148      If this field is not NULL, then simply call it with the
149      instruction value.  It will return the value of the operand.  If
150      the INVALID argument is not NULL, *INVALID will be set to
151      non-zero if this operand type can not actually be extracted from
152      this operand (i.e., the instruction does not match).  If the
153      operand is valid, *INVALID will not be changed.  */
154   unsigned long (* extract) (unsigned long instruction, int * invalid);
155 
156   /* One bit syntax flags.  */
157   int flags;
158 
159   int default_reloc;
160 };
161 
162 /* Elements in the table are retrieved by indexing with values from
163    the operands field of the v850_opcodes table.  */
164 
165 extern const struct v850_operand v850_operands[];
166 
167 /* Values defined for the flags field of a struct v850_operand.  */
168 
169 /* This operand names a general purpose register.  */
170 #define V850_OPERAND_REG	0x01
171 
172 /* This operand is the ep register.  */
173 #define V850_OPERAND_EP		0x02
174 
175 /* This operand names a system register.  */
176 #define V850_OPERAND_SRG	0x04
177 
178 /* Prologue eilogue type instruction, V850E specific.  */
179 #define V850E_OPERAND_REG_LIST	0x08
180 
181 /* This operand names a condition code used in the setf instruction.  */
182 #define V850_OPERAND_CC		0x10
183 
184 #define V850_OPERAND_FLOAT_CC	0x20
185 
186 /* This operand names a vector purpose register.  */
187 #define V850_OPERAND_VREG	0x40
188 
189 /* 16 bit immediate follows instruction, V850E specific.  */
190 #define V850E_IMMEDIATE16	0x80
191 
192 /* hi16 bit immediate follows instruction, V850E specific.  */
193 #define V850E_IMMEDIATE16HI	0x100
194 
195 /* 23 bit immediate follows instruction, V850E specific.  */
196 #define V850E_IMMEDIATE23	0x200
197 
198 /* 32 bit immediate follows instruction, V850E specific.  */
199 #define V850E_IMMEDIATE32	0x400
200 
201 /* This is a relaxable operand.   Only used for D9->D22 branch relaxing
202    right now.  We may need others in the future (or maybe handle them like
203    promoted operands on the mn10300?).  */
204 #define V850_OPERAND_RELAX	0x800
205 
206 /* This operand takes signed values.  */
207 #define V850_OPERAND_SIGNED	0x1000
208 
209 /* This operand is a displacement.  */
210 #define V850_OPERAND_DISP	0x2000
211 
212 /* This operand is a PC displacement.  */
213 #define V850_PCREL		0x4000
214 
215 /* The register specified must be even number.  */
216 #define V850_REG_EVEN		0x8000
217 
218 /* The register specified must not be r0.  */
219 #define V850_NOT_R0	        0x20000
220 
221 /* The register specified must not be 0.  */
222 #define V850_NOT_IMM0	        0x40000
223 
224 /* The condition code must not be SA CONDITION.  */
225 #define V850_NOT_SA		0x80000
226 
227 /* The operand has '!' prefix.  */
228 #define V850_OPERAND_BANG	0x100000
229 
230 /* The operand has '%' prefix.  */
231 #define V850_OPERAND_PERCENT	0x200000
232 
233 /* This operand is a cache oparation.  */
234 #define V850_OPERAND_CACHEOP	0x400000
235 
236 /* This operand is a prefetch oparation.  */
237 #define V850_OPERAND_PREFOP	0x800000
238 
239 /* A PC-relative displacement where a positive value indicates a backwards displacement.  */
240 #define V850_INVERSE_PCREL	0x1000000
241 
242 extern int v850_msg_is_out_of_range (const char *);
243 
244 #ifdef __cplusplus
245 }
246 #endif
247 
248 #endif /* V850_H */
249