1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "subsegs.h"
24 #include "opcode/d10v.h"
25 #include "elf/ppc.h"
26 #include "dwarf2dbg.h"
27
28 const char comment_chars[] = ";";
29 const char line_comment_chars[] = "#";
30 const char line_separator_chars[] = "";
31 const char *md_shortopts = "O";
32 const char EXP_CHARS[] = "eE";
33 const char FLT_CHARS[] = "dD";
34
35 int Optimizing = 0;
36
37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
38 && (X)->X_op_symbol != NULL \
39 && symbol_constant_p ((X)->X_op_symbol) \
40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
41 #define AT_WORD_RIGHT_SHIFT 2
42
43 /* Fixups. */
44 #define MAX_INSN_FIXUPS 5
45
46 struct d10v_fixup
47 {
48 expressionS exp;
49 int operand;
50 int pcrel;
51 int size;
52 bfd_reloc_code_real_type reloc;
53 };
54
55 typedef struct _fixups
56 {
57 int fc;
58 struct d10v_fixup fix[MAX_INSN_FIXUPS];
59 struct _fixups *next;
60 } Fixups;
61
62 static Fixups FixUps[2];
63 static Fixups *fixups;
64
65 static int do_not_ignore_hash = 0;
66
67 typedef int packing_type;
68 #define PACK_UNSPEC (0) /* Packing order not specified. */
69 #define PACK_PARALLEL (1) /* "||" */
70 #define PACK_LEFT_RIGHT (2) /* "->" */
71 #define PACK_RIGHT_LEFT (3) /* "<-" */
72 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
73
74 /* TRUE if instruction swapping warnings should be inhibited.
75 --nowarnswap. */
76 static bfd_boolean flag_warn_suppress_instructionswap;
77
78 /* TRUE if instruction packing should be performed when --gstabs is specified.
79 --gstabs-packing, --no-gstabs-packing. */
80 static bfd_boolean flag_allow_gstabs_packing = 1;
81
82 /* Local functions. */
83
84 enum options
85 {
86 OPTION_NOWARNSWAP = OPTION_MD_BASE,
87 OPTION_GSTABSPACKING,
88 OPTION_NOGSTABSPACKING
89 };
90
91 struct option md_longopts[] =
92 {
93 {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
94 {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING},
95 {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
96 {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING},
97 {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
98 {NULL, no_argument, NULL, 0}
99 };
100
101 size_t md_longopts_size = sizeof (md_longopts);
102
103 /* Opcode hash table. */
104 static struct hash_control *d10v_hash;
105
106 /* Do a binary search of the d10v_predefined_registers array to see if
107 NAME is a valid regiter name. Return the register number from the
108 array on success, or -1 on failure. */
109
110 static int
reg_name_search(char * name)111 reg_name_search (char *name)
112 {
113 int middle, low, high;
114 int cmp;
115
116 low = 0;
117 high = d10v_reg_name_cnt () - 1;
118
119 do
120 {
121 middle = (low + high) / 2;
122 cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
123 if (cmp < 0)
124 high = middle - 1;
125 else if (cmp > 0)
126 low = middle + 1;
127 else
128 return d10v_predefined_registers[middle].value;
129 }
130 while (low <= high);
131 return -1;
132 }
133
134 /* Check the string at input_line_pointer
135 to see if it is a valid register name. */
136
137 static int
register_name(expressionS * expressionP)138 register_name (expressionS *expressionP)
139 {
140 int reg_number;
141 char c, *p = input_line_pointer;
142
143 while (*p
144 && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
145 p++;
146
147 c = *p;
148 if (c)
149 *p++ = 0;
150
151 /* Look to see if it's in the register table. */
152 reg_number = reg_name_search (input_line_pointer);
153 if (reg_number >= 0)
154 {
155 expressionP->X_op = O_register;
156 /* Temporarily store a pointer to the string here. */
157 expressionP->X_op_symbol = (symbolS *) input_line_pointer;
158 expressionP->X_add_number = reg_number;
159 input_line_pointer = p;
160 return 1;
161 }
162 if (c)
163 *(p - 1) = c;
164 return 0;
165 }
166
167 static int
check_range(unsigned long num,int bits,int flags)168 check_range (unsigned long num, int bits, int flags)
169 {
170 long min, max;
171 int retval = 0;
172
173 /* Don't bother checking 16-bit values. */
174 if (bits == 16)
175 return 0;
176
177 if (flags & OPERAND_SHIFT)
178 {
179 /* All special shift operands are unsigned and <= 16.
180 We allow 0 for now. */
181 if (num > 16)
182 return 1;
183 else
184 return 0;
185 }
186
187 if (flags & OPERAND_SIGNED)
188 {
189 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
190 if (flags & RESTRICTED_NUM3)
191 {
192 if ((long) num < -2 || (long) num > 3)
193 retval = 1;
194 }
195 else
196 {
197 max = (1 << (bits - 1)) - 1;
198 min = - (1 << (bits - 1));
199 if (((long) num > max) || ((long) num < min))
200 retval = 1;
201 }
202 }
203 else
204 {
205 max = (1 << bits) - 1;
206 min = 0;
207 if (((long) num > max) || ((long) num < min))
208 retval = 1;
209 }
210 return retval;
211 }
212
213 void
md_show_usage(FILE * stream)214 md_show_usage (FILE *stream)
215 {
216 fprintf (stream, _("D10V options:\n\
217 -O Optimize. Will do some operations in parallel.\n\
218 --gstabs-packing Pack adjacent short instructions together even\n\
219 when --gstabs is specified. On by default.\n\
220 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
221 instructions together.\n"));
222 }
223
224 int
md_parse_option(int c,const char * arg ATTRIBUTE_UNUSED)225 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
226 {
227 switch (c)
228 {
229 case 'O':
230 /* Optimize. Will attempt to parallelize operations. */
231 Optimizing = 1;
232 break;
233 case OPTION_NOWARNSWAP:
234 flag_warn_suppress_instructionswap = 1;
235 break;
236 case OPTION_GSTABSPACKING:
237 flag_allow_gstabs_packing = 1;
238 break;
239 case OPTION_NOGSTABSPACKING:
240 flag_allow_gstabs_packing = 0;
241 break;
242 default:
243 return 0;
244 }
245 return 1;
246 }
247
248 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)249 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
250 {
251 return 0;
252 }
253
254 const char *
md_atof(int type,char * litP,int * sizeP)255 md_atof (int type, char *litP, int *sizeP)
256 {
257 return ieee_md_atof (type, litP, sizeP, TRUE);
258 }
259
260 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,asection * sec ATTRIBUTE_UNUSED,fragS * fragP ATTRIBUTE_UNUSED)261 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
262 asection *sec ATTRIBUTE_UNUSED,
263 fragS *fragP ATTRIBUTE_UNUSED)
264 {
265 abort ();
266 }
267
268 valueT
md_section_align(asection * seg,valueT addr)269 md_section_align (asection *seg, valueT addr)
270 {
271 int align = bfd_get_section_alignment (stdoutput, seg);
272 return ((addr + (1 << align) - 1) & -(1 << align));
273 }
274
275 void
md_begin(void)276 md_begin (void)
277 {
278 const char *prev_name = "";
279 struct d10v_opcode *opcode;
280 d10v_hash = hash_new ();
281
282 /* Insert unique names into hash table. The D10v instruction set
283 has many identical opcode names that have different opcodes based
284 on the operands. This hash table then provides a quick index to
285 the first opcode with a particular name in the opcode table. */
286
287 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
288 {
289 if (strcmp (prev_name, opcode->name))
290 {
291 prev_name = (char *) opcode->name;
292 hash_insert (d10v_hash, opcode->name, (char *) opcode);
293 }
294 }
295
296 fixups = &FixUps[0];
297 FixUps[0].next = &FixUps[1];
298 FixUps[1].next = &FixUps[0];
299 }
300
301 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
302 from an expression. */
303
304 static int
postfix(char * p)305 postfix (char *p)
306 {
307 while (*p != '-' && *p != '+')
308 {
309 if (*p == 0 || *p == '\n' || *p == '\r')
310 break;
311 p++;
312 }
313
314 if (*p == '-')
315 {
316 *p = ' ';
317 return -1;
318 }
319 if (*p == '+')
320 {
321 *p = ' ';
322 return 1;
323 }
324
325 return 0;
326 }
327
328 static bfd_reloc_code_real_type
get_reloc(struct d10v_operand * op)329 get_reloc (struct d10v_operand *op)
330 {
331 int bits = op->bits;
332
333 if (bits <= 4)
334 return 0;
335
336 if (op->flags & OPERAND_ADDR)
337 {
338 if (bits == 8)
339 return BFD_RELOC_D10V_10_PCREL_R;
340 else
341 return BFD_RELOC_D10V_18_PCREL;
342 }
343
344 return BFD_RELOC_16;
345 }
346
347 /* Parse a string of operands. Return an array of expressions. */
348
349 static int
get_operands(expressionS exp[])350 get_operands (expressionS exp[])
351 {
352 char *p = input_line_pointer;
353 int numops = 0;
354 int post = 0;
355 int uses_at = 0;
356
357 while (*p)
358 {
359 while (*p == ' ' || *p == '\t' || *p == ',')
360 p++;
361 if (*p == 0 || *p == '\n' || *p == '\r')
362 break;
363
364 if (*p == '@')
365 {
366 uses_at = 1;
367
368 p++;
369 exp[numops].X_op = O_absent;
370 if (*p == '(')
371 {
372 p++;
373 exp[numops].X_add_number = OPERAND_ATPAR;
374 }
375 else if (*p == '-')
376 {
377 p++;
378 exp[numops].X_add_number = OPERAND_ATMINUS;
379 }
380 else
381 {
382 exp[numops].X_add_number = OPERAND_ATSIGN;
383 if (*p == '+')
384 {
385 numops++;
386 exp[numops].X_op = O_absent;
387 exp[numops].X_add_number = OPERAND_PLUS;
388 p++;
389 }
390 post = postfix (p);
391 }
392 numops++;
393 continue;
394 }
395
396 if (*p == ')')
397 {
398 /* Just skip the trailing paren. */
399 p++;
400 continue;
401 }
402
403 input_line_pointer = p;
404
405 /* Check to see if it might be a register name. */
406 if (!register_name (&exp[numops]))
407 {
408 /* Parse as an expression. */
409 if (uses_at)
410 {
411 /* Any expression that involves the indirect addressing
412 cannot also involve immediate addressing. Therefore
413 the use of the hash character is illegal. */
414 int save = do_not_ignore_hash;
415 do_not_ignore_hash = 1;
416
417 expression (&exp[numops]);
418
419 do_not_ignore_hash = save;
420 }
421 else
422 expression (&exp[numops]);
423 }
424
425 if (strncasecmp (input_line_pointer, "@word", 5) == 0)
426 {
427 input_line_pointer += 5;
428 if (exp[numops].X_op == O_register)
429 {
430 /* If it looked like a register name but was followed by
431 "@word" then it was really a symbol, so change it to
432 one. */
433 exp[numops].X_op = O_symbol;
434 exp[numops].X_add_symbol =
435 symbol_find_or_make ((char *) exp[numops].X_op_symbol);
436 }
437
438 /* Check for identifier@word+constant. */
439 if (*input_line_pointer == '-' || *input_line_pointer == '+')
440 {
441 expressionS new_exp;
442 expression (&new_exp);
443 exp[numops].X_add_number = new_exp.X_add_number;
444 }
445
446 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
447 {
448 expressionS new_exp;
449 memset (&new_exp, 0, sizeof new_exp);
450 new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
451 new_exp.X_op = O_constant;
452 new_exp.X_unsigned = 1;
453 exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
454 exp[numops].X_op = O_right_shift;
455 }
456
457 know (AT_WORD_P (&exp[numops]));
458 }
459
460 if (exp[numops].X_op == O_illegal)
461 as_bad (_("illegal operand"));
462 else if (exp[numops].X_op == O_absent)
463 as_bad (_("missing operand"));
464
465 numops++;
466 p = input_line_pointer;
467 }
468
469 switch (post)
470 {
471 case -1: /* Postdecrement mode. */
472 exp[numops].X_op = O_absent;
473 exp[numops++].X_add_number = OPERAND_MINUS;
474 break;
475 case 1: /* Postincrement mode. */
476 exp[numops].X_op = O_absent;
477 exp[numops++].X_add_number = OPERAND_PLUS;
478 break;
479 }
480
481 exp[numops].X_op = 0;
482 return numops;
483 }
484
485 static unsigned long
d10v_insert_operand(unsigned long insn,int op_type,offsetT value,int left,fixS * fix)486 d10v_insert_operand (unsigned long insn,
487 int op_type,
488 offsetT value,
489 int left,
490 fixS *fix)
491 {
492 int shift, bits;
493
494 shift = d10v_operands[op_type].shift;
495 if (left)
496 shift += 15;
497
498 bits = d10v_operands[op_type].bits;
499
500 /* Truncate to the proper number of bits. */
501 if (check_range (value, bits, d10v_operands[op_type].flags))
502 as_bad_where (fix->fx_file, fix->fx_line,
503 _("operand out of range: %ld"), (long) value);
504
505 value &= 0x7FFFFFFF >> (31 - bits);
506 insn |= (value << shift);
507
508 return insn;
509 }
510
511 /* Take a pointer to the opcode entry in the opcode table and the
512 array of operand expressions. Return the instruction. */
513
514 static unsigned long
build_insn(struct d10v_opcode * opcode,expressionS * opers,unsigned long insn)515 build_insn (struct d10v_opcode *opcode,
516 expressionS *opers,
517 unsigned long insn)
518 {
519 int i, bits, shift, flags, format;
520 unsigned long number;
521
522 /* The insn argument is only used for the DIVS kludge. */
523 if (insn)
524 format = LONG_R;
525 else
526 {
527 insn = opcode->opcode;
528 format = opcode->format;
529 }
530
531 for (i = 0; opcode->operands[i]; i++)
532 {
533 flags = d10v_operands[opcode->operands[i]].flags;
534 bits = d10v_operands[opcode->operands[i]].bits;
535 shift = d10v_operands[opcode->operands[i]].shift;
536 number = opers[i].X_add_number;
537
538 if (flags & OPERAND_REG)
539 {
540 number &= REGISTER_MASK;
541 if (format == LONG_L)
542 shift += 15;
543 }
544
545 if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
546 {
547 /* Now create a fixup. */
548
549 if (fixups->fc >= MAX_INSN_FIXUPS)
550 as_fatal (_("too many fixups"));
551
552 if (AT_WORD_P (&opers[i]))
553 {
554 /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
555 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
556 opers[i].X_op = O_symbol;
557 opers[i].X_op_symbol = NULL; /* Should free it. */
558 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
559 that, it is aligned with the symbol's value. Later,
560 BFD_RELOC_D10V_18 will right shift (symbol_value +
561 X_add_number). */
562 number <<= AT_WORD_RIGHT_SHIFT;
563 opers[i].X_add_number = number;
564 }
565 else
566 {
567 fixups->fix[fixups->fc].reloc =
568 get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
569
570 /* Check that an immediate was passed to ops that expect one. */
571 if ((flags & OPERAND_NUM)
572 && (fixups->fix[fixups->fc].reloc == 0))
573 as_bad (_("operand is not an immediate"));
574 }
575
576 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
577 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
578 fixups->fix[fixups->fc].size = 2;
579 else
580 fixups->fix[fixups->fc].size = 4;
581
582 fixups->fix[fixups->fc].exp = opers[i];
583 fixups->fix[fixups->fc].operand = opcode->operands[i];
584 fixups->fix[fixups->fc].pcrel =
585 (flags & OPERAND_ADDR) ? TRUE : FALSE;
586 (fixups->fc)++;
587 }
588
589 /* Truncate to the proper number of bits. */
590 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
591 as_bad (_("operand out of range: %lu"), number);
592 number &= 0x7FFFFFFF >> (31 - bits);
593 insn = insn | (number << shift);
594 }
595
596 /* kludge: for DIVS, we need to put the operands in twice on the second
597 pass, format is changed to LONG_R to force the second set of operands
598 to not be shifted over 15. */
599 if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
600 insn = build_insn (opcode, opers, insn);
601
602 return insn;
603 }
604
605 /* Write out a long form instruction. */
606
607 static void
write_long(unsigned long insn,Fixups * fx)608 write_long (unsigned long insn, Fixups *fx)
609 {
610 int i, where;
611 char *f = frag_more (4);
612
613 dwarf2_emit_insn (4);
614 insn |= FM11;
615 number_to_chars_bigendian (f, insn, 4);
616
617 for (i = 0; i < fx->fc; i++)
618 {
619 if (fx->fix[i].reloc)
620 {
621 where = f - frag_now->fr_literal;
622 if (fx->fix[i].size == 2)
623 where += 2;
624
625 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
626 fx->fix[i].operand |= 4096;
627
628 fix_new_exp (frag_now,
629 where,
630 fx->fix[i].size,
631 &(fx->fix[i].exp),
632 fx->fix[i].pcrel,
633 fx->fix[i].operand|2048);
634 }
635 }
636 fx->fc = 0;
637 }
638
639 /* Write out a short form instruction by itself. */
640
641 static void
write_1_short(struct d10v_opcode * opcode,unsigned long insn,Fixups * fx)642 write_1_short (struct d10v_opcode *opcode,
643 unsigned long insn,
644 Fixups *fx)
645 {
646 char *f = frag_more (4);
647 int i, where;
648
649 dwarf2_emit_insn (4);
650 if (opcode->exec_type & PARONLY)
651 as_fatal (_("Instruction must be executed in parallel with another instruction."));
652
653 /* The other container needs to be NOP.
654 According to 4.3.1: for FM=00, sub-instructions performed only by IU
655 cannot be encoded in L-container. */
656 if (opcode->unit == IU)
657 insn |= FM00 | (NOP << 15); /* Right container. */
658 else
659 insn = FM00 | (insn << 15) | NOP; /* Left container. */
660
661 number_to_chars_bigendian (f, insn, 4);
662 for (i = 0; i < fx->fc; i++)
663 {
664 if (fx->fix[i].reloc)
665 {
666 where = f - frag_now->fr_literal;
667 if (fx->fix[i].size == 2)
668 where += 2;
669
670 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
671 fx->fix[i].operand |= 4096;
672
673 /* If it's an R reloc, we may have to switch it to L. */
674 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
675 && (opcode->unit != IU))
676 fx->fix[i].operand |= 1024;
677
678 fix_new_exp (frag_now,
679 where,
680 fx->fix[i].size,
681 &(fx->fix[i].exp),
682 fx->fix[i].pcrel,
683 fx->fix[i].operand|2048);
684 }
685 }
686 fx->fc = 0;
687 }
688
689 /* Determine if there are any resource conflicts among two manually
690 parallelized instructions. Some of this was lifted from parallel_ok. */
691
692 static void
check_resource_conflict(struct d10v_opcode * op1,unsigned long insn1,struct d10v_opcode * op2,unsigned long insn2)693 check_resource_conflict (struct d10v_opcode *op1,
694 unsigned long insn1,
695 struct d10v_opcode *op2,
696 unsigned long insn2)
697 {
698 int i, j, flags, mask, shift, regno;
699 unsigned long ins, mod[2];
700 struct d10v_opcode *op;
701
702 if ((op1->exec_type & SEQ)
703 || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
704 {
705 as_warn (_("packing conflict: %s must dispatch sequentially"),
706 op1->name);
707 return;
708 }
709
710 if ((op2->exec_type & SEQ)
711 || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
712 {
713 as_warn (_("packing conflict: %s must dispatch sequentially"),
714 op2->name);
715 return;
716 }
717
718 /* See if both instructions write to the same resource.
719
720 The idea here is to create two sets of bitmasks (mod and used) which
721 indicate which registers are modified or used by each instruction.
722 The operation can only be done in parallel if neither instruction
723 modifies the same register. Accesses to control registers and memory
724 are treated as accesses to a single register. So if both instructions
725 write memory or if the first instruction writes memory and the second
726 reads, then they cannot be done in parallel. We treat reads to the PSW
727 (which includes C, F0, and F1) in isolation. So simultaneously writing
728 C and F0 in two different sub-instructions is permitted. */
729
730 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
731 r0-r15 0-15
732 a0-a1 16-17
733 cr (not psw) 18
734 psw(other) 19
735 mem 20
736 psw(C flag) 21
737 psw(F0 flag) 22 */
738
739 for (j = 0; j < 2; j++)
740 {
741 if (j == 0)
742 {
743 op = op1;
744 ins = insn1;
745 }
746 else
747 {
748 op = op2;
749 ins = insn2;
750 }
751 mod[j] = 0;
752 if (op->exec_type & BRANCH_LINK)
753 mod[j] |= 1 << 13;
754
755 for (i = 0; op->operands[i]; i++)
756 {
757 flags = d10v_operands[op->operands[i]].flags;
758 shift = d10v_operands[op->operands[i]].shift;
759 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
760 if (flags & OPERAND_REG)
761 {
762 regno = (ins >> shift) & mask;
763 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
764 regno += 16;
765 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
766 {
767 if (regno == 0)
768 regno = 19;
769 else
770 regno = 18;
771 }
772 else if (flags & OPERAND_FFLAG)
773 regno = 22;
774 else if (flags & OPERAND_CFLAG)
775 regno = 21;
776
777 if (flags & OPERAND_DEST
778 /* Auto inc/dec also modifies the register. */
779 || (op->operands[i + 1] != 0
780 && (d10v_operands[op->operands[i + 1]].flags
781 & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
782 {
783 mod[j] |= 1 << regno;
784 if (flags & OPERAND_EVEN)
785 mod[j] |= 1 << (regno + 1);
786 }
787 }
788 else if (flags & OPERAND_ATMINUS)
789 {
790 /* SP implicitly used/modified. */
791 mod[j] |= 1 << 15;
792 }
793 }
794
795 if (op->exec_type & WMEM)
796 mod[j] |= 1 << 20;
797 else if (op->exec_type & WF0)
798 mod[j] |= 1 << 22;
799 else if (op->exec_type & WCAR)
800 mod[j] |= 1 << 21;
801 }
802
803 if ((mod[0] & mod[1]) == 0)
804 return;
805 else
806 {
807 unsigned long x;
808 x = mod[0] & mod[1];
809
810 for (j = 0; j <= 15; j++)
811 if (x & (1 << j))
812 as_warn (_("resource conflict (R%d)"), j);
813 for (j = 16; j <= 17; j++)
814 if (x & (1 << j))
815 as_warn (_("resource conflict (A%d)"), j - 16);
816 if (x & (1 << 19))
817 as_warn (_("resource conflict (PSW)"));
818 if (x & (1 << 21))
819 as_warn (_("resource conflict (C flag)"));
820 if (x & (1 << 22))
821 as_warn (_("resource conflict (F flag)"));
822 }
823 }
824
825 /* Check 2 instructions and determine if they can be safely
826 executed in parallel. Return 1 if they can be. */
827
828 static int
parallel_ok(struct d10v_opcode * op1,unsigned long insn1,struct d10v_opcode * op2,unsigned long insn2,packing_type exec_type)829 parallel_ok (struct d10v_opcode *op1,
830 unsigned long insn1,
831 struct d10v_opcode *op2,
832 unsigned long insn2,
833 packing_type exec_type)
834 {
835 int i, j, flags, mask, shift, regno;
836 unsigned long ins, mod[2], used[2];
837 struct d10v_opcode *op;
838
839 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
840 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
841 || (op1->unit == BOTH) || (op2->unit == BOTH)
842 || (op1->unit == IU && op2->unit == IU)
843 || (op1->unit == MU && op2->unit == MU))
844 return 0;
845
846 /* If this is auto parallelization, and the first instruction is a
847 branch or should not be packed, then don't parallelize. */
848 if (exec_type == PACK_UNSPEC
849 && (op1->exec_type & (ALONE | BRANCH)))
850 return 0;
851
852 /* The idea here is to create two sets of bitmasks (mod and used)
853 which indicate which registers are modified or used by each
854 instruction. The operation can only be done in parallel if
855 instruction 1 and instruction 2 modify different registers, and
856 the first instruction does not modify registers that the second
857 is using (The second instruction can modify registers that the
858 first is using as they are only written back after the first
859 instruction has completed). Accesses to control registers, PSW,
860 and memory are treated as accesses to a single register. So if
861 both instructions write memory or if the first instruction writes
862 memory and the second reads, then they cannot be done in
863 parallel. Likewise, if the first instruction mucks with the psw
864 and the second reads the PSW (which includes C, F0, and F1), then
865 they cannot operate safely in parallel. */
866
867 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
868 r0-r15 0-15
869 a0-a1 16-17
870 cr (not psw) 18
871 psw 19
872 mem 20 */
873
874 for (j = 0; j < 2; j++)
875 {
876 if (j == 0)
877 {
878 op = op1;
879 ins = insn1;
880 }
881 else
882 {
883 op = op2;
884 ins = insn2;
885 }
886 mod[j] = used[j] = 0;
887 if (op->exec_type & BRANCH_LINK)
888 mod[j] |= 1 << 13;
889
890 for (i = 0; op->operands[i]; i++)
891 {
892 flags = d10v_operands[op->operands[i]].flags;
893 shift = d10v_operands[op->operands[i]].shift;
894 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
895 if (flags & OPERAND_REG)
896 {
897 regno = (ins >> shift) & mask;
898 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
899 regno += 16;
900 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
901 {
902 if (regno == 0)
903 regno = 19;
904 else
905 regno = 18;
906 }
907 else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
908 regno = 19;
909
910 if (flags & OPERAND_DEST)
911 {
912 mod[j] |= 1 << regno;
913 if (flags & OPERAND_EVEN)
914 mod[j] |= 1 << (regno + 1);
915 }
916 else
917 {
918 used[j] |= 1 << regno;
919 if (flags & OPERAND_EVEN)
920 used[j] |= 1 << (regno + 1);
921
922 /* Auto inc/dec also modifies the register. */
923 if (op->operands[i + 1] != 0
924 && (d10v_operands[op->operands[i + 1]].flags
925 & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
926 mod[j] |= 1 << regno;
927 }
928 }
929 else if (flags & OPERAND_ATMINUS)
930 {
931 /* SP implicitly used/modified. */
932 mod[j] |= 1 << 15;
933 used[j] |= 1 << 15;
934 }
935 }
936 if (op->exec_type & RMEM)
937 used[j] |= 1 << 20;
938 else if (op->exec_type & WMEM)
939 mod[j] |= 1 << 20;
940 else if (op->exec_type & RF0)
941 used[j] |= 1 << 19;
942 else if (op->exec_type & WF0)
943 mod[j] |= 1 << 19;
944 else if (op->exec_type & WCAR)
945 mod[j] |= 1 << 19;
946 }
947 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
948 return 1;
949 return 0;
950 }
951
952 /* Expects two short instructions.
953 If possible, writes out both as a single packed instruction.
954 Otherwise, writes out the first one, packed with a NOP.
955 Returns number of instructions not written out. */
956
957 static int
write_2_short(struct d10v_opcode * opcode1,unsigned long insn1,struct d10v_opcode * opcode2,unsigned long insn2,packing_type exec_type,Fixups * fx)958 write_2_short (struct d10v_opcode *opcode1,
959 unsigned long insn1,
960 struct d10v_opcode *opcode2,
961 unsigned long insn2,
962 packing_type exec_type,
963 Fixups *fx)
964 {
965 unsigned long insn;
966 char *f;
967 int i, j, where;
968
969 if ((exec_type != PACK_PARALLEL)
970 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
971 as_fatal (_("Instruction must be executed in parallel"));
972
973 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
974 as_fatal (_("Long instructions may not be combined."));
975
976 switch (exec_type)
977 {
978 case PACK_UNSPEC: /* Order not specified. */
979 if (opcode1->exec_type & ALONE)
980 {
981 /* Case of a short branch on a separate GAS line. Pack with NOP. */
982 write_1_short (opcode1, insn1, fx->next);
983 return 1;
984 }
985 if (Optimizing
986 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
987 {
988 /* Parallel. */
989 if (opcode1->unit == IU)
990 insn = FM00 | (insn2 << 15) | insn1;
991 else if (opcode2->unit == MU)
992 insn = FM00 | (insn2 << 15) | insn1;
993 else
994 insn = FM00 | (insn1 << 15) | insn2;
995 }
996 else if (opcode1->unit == IU)
997 /* Reverse sequential with IU opcode1 on right and done first. */
998 insn = FM10 | (insn2 << 15) | insn1;
999 else
1000 /* Sequential with non-IU opcode1 on left and done first. */
1001 insn = FM01 | (insn1 << 15) | insn2;
1002 break;
1003
1004 case PACK_PARALLEL:
1005 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
1006 as_fatal
1007 (_("One of these instructions may not be executed in parallel."));
1008 if (opcode1->unit == IU)
1009 {
1010 if (opcode2->unit == IU)
1011 as_fatal (_("Two IU instructions may not be executed in parallel"));
1012 if (!flag_warn_suppress_instructionswap)
1013 as_warn (_("Swapping instruction order"));
1014 insn = FM00 | (insn2 << 15) | insn1;
1015 }
1016 else if (opcode2->unit == MU)
1017 {
1018 if (opcode1->unit == MU)
1019 as_fatal (_("Two MU instructions may not be executed in parallel"));
1020 if (!flag_warn_suppress_instructionswap)
1021 as_warn (_("Swapping instruction order"));
1022 insn = FM00 | (insn2 << 15) | insn1;
1023 }
1024 else
1025 insn = FM00 | (insn1 << 15) | insn2;
1026 check_resource_conflict (opcode1, insn1, opcode2, insn2);
1027 break;
1028
1029 case PACK_LEFT_RIGHT:
1030 if (opcode1->unit != IU)
1031 insn = FM01 | (insn1 << 15) | insn2;
1032 else if (opcode2->unit == MU || opcode2->unit == EITHER)
1033 {
1034 if (!flag_warn_suppress_instructionswap)
1035 as_warn (_("Swapping instruction order"));
1036 insn = FM10 | (insn2 << 15) | insn1;
1037 }
1038 else
1039 as_fatal (_("IU instruction may not be in the left container"));
1040 if (opcode1->exec_type & ALONE)
1041 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1042 break;
1043
1044 case PACK_RIGHT_LEFT:
1045 if (opcode2->unit != MU)
1046 insn = FM10 | (insn1 << 15) | insn2;
1047 else if (opcode1->unit == IU || opcode1->unit == EITHER)
1048 {
1049 if (!flag_warn_suppress_instructionswap)
1050 as_warn (_("Swapping instruction order"));
1051 insn = FM01 | (insn2 << 15) | insn1;
1052 }
1053 else
1054 as_fatal (_("MU instruction may not be in the right container"));
1055 if (opcode2->exec_type & ALONE)
1056 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1057 break;
1058
1059 default:
1060 as_fatal (_("unknown execution type passed to write_2_short()"));
1061 }
1062
1063 f = frag_more (4);
1064 dwarf2_emit_insn (4);
1065 number_to_chars_bigendian (f, insn, 4);
1066
1067 /* Process fixup chains. fx refers to insn2 when j == 0, and to
1068 insn1 when j == 1. Yes, it's reversed. */
1069
1070 for (j = 0; j < 2; j++)
1071 {
1072 for (i = 0; i < fx->fc; i++)
1073 {
1074 if (fx->fix[i].reloc)
1075 {
1076 where = f - frag_now->fr_literal;
1077 if (fx->fix[i].size == 2)
1078 where += 2;
1079
1080 if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
1081 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
1082 the instruction in the L container has to be
1083 adjusted to BDF_RELOC_D10V_10_PCREL_L. When
1084 j==0, we're processing insn2's operands, so we
1085 want to mark the operand if insn2 is *not* in the
1086 R container. When j==1, we're processing insn1's
1087 operands, so we want to mark the operand if insn2
1088 *is* in the R container. Note that, if two
1089 instructions are identical, we're never going to
1090 swap them, so the test is safe. */
1091 && j == ((insn & 0x7fff) == insn2))
1092 fx->fix[i].operand |= 1024;
1093
1094 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
1095 fx->fix[i].operand |= 4096;
1096
1097 fix_new_exp (frag_now,
1098 where,
1099 fx->fix[i].size,
1100 &(fx->fix[i].exp),
1101 fx->fix[i].pcrel,
1102 fx->fix[i].operand|2048);
1103 }
1104 }
1105 fx->fc = 0;
1106 fx = fx->next;
1107 }
1108 return 0;
1109 }
1110
1111 /* This is the main entry point for the machine-dependent assembler.
1112 str points to a machine-dependent instruction. This function is
1113 supposed to emit the frags/bytes it assembles to. For the D10V, it
1114 mostly handles the special VLIW parsing and packing and leaves the
1115 difficult stuff to do_assemble(). */
1116
1117 static unsigned long prev_insn;
1118 static struct d10v_opcode *prev_opcode = 0;
1119 static subsegT prev_subseg;
1120 static segT prev_seg = 0;
1121
1122 /* Find the symbol which has the same name as the register in exp. */
1123
1124 static symbolS *
find_symbol_matching_register(expressionS * exp)1125 find_symbol_matching_register (expressionS *exp)
1126 {
1127 int i;
1128
1129 if (exp->X_op != O_register)
1130 return NULL;
1131
1132 /* Find the name of the register. */
1133 for (i = d10v_reg_name_cnt (); i--;)
1134 if (d10v_predefined_registers[i].value == exp->X_add_number)
1135 break;
1136
1137 if (i < 0)
1138 abort ();
1139
1140 /* Now see if a symbol has been defined with the same name. */
1141 return symbol_find (d10v_predefined_registers[i].name);
1142 }
1143
1144 /* Get a pointer to an entry in the opcode table.
1145 The function must look at all opcodes with the same name and use
1146 the operands to choose the correct opcode. */
1147
1148 static struct d10v_opcode *
find_opcode(struct d10v_opcode * opcode,expressionS myops[])1149 find_opcode (struct d10v_opcode *opcode, expressionS myops[])
1150 {
1151 int i, match;
1152 struct d10v_opcode *next_opcode;
1153
1154 /* Get all the operands and save them as expressions. */
1155 get_operands (myops);
1156
1157 /* Now see if the operand is a fake. If so, find the correct size
1158 instruction, if possible. */
1159 if (opcode->format == OPCODE_FAKE)
1160 {
1161 int opnum = opcode->operands[0];
1162 int flags;
1163
1164 if (myops[opnum].X_op == O_register)
1165 {
1166 myops[opnum].X_op = O_symbol;
1167 myops[opnum].X_add_symbol =
1168 symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
1169 myops[opnum].X_add_number = 0;
1170 myops[opnum].X_op_symbol = NULL;
1171 }
1172
1173 next_opcode = opcode + 1;
1174
1175 /* If the first operand is supposed to be a register, make sure
1176 we got a valid one. */
1177 flags = d10v_operands[next_opcode->operands[0]].flags;
1178 if (flags & OPERAND_REG)
1179 {
1180 int X_op = myops[0].X_op;
1181 int num = myops[0].X_add_number;
1182
1183 if (X_op != O_register
1184 || (num & ~flags
1185 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1186 | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))
1187 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1188 {
1189 as_bad (_("bad opcode or operands"));
1190 return 0;
1191 }
1192 }
1193
1194 if (myops[opnum].X_op == O_constant
1195 || (myops[opnum].X_op == O_symbol
1196 && S_IS_DEFINED (myops[opnum].X_add_symbol)
1197 && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
1198 {
1199 for (i = 0; opcode->operands[i + 1]; i++)
1200 {
1201 int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1202
1203 flags = d10v_operands[next_opcode->operands[opnum]].flags;
1204
1205 if (flags & OPERAND_ADDR)
1206 bits += 2;
1207
1208 if (myops[opnum].X_op == O_constant)
1209 {
1210 if (!check_range (myops[opnum].X_add_number, bits, flags))
1211 break;
1212 }
1213 else
1214 {
1215 fragS *sym_frag;
1216 fragS *f;
1217 unsigned long current_position;
1218 unsigned long symbol_position;
1219 unsigned long value;
1220 bfd_boolean found_symbol;
1221
1222 /* Calculate the address of the current instruction
1223 and the address of the symbol. Do this by summing
1224 the offsets of previous frags until we reach the
1225 frag containing the symbol, and the current frag. */
1226 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
1227 found_symbol = FALSE;
1228
1229 current_position = frag_now_fix_octets ();
1230 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
1231
1232 for (f = frchain_now->frch_root; f; f = f->fr_next)
1233 {
1234 current_position += f->fr_fix + f->fr_offset;
1235
1236 if (f == sym_frag)
1237 found_symbol = TRUE;
1238
1239 if (! found_symbol)
1240 symbol_position += f->fr_fix + f->fr_offset;
1241 }
1242
1243 value = symbol_position;
1244
1245 if (flags & OPERAND_ADDR)
1246 value -= current_position;
1247
1248 if (AT_WORD_P (&myops[opnum]))
1249 {
1250 if (bits > 4)
1251 {
1252 bits += 2;
1253 if (!check_range (value, bits, flags))
1254 break;
1255 }
1256 }
1257 else if (!check_range (value, bits, flags))
1258 break;
1259 }
1260 next_opcode++;
1261 }
1262
1263 if (opcode->operands [i + 1] == 0)
1264 as_fatal (_("value out of range"));
1265 else
1266 opcode = next_opcode;
1267 }
1268 else
1269 /* Not a constant, so use a long instruction. */
1270 opcode += 2;
1271 }
1272
1273 match = 0;
1274
1275 /* Now search the opcode table table for one with operands
1276 that matches what we've got. */
1277 while (!match)
1278 {
1279 match = 1;
1280 for (i = 0; opcode->operands[i]; i++)
1281 {
1282 int flags = d10v_operands[opcode->operands[i]].flags;
1283 int X_op = myops[i].X_op;
1284 int num = myops[i].X_add_number;
1285
1286 if (X_op == 0)
1287 {
1288 match = 0;
1289 break;
1290 }
1291
1292 if (flags & OPERAND_REG)
1293 {
1294 if ((X_op != O_register)
1295 || (num & ~flags
1296 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1297 | OPERAND_FFLAG | OPERAND_CFLAG
1298 | OPERAND_CONTROL))
1299 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1300 {
1301 match = 0;
1302 break;
1303 }
1304 }
1305
1306 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1307 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1308 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1309 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1310 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR)))))
1311 {
1312 match = 0;
1313 break;
1314 }
1315
1316 /* Unfortunately, for the indirect operand in instructions such
1317 as ``ldb r1, @(c,r14)'' this function can be passed
1318 X_op == O_register (because 'c' is a valid register name).
1319 However we cannot just ignore the case when X_op == O_register
1320 but flags & OPERAND_REG is null, so we check to see if a symbol
1321 of the same name as the register exists. If the symbol does
1322 exist, then the parser was unable to distinguish the two cases
1323 and we fix things here. (Ref: PR14826) */
1324
1325 if (!(flags & OPERAND_REG) && (X_op == O_register))
1326 {
1327 symbolS * sym;
1328
1329 sym = find_symbol_matching_register (& myops[i]);
1330
1331 if (sym != NULL)
1332 {
1333 myops[i].X_op = X_op = O_symbol;
1334 myops[i].X_add_symbol = sym;
1335 }
1336 else
1337 as_bad
1338 (_("illegal operand - register name found where none expected"));
1339 }
1340 }
1341
1342 /* We're only done if the operands matched so far AND there
1343 are no more to check. */
1344 if (match && myops[i].X_op == 0)
1345 break;
1346 else
1347 match = 0;
1348
1349 next_opcode = opcode + 1;
1350
1351 if (next_opcode->opcode == 0)
1352 break;
1353
1354 if (strcmp (next_opcode->name, opcode->name))
1355 break;
1356
1357 opcode = next_opcode;
1358 }
1359
1360 if (!match)
1361 {
1362 as_bad (_("bad opcode or operands"));
1363 return 0;
1364 }
1365
1366 /* Check that all registers that are required to be even are.
1367 Also, if any operands were marked as registers, but were really symbols,
1368 fix that here. */
1369 for (i = 0; opcode->operands[i]; i++)
1370 {
1371 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1372 (myops[i].X_add_number & 1))
1373 as_fatal (_("Register number must be EVEN"));
1374 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP)
1375 && (myops[i].X_add_number & OPERAND_SP))
1376 as_bad (_("Unsupported use of sp"));
1377 if (myops[i].X_op == O_register)
1378 {
1379 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1380 {
1381 myops[i].X_op = O_symbol;
1382 myops[i].X_add_symbol =
1383 symbol_find_or_make ((char *) myops[i].X_op_symbol);
1384 myops[i].X_add_number = 0;
1385 myops[i].X_op_symbol = NULL;
1386 }
1387 }
1388 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL)
1389 && (myops[i].X_add_number == OPERAND_CONTROL + 4
1390 || myops[i].X_add_number == OPERAND_CONTROL + 5
1391 || myops[i].X_add_number == OPERAND_CONTROL + 6
1392 || myops[i].X_add_number == OPERAND_CONTROL + 12
1393 || myops[i].X_add_number == OPERAND_CONTROL + 13
1394 || myops[i].X_add_number == OPERAND_CONTROL + 15))
1395 as_warn (_("cr%ld is a reserved control register"),
1396 myops[i].X_add_number - OPERAND_CONTROL);
1397 }
1398 return opcode;
1399 }
1400
1401 /* Assemble a single instruction.
1402 Return an opcode, or -1 (an invalid opcode) on error. */
1403
1404 static unsigned long
do_assemble(char * str,struct d10v_opcode ** opcode)1405 do_assemble (char *str, struct d10v_opcode **opcode)
1406 {
1407 unsigned char *op_start, *op_end;
1408 char *save;
1409 char name[20];
1410 int nlen = 0;
1411 expressionS myops[6];
1412
1413 /* Drop leading whitespace. */
1414 while (*str == ' ')
1415 str++;
1416
1417 /* Find the opcode end. */
1418 for (op_start = op_end = (unsigned char *) str;
1419 *op_end && !is_end_of_line[*op_end] && *op_end != ' ';
1420 op_end++)
1421 {
1422 name[nlen] = TOLOWER (op_start[nlen]);
1423 nlen++;
1424 if (nlen == sizeof (name) - 1)
1425 break;
1426 }
1427 name[nlen] = 0;
1428
1429 if (nlen == 0)
1430 return -1;
1431
1432 /* Find the first opcode with the proper name. */
1433 *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
1434 if (*opcode == NULL)
1435 return -1;
1436
1437 save = input_line_pointer;
1438 input_line_pointer = (char *) op_end;
1439 *opcode = find_opcode (*opcode, myops);
1440 if (*opcode == 0)
1441 return -1;
1442 input_line_pointer = save;
1443
1444 return build_insn ((*opcode), myops, 0);
1445 }
1446
1447 /* If while processing a fixup, a reloc really needs to be created.
1448 Then it is done here. */
1449
1450 arelent *
tc_gen_reloc(asection * seg ATTRIBUTE_UNUSED,fixS * fixp)1451 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1452 {
1453 arelent *reloc;
1454 reloc = XNEW (arelent);
1455 reloc->sym_ptr_ptr = XNEW (asymbol *);
1456 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1457 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1458 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1459 if (reloc->howto == (reloc_howto_type *) NULL)
1460 {
1461 as_bad_where (fixp->fx_file, fixp->fx_line,
1462 _("reloc %d not supported by object file format"),
1463 (int) fixp->fx_r_type);
1464 return NULL;
1465 }
1466
1467 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1468 reloc->address = fixp->fx_offset;
1469
1470 reloc->addend = 0;
1471
1472 return reloc;
1473 }
1474
1475 int
md_estimate_size_before_relax(fragS * fragp ATTRIBUTE_UNUSED,asection * seg ATTRIBUTE_UNUSED)1476 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1477 asection *seg ATTRIBUTE_UNUSED)
1478 {
1479 abort ();
1480 return 0;
1481 }
1482
1483 long
md_pcrel_from_section(fixS * fixp,segT sec)1484 md_pcrel_from_section (fixS *fixp, segT sec)
1485 {
1486 if (fixp->fx_addsy != (symbolS *) NULL
1487 && (!S_IS_DEFINED (fixp->fx_addsy)
1488 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1489 return 0;
1490 return fixp->fx_frag->fr_address + fixp->fx_where;
1491 }
1492
1493 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg ATTRIBUTE_UNUSED)1494 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1495 {
1496 char *where;
1497 unsigned long insn;
1498 long value = *valP;
1499 int op_type;
1500 int left = 0;
1501
1502 if (fixP->fx_addsy == (symbolS *) NULL)
1503 fixP->fx_done = 1;
1504
1505 /* We don't actually support subtracting a symbol. */
1506 if (fixP->fx_subsy != (symbolS *) NULL)
1507 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1508
1509 op_type = fixP->fx_r_type;
1510 if (op_type & 2048)
1511 {
1512 op_type -= 2048;
1513 if (op_type & 1024)
1514 {
1515 op_type -= 1024;
1516 fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1517 left = 1;
1518 }
1519 else if (op_type & 4096)
1520 {
1521 op_type -= 4096;
1522 fixP->fx_r_type = BFD_RELOC_D10V_18;
1523 }
1524 else
1525 fixP->fx_r_type =
1526 get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
1527 }
1528
1529 /* Fetch the instruction, insert the fully resolved operand
1530 value, and stuff the instruction back again. */
1531 where = fixP->fx_frag->fr_literal + fixP->fx_where;
1532 insn = bfd_getb32 ((unsigned char *) where);
1533
1534 switch (fixP->fx_r_type)
1535 {
1536 case BFD_RELOC_D10V_10_PCREL_L:
1537 case BFD_RELOC_D10V_10_PCREL_R:
1538 case BFD_RELOC_D10V_18_PCREL:
1539 /* If the fix is relative to a global symbol, not a section
1540 symbol, then ignore the offset.
1541 XXX - Do we have to worry about branches to a symbol + offset ? */
1542 if (fixP->fx_addsy != NULL
1543 && S_IS_EXTERNAL (fixP->fx_addsy) )
1544 {
1545 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
1546 segment_info_type *segf = seg_info(fseg);
1547
1548 if ( segf && segf->sym != fixP->fx_addsy)
1549 value = 0;
1550 }
1551 /* Drop through. */
1552 case BFD_RELOC_D10V_18:
1553 /* Instruction addresses are always right-shifted by 2. */
1554 value >>= AT_WORD_RIGHT_SHIFT;
1555 if (fixP->fx_size == 2)
1556 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1557 else
1558 {
1559 struct d10v_opcode *rep, *repi;
1560
1561 rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
1562 repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
1563 if ((insn & FM11) == FM11
1564 && ((repi != NULL
1565 && (insn & repi->mask) == (unsigned) repi->opcode)
1566 || (rep != NULL
1567 && (insn & rep->mask) == (unsigned) rep->opcode))
1568 && value < 4)
1569 as_fatal
1570 (_("line %d: rep or repi must include at least 4 instructions"),
1571 fixP->fx_line);
1572 insn =
1573 d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP);
1574 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1575 }
1576 break;
1577 case BFD_RELOC_32:
1578 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1579 break;
1580 case BFD_RELOC_16:
1581 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1582 break;
1583
1584 case BFD_RELOC_VTABLE_INHERIT:
1585 case BFD_RELOC_VTABLE_ENTRY:
1586 fixP->fx_done = 0;
1587 return;
1588
1589 default:
1590 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1591 fixP->fx_line, fixP->fx_r_type);
1592 }
1593 }
1594
1595 /* d10v_cleanup() is called after the assembler has finished parsing
1596 the input file, when a label is read from the input file, or when a
1597 stab directive is output. Because the D10V assembler sometimes
1598 saves short instructions to see if it can package them with the
1599 next instruction, there may be a short instruction that still needs
1600 to be written.
1601
1602 NOTE: accesses a global, etype.
1603 NOTE: invoked by various macros such as md_cleanup: see. */
1604
1605 int
d10v_cleanup(void)1606 d10v_cleanup (void)
1607 {
1608 segT seg;
1609 subsegT subseg;
1610
1611 /* If cleanup was invoked because the assembler encountered, e.g., a
1612 user label, we write out the pending instruction, if any. If it
1613 was invoked because the assembler is outputting a piece of line
1614 debugging information, though, we write out the pending
1615 instruction only if the --no-gstabs-packing command line switch
1616 has been specified. */
1617 if (prev_opcode
1618 && etype == PACK_UNSPEC
1619 && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
1620 {
1621 seg = now_seg;
1622 subseg = now_subseg;
1623
1624 if (prev_seg)
1625 subseg_set (prev_seg, prev_subseg);
1626
1627 write_1_short (prev_opcode, prev_insn, fixups->next);
1628 subseg_set (seg, subseg);
1629 prev_opcode = NULL;
1630 }
1631 return 1;
1632 }
1633
1634 void
d10v_frob_label(symbolS * lab)1635 d10v_frob_label (symbolS *lab)
1636 {
1637 d10v_cleanup ();
1638 symbol_set_frag (lab, frag_now);
1639 S_SET_VALUE (lab, (valueT) frag_now_fix ());
1640 dwarf2_emit_label (lab);
1641 }
1642
1643 /* Like normal .word, except support @word.
1644 Clobbers input_line_pointer, checks end-of-line. */
1645
1646 static void
d10v_dot_word(int dummy ATTRIBUTE_UNUSED)1647 d10v_dot_word (int dummy ATTRIBUTE_UNUSED)
1648 {
1649 expressionS exp;
1650 char *p;
1651
1652 if (is_it_end_of_statement ())
1653 {
1654 demand_empty_rest_of_line ();
1655 return;
1656 }
1657
1658 do
1659 {
1660 expression (&exp);
1661 if (!strncasecmp (input_line_pointer, "@word", 5))
1662 {
1663 exp.X_add_number = 0;
1664 input_line_pointer += 5;
1665
1666 p = frag_more (2);
1667 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1668 &exp, 0, BFD_RELOC_D10V_18);
1669 }
1670 else
1671 emit_expr (&exp, 2);
1672 }
1673 while (*input_line_pointer++ == ',');
1674
1675 input_line_pointer--; /* Put terminator back into stream. */
1676 demand_empty_rest_of_line ();
1677 }
1678
1679 /* Mitsubishi asked that we support some old syntax that apparently
1680 had immediate operands starting with '#'. This is in some of their
1681 sample code but is not documented (although it appears in some
1682 examples in their assembler manual). For now, we'll solve this
1683 compatibility problem by simply ignoring any '#' at the beginning
1684 of an operand. */
1685
1686 /* Operands that begin with '#' should fall through to here.
1687 From expr.c. */
1688
1689 void
md_operand(expressionS * expressionP)1690 md_operand (expressionS *expressionP)
1691 {
1692 if (*input_line_pointer == '#' && ! do_not_ignore_hash)
1693 {
1694 input_line_pointer++;
1695 expression (expressionP);
1696 }
1697 }
1698
1699 bfd_boolean
d10v_fix_adjustable(fixS * fixP)1700 d10v_fix_adjustable (fixS *fixP)
1701 {
1702 /* We need the symbol name for the VTABLE entries. */
1703 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1704 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1705 return 0;
1706
1707 return 1;
1708 }
1709
1710 /* The target specific pseudo-ops which we support. */
1711 const pseudo_typeS md_pseudo_table[] =
1712 {
1713 { "word", d10v_dot_word, 2 },
1714 { NULL, NULL, 0 }
1715 };
1716
1717 void
md_assemble(char * str)1718 md_assemble (char *str)
1719 {
1720 /* etype is saved extype. For multi-line instructions. */
1721 packing_type extype = PACK_UNSPEC; /* Parallel, etc. */
1722 struct d10v_opcode *opcode;
1723 unsigned long insn;
1724 char *str2;
1725
1726 if (etype == PACK_UNSPEC)
1727 {
1728 /* Look for the special multiple instruction separators. */
1729 str2 = strstr (str, "||");
1730 if (str2)
1731 extype = PACK_PARALLEL;
1732 else
1733 {
1734 str2 = strstr (str, "->");
1735 if (str2)
1736 extype = PACK_LEFT_RIGHT;
1737 else
1738 {
1739 str2 = strstr (str, "<-");
1740 if (str2)
1741 extype = PACK_RIGHT_LEFT;
1742 }
1743 }
1744
1745 /* str2 points to the separator, if there is one. */
1746 if (str2)
1747 {
1748 *str2 = 0;
1749
1750 /* If two instructions are present and we already have one saved,
1751 then first write out the saved one. */
1752 d10v_cleanup ();
1753
1754 /* Assemble first instruction and save it. */
1755 prev_insn = do_assemble (str, &prev_opcode);
1756 prev_seg = now_seg;
1757 prev_subseg = now_subseg;
1758 if (prev_insn == (unsigned long) -1)
1759 as_fatal (_("can't find previous opcode "));
1760 fixups = fixups->next;
1761 str = str2 + 2;
1762 }
1763 }
1764
1765 insn = do_assemble (str, &opcode);
1766 if (insn == (unsigned long) -1)
1767 {
1768 if (extype != PACK_UNSPEC)
1769 etype = extype;
1770 else
1771 as_bad (_("could not assemble: %s"), str);
1772 return;
1773 }
1774
1775 if (etype != PACK_UNSPEC)
1776 {
1777 extype = etype;
1778 etype = PACK_UNSPEC;
1779 }
1780
1781 /* If this is a long instruction, write it and any previous short
1782 instruction. */
1783 if (opcode->format & LONG_OPCODE)
1784 {
1785 if (extype != PACK_UNSPEC)
1786 as_fatal (_("Unable to mix instructions as specified"));
1787 d10v_cleanup ();
1788 write_long (insn, fixups);
1789 prev_opcode = NULL;
1790 return;
1791 }
1792
1793 if (prev_opcode
1794 && prev_seg
1795 && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1796 d10v_cleanup ();
1797
1798 if (prev_opcode
1799 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
1800 fixups)))
1801 {
1802 /* No instructions saved. */
1803 prev_opcode = NULL;
1804 }
1805 else
1806 {
1807 if (extype != PACK_UNSPEC)
1808 as_fatal (_("Unable to mix instructions as specified"));
1809 /* Save last instruction so it may be packed on next pass. */
1810 prev_opcode = opcode;
1811 prev_insn = insn;
1812 prev_seg = now_seg;
1813 prev_subseg = now_subseg;
1814 fixups = fixups->next;
1815 }
1816 }
1817
1818