1 /*
2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
26 * of the Software.
27 */
28 /*
29 * Authors:
30 * Marek Olšák <maraeo@gmail.com>
31 */
32
33 #ifndef AMDGPU_BO_H
34 #define AMDGPU_BO_H
35
36 #include "amdgpu_winsys.h"
37
38 #include "pipebuffer/pb_slab.h"
39
40 struct amdgpu_winsys_bo {
41 struct pb_buffer base;
42 union {
43 struct {
44 struct pb_cache_entry cache_entry;
45
46 amdgpu_va_handle va_handle;
47 int map_count;
48 bool use_reusable_pool;
49
50 struct list_head global_list_item;
51 } real;
52 struct {
53 struct pb_slab_entry entry;
54 struct amdgpu_winsys_bo *real;
55 } slab;
56 } u;
57
58 struct amdgpu_winsys *ws;
59 void *user_ptr; /* from buffer_from_ptr */
60
61 amdgpu_bo_handle bo; /* NULL for slab entries */
62 uint32_t unique_id;
63 uint64_t va;
64 enum radeon_bo_domain initial_domain;
65
66 /* how many command streams is this bo referenced in? */
67 int num_cs_references;
68
69 /* how many command streams, which are being emitted in a separate
70 * thread, is this bo referenced in? */
71 volatile int num_active_ioctls;
72
73 /* whether buffer_get_handle or buffer_from_handle was called,
74 * it can only transition from false to true
75 */
76 volatile int is_shared; /* bool (int for atomicity) */
77
78 /* Fences for buffer synchronization. */
79 unsigned num_fences;
80 unsigned max_fences;
81 struct pipe_fence_handle **fences;
82 };
83
84 struct amdgpu_slab {
85 struct pb_slab base;
86 struct amdgpu_winsys_bo *buffer;
87 struct amdgpu_winsys_bo *entries;
88 };
89
90 bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf);
91 void amdgpu_bo_destroy(struct pb_buffer *_buf);
92 void amdgpu_bo_init_functions(struct amdgpu_winsys *ws);
93
94 bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry);
95 struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap,
96 unsigned entry_size,
97 unsigned group_index);
98 void amdgpu_bo_slab_free(void *priv, struct pb_slab *slab);
99
100 static inline
amdgpu_winsys_bo(struct pb_buffer * bo)101 struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer *bo)
102 {
103 return (struct amdgpu_winsys_bo *)bo;
104 }
105
106 static inline
amdgpu_slab(struct pb_slab * slab)107 struct amdgpu_slab *amdgpu_slab(struct pb_slab *slab)
108 {
109 return (struct amdgpu_slab *)slab;
110 }
111
112 static inline
amdgpu_winsys_bo_reference(struct amdgpu_winsys_bo ** dst,struct amdgpu_winsys_bo * src)113 void amdgpu_winsys_bo_reference(struct amdgpu_winsys_bo **dst,
114 struct amdgpu_winsys_bo *src)
115 {
116 pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src);
117 }
118
119 #endif
120