1/* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* 18 Art assembly interpreter notes: 19 20 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 21 handle invoke, allows higher-level code to create frame & shadow frame. 22 23 Once that's working, support direct entry code & eliminate shadow frame (and 24 excess locals allocation. 25 26 Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the 27 base of the vreg array within the shadow frame. Access the other fields, 28 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 29 the shadow frame mechanism of double-storing object references - via xFP & 30 number_of_vregs_. 31 32 */ 33 34/* 35ARM64 Runtime register usage conventions. 36 37 r0 : w0 is 32-bit return register and x0 is 64-bit. 38 r0-r7 : Argument registers. 39 r8-r15 : Caller save registers (used as temporary registers). 40 r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by 41 the linker, by the trampolines and other stubs (the backend uses 42 these as temporary registers). 43 r18 : Caller save register (used as temporary register). 44 r19 : Pointer to thread-local storage. 45 r20-r29: Callee save registers. 46 r30 : (lr) is reserved (the link register). 47 rsp : (sp) is reserved (the stack pointer). 48 rzr : (zr) is reserved (the zero register). 49 50 Floating-point registers 51 v0-v31 52 53 v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). 54 This is analogous to the C/C++ (hard-float) calling convention. 55 v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. 56 Also used as temporary and codegen scratch registers. 57 58 v0-v7 and v16-v31 : trashed across C calls. 59 v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). 60 61 v16-v31: Used as codegen temp/scratch. 62 v8-v15 : Can be used for promotion. 63 64 Must maintain 16-byte stack alignment. 65 66Mterp notes: 67 68The following registers have fixed assignments: 69 70 reg nick purpose 71 x20 xPC interpreted program counter, used for fetching instructions 72 x21 xFP interpreted frame pointer, used for accessing locals and args 73 x22 xSELF self (Thread) pointer 74 x23 xINST first 16-bit code unit of current instruction 75 x24 xIBASE interpreted instruction base pointer, used for computed goto 76 x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). 77 x26 wPROFILE jit profile hotness countdown 78 x16 ip scratch reg 79 x17 ip2 scratch reg (used by macros) 80 81Macros are provided for common operations. They MUST NOT alter unspecified registers or condition 82codes. 83*/ 84 85/* 86 * This is a #include, not a %include, because we want the C pre-processor 87 * to expand the macros into assembler assignment statements. 88 */ 89#include "asm_support.h" 90#include "interpreter/cfi_asm_support.h" 91 92#define MTERP_PROFILE_BRANCHES 1 93#define MTERP_LOGGING 0 94 95/* During bringup, we'll use the shadow frame model instead of xFP */ 96/* single-purpose registers, given names for clarity */ 97#define xPC x20 98#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). 99#define CFI_TMP 0 // DWARF register number of the first argument register (r0). 100#define xFP x21 101#define xSELF x22 102#define xINST x23 103#define wINST w23 104#define xIBASE x24 105#define xREFS x25 106#define wPROFILE w26 107#define xPROFILE x26 108#define ip x16 109#define ip2 x17 110 111/* 112 * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, 113 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 114 */ 115#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 116#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 117#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 118#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 119#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 120#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 121#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 122#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) 123#define OFF_FP_SHADOWFRAME OFF_FP(0) 124 125/* 126 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 127 * be done *before* something throws. 128 * 129 * It's okay to do this more than once. 130 * 131 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 132 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 133 * offset into the code_items_[] array. For effiency, we will "export" the 134 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 135 * to convert to a dex pc when needed. 136 */ 137.macro EXPORT_PC 138 str xPC, [xFP, #OFF_FP_DEX_PC_PTR] 139.endm 140 141/* 142 * Fetch the next instruction from xPC into wINST. Does not advance xPC. 143 */ 144.macro FETCH_INST 145 ldrh wINST, [xPC] 146.endm 147 148/* 149 * Fetch the next instruction from the specified offset. Advances xPC 150 * to point to the next instruction. "_count" is in 16-bit code units. 151 * 152 * Because of the limited size of immediate constants on ARM, this is only 153 * suitable for small forward movements (i.e. don't try to implement "goto" 154 * with this). 155 * 156 * This must come AFTER anything that can throw an exception, or the 157 * exception catch may miss. (This also implies that it must come after 158 * EXPORT_PC.) 159 */ 160.macro FETCH_ADVANCE_INST count 161 ldrh wINST, [xPC, #((\count)*2)]! 162.endm 163 164/* 165 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 166 * src and dest registers are parameterized (not hard-wired to xPC and xINST). 167 */ 168.macro PREFETCH_ADVANCE_INST dreg, sreg, count 169 ldrh \dreg, [\sreg, #((\count)*2)]! 170.endm 171 172/* 173 * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load 174 * xINST ahead of possible exception point. Be sure to manually advance xPC 175 * later. 176 */ 177.macro PREFETCH_INST count 178 ldrh wINST, [xPC, #((\count)*2)] 179.endm 180 181/* Advance xPC by some number of code units. */ 182.macro ADVANCE count 183 add xPC, xPC, #((\count)*2) 184.endm 185 186/* 187 * Fetch the next instruction from an offset specified by _reg and advance xPC. 188 * xPC to point to the next instruction. "_reg" must specify the distance 189 * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. 190 * 191 */ 192.macro FETCH_ADVANCE_INST_RB reg 193 add xPC, xPC, \reg, sxtw 194 ldrh wINST, [xPC] 195.endm 196 197/* 198 * Fetch a half-word code unit from an offset past the current PC. The 199 * "_count" value is in 16-bit code units. Does not advance xPC. 200 * 201 * The "_S" variant works the same but treats the value as signed. 202 */ 203.macro FETCH reg, count 204 ldrh \reg, [xPC, #((\count)*2)] 205.endm 206 207.macro FETCH_S reg, count 208 ldrsh \reg, [xPC, #((\count)*2)] 209.endm 210 211/* 212 * Fetch one byte from an offset past the current PC. Pass in the same 213 * "_count" as you would for FETCH, and an additional 0/1 indicating which 214 * byte of the halfword you want (lo/hi). 215 */ 216.macro FETCH_B reg, count, byte 217 ldrb \reg, [xPC, #((\count)*2+(\byte))] 218.endm 219 220/* 221 * Put the instruction's opcode field into the specified register. 222 */ 223.macro GET_INST_OPCODE reg 224 and \reg, xINST, #255 225.endm 226 227/* 228 * Put the prefetched instruction's opcode field into the specified register. 229 */ 230.macro GET_PREFETCHED_OPCODE oreg, ireg 231 and \oreg, \ireg, #255 232.endm 233 234/* 235 * Begin executing the opcode in _reg. Clobbers reg 236 */ 237 238.macro GOTO_OPCODE reg 239 add \reg, xIBASE, \reg, lsl #${handler_size_bits} 240 br \reg 241.endm 242.macro GOTO_OPCODE_BASE base,reg 243 add \reg, \base, \reg, lsl #${handler_size_bits} 244 br \reg 245.endm 246 247/* 248 * Get/set the 32-bit value from a Dalvik register. 249 */ 250.macro GET_VREG reg, vreg 251 ldr \reg, [xFP, \vreg, uxtw #2] 252.endm 253.macro SET_VREG reg, vreg 254 str \reg, [xFP, \vreg, uxtw #2] 255 str wzr, [xREFS, \vreg, uxtw #2] 256.endm 257.macro SET_VREG_OBJECT reg, vreg, tmpreg 258 str \reg, [xFP, \vreg, uxtw #2] 259 str \reg, [xREFS, \vreg, uxtw #2] 260.endm 261 262/* 263 * Get/set the 64-bit value from a Dalvik register. 264 * TUNING: can we do better here? 265 */ 266.macro GET_VREG_WIDE reg, vreg 267 add ip2, xFP, \vreg, lsl #2 268 ldr \reg, [ip2] 269.endm 270.macro SET_VREG_WIDE reg, vreg 271 add ip2, xFP, \vreg, lsl #2 272 str \reg, [ip2] 273 add ip2, xREFS, \vreg, lsl #2 274 str xzr, [ip2] 275.endm 276 277/* 278 * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. 279 * Used to avoid an extra instruction in int-to-long. 280 */ 281.macro GET_VREG_S reg, vreg 282 ldrsw \reg, [xFP, \vreg, uxtw #2] 283.endm 284 285/* 286 * Convert a virtual register index into an address. 287 */ 288.macro VREG_INDEX_TO_ADDR reg, vreg 289 add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ 290.endm 291 292/* 293 * Refresh handler table. 294 */ 295.macro REFRESH_IBASE 296 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 297.endm 298 299/* 300 * Save two registers to the stack. 301 */ 302.macro SAVE_TWO_REGS reg1, reg2, offset 303 stp \reg1, \reg2, [sp, #(\offset)] 304 .cfi_rel_offset \reg1, (\offset) 305 .cfi_rel_offset \reg2, (\offset) + 8 306.endm 307 308/* 309 * Restore two registers from the stack. 310 */ 311.macro RESTORE_TWO_REGS reg1, reg2, offset 312 ldp \reg1, \reg2, [sp, #(\offset)] 313 .cfi_restore \reg1 314 .cfi_restore \reg2 315.endm 316 317/* 318 * Increase frame size and save two registers to the bottom of the stack. 319 */ 320.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment 321 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! 322 .cfi_adjust_cfa_offset (\frame_adjustment) 323 .cfi_rel_offset \reg1, 0 324 .cfi_rel_offset \reg2, 8 325.endm 326 327/* 328 * Restore two registers from the bottom of the stack and decrease frame size. 329 */ 330.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment 331 ldp \reg1, \reg2, [sp], #(\frame_adjustment) 332 .cfi_restore \reg1 333 .cfi_restore \reg2 334 .cfi_adjust_cfa_offset -(\frame_adjustment) 335.endm 336 337/* 338 * cfi support macros. 339 */ 340.macro ENTRY name 341 .type \name, #function 342 .global \name 343 /* Cache alignment for function entry */ 344 .balign 16 345\name: 346 .cfi_startproc 347.endm 348 349.macro END name 350 .cfi_endproc 351 .size \name, .-\name 352.endm 353