1@c Copyright (C) 2008-2016 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4 5@ifset GENERIC 6@page 7@node LM32-Dependent 8@chapter LM32 Dependent Features 9@end ifset 10 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter LM�" Dependent Features 14@end ifclear 15 16@cindex LM32 support 17@menu 18* LM32 Options:: Options 19* LM32 Syntax:: Syntax 20* LM32 Opcodes:: Opcodes 21@end menu 22 23@node LM32 Options 24@section Options 25@cindex LM32 options (none) 26@cindex options for LM32 (none) 27 28@table @code 29 30@cindex @code{-mmultiply-enabled} command line option, LM32 31@item -mmultiply-enabled 32Enable multiply instructions. 33 34@cindex @code{-mdivide-enabled} command line option, LM32 35@item -mdivide-enabled 36Enable divide instructions. 37 38@cindex @code{-mbarrel-shift-enabled} command line option, LM32 39@item -mbarrel-shift-enabled 40Enable barrel-shift instructions. 41 42@cindex @code{-msign-extend-enabled} command line option, LM32 43@item -msign-extend-enabled 44Enable sign extend instructions. 45 46@cindex @code{-muser-enabled} command line option, LM32 47@item -muser-enabled 48Enable user defined instructions. 49 50@cindex @code{-micache-enabled} command line option, LM32 51@item -micache-enabled 52Enable instruction cache related CSRs. 53 54@cindex @code{-mdcache-enabled} command line option, LM32 55@item -mdcache-enabled 56Enable data cache related CSRs. 57 58@cindex @code{-mbreak-enabled} command line option, LM32 59@item -mbreak-enabled 60Enable break instructions. 61 62@cindex @code{-mall-enabled} command line option, LM32 63@item -mall-enabled 64Enable all instructions and CSRs. 65 66@end table 67 68 69@node LM32 Syntax 70@section Syntax 71@menu 72* LM32-Regs:: Register Names 73* LM32-Modifiers:: Relocatable Expression Modifiers 74* LM32-Chars:: Special Characters 75@end menu 76 77@node LM32-Regs 78@subsection Register Names 79 80@cindex LM32 register names 81@cindex register names, LM32 82 83LM32 has 32 x 32-bit general purpose registers @samp{r0}, 84@samp{r1}, ... @samp{r31}. 85 86The following aliases are defined: @samp{gp} - @samp{r26}, 87@samp{fp} - @samp{r27}, @samp{sp} - @samp{r28}, 88@samp{ra} - @samp{r29}, @samp{ea} - @samp{r30}, 89@samp{ba} - @samp{r31}. 90 91LM32 has the following Control and Status Registers (CSRs). 92 93@table @code 94@item IE 95Interrupt enable. 96@item IM 97Interrupt mask. 98@item IP 99Interrupt pending. 100@item ICC 101Instruction cache control. 102@item DCC 103Data cache control. 104@item CC 105Cycle counter. 106@item CFG 107Configuration. 108@item EBA 109Exception base address. 110@item DC 111Debug control. 112@item DEBA 113Debug exception base address. 114@item JTX 115JTAG transmit. 116@item JRX 117JTAG receive. 118@item BP0 119Breakpoint 0. 120@item BP1 121Breakpoint 1. 122@item BP2 123Breakpoint 2. 124@item BP3 125Breakpoint 3. 126@item WP0 127Watchpoint 0. 128@item WP1 129Watchpoint 1. 130@item WP2 131Watchpoint 2. 132@item WP3 133Watchpoint 3. 134@end table 135 136@node LM32-Modifiers 137@subsection Relocatable Expression Modifiers 138 139@cindex LM32 modifiers 140@cindex syntax, LM32 141 142The assembler supports several modifiers when using relocatable addresses 143in LM32 instruction operands. The general syntax is the following: 144 145@smallexample 146modifier(relocatable-expression) 147@end smallexample 148 149@table @code 150@cindex symbol modifiers 151 152@item lo 153 154This modifier allows you to use bits 0 through 15 of 155an address expression as 16 bit relocatable expression. 156 157@item hi 158 159This modifier allows you to use bits 16 through 23 of an address expression 160as 16 bit relocatable expression. 161 162For example 163 164@smallexample 165ori r4, r4, lo(sym+10) 166orhi r4, r4, hi(sym+10) 167@end smallexample 168 169@item gp 170 171This modified creates a 16-bit relocatable expression that is 172the offset of the symbol from the global pointer. 173 174@smallexample 175mva r4, gp(sym) 176@end smallexample 177 178@item got 179 180This modifier places a symbol in the GOT and creates a 16-bit 181relocatable expression that is the offset into the GOT of this 182symbol. 183 184@smallexample 185lw r4, (gp+got(sym)) 186@end smallexample 187 188@item gotofflo16 189 190This modifier allows you to use the bits 0 through 15 of an 191address which is an offset from the GOT. 192 193@item gotoffhi16 194 195This modifier allows you to use the bits 16 through 31 of an 196address which is an offset from the GOT. 197 198@smallexample 199orhi r4, r4, gotoffhi16(lsym) 200addi r4, r4, gotofflo16(lsym) 201@end smallexample 202 203@end table 204 205@node LM32-Chars 206@subsection Special Characters 207 208@cindex line comment character, LM32 209@cindex LM32 line comment character 210The presence of a @samp{#} on a line indicates the start of a comment 211that extends to the end of the current line. Note that if a line 212starts with a @samp{#} character then it can also be a logical line 213number directive (@pxref{Comments}) or a preprocessor 214control command (@pxref{Preprocessing}). 215 216@cindex line separator, LM32 217@cindex statement separator, LM32 218@cindex LM32 line separator 219A semicolon (@samp{;}) can be used to separate multiple statements on 220the same line. 221 222@node LM32 Opcodes 223@section Opcodes 224 225@cindex LM32 opcode summary 226@cindex opcode summary, LM32 227@cindex mnemonics, LM32 228@cindex instruction summary, LM32 229For detailed information on the LM32 machine instruction set, see 230@url{http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/}. 231 232@code{@value{AS}} implements all the standard LM32 opcodes. 233