1@c Copyright (C) 1997-2016 Free Software Foundation, Inc.
2@c This is part of the GAS manual.
3@c For copying conditions, see the file as.texinfo.
4
5@node V850-Dependent
6@chapter v850 Dependent Features
7
8@cindex V850 support
9@menu
10* V850 Options::              Options
11* V850 Syntax::               Syntax
12* V850 Floating Point::       Floating Point
13* V850 Directives::           V850 Machine Directives
14* V850 Opcodes::              Opcodes
15@end menu
16
17@node V850 Options
18@section Options
19@cindex V850 options (none)
20@cindex options for V850 (none)
21@code{@value{AS}} supports the following additional command-line options
22for the V850 processor family:
23
24@cindex command line options, V850
25@cindex V850 command line options
26@table @code
27
28@cindex @code{-wsigned_overflow} command line option, V850
29@item -wsigned_overflow
30Causes warnings to be produced when signed immediate values overflow the
31space available for then within their opcodes.  By default this option
32is disabled as it is possible to receive spurious warnings due to using
33exact bit patterns as immediate constants.
34
35@cindex @code{-wunsigned_overflow} command line option, V850
36@item -wunsigned_overflow
37Causes warnings to be produced when unsigned immediate values overflow
38the space available for then within their opcodes.  By default this
39option is disabled as it is possible to receive spurious warnings due to
40using exact bit patterns as immediate constants.
41
42@cindex @code{-mv850} command line option, V850
43@item -mv850
44Specifies that the assembled code should be marked as being targeted at
45the V850 processor.  This allows the linker to detect attempts to link
46such code with code assembled for other processors.
47
48@cindex @code{-mv850e} command line option, V850
49@item -mv850e
50Specifies that the assembled code should be marked as being targeted at
51the V850E processor.  This allows the linker to detect attempts to link
52such code with code assembled for other processors.
53
54@cindex @code{-mv850e1} command line option, V850
55@item -mv850e1
56Specifies that the assembled code should be marked as being targeted at
57the V850E1 processor.  This allows the linker to detect attempts to link
58such code with code assembled for other processors.
59
60@cindex @code{-mv850any} command line option, V850
61@item -mv850any
62Specifies that the assembled code should be marked as being targeted at
63the V850 processor but support instructions that are specific to the
64extended variants of the process.  This allows the production of
65binaries that contain target specific code, but which are also intended
66to be used in a generic fashion.  For example libgcc.a contains generic
67routines used by the code produced by GCC for all versions of the v850
68architecture, together with support routines only used by the V850E
69architecture.
70
71@cindex @code{-mv850e2} command line option, V850
72@item -mv850e2
73Specifies that the assembled code should be marked as being targeted at
74the V850E2 processor.  This allows the linker to detect attempts to link
75such code with code assembled for other processors.
76
77@cindex @code{-mv850e2v3} command line option, V850
78@item -mv850e2v3
79Specifies that the assembled code should be marked as being targeted at
80the V850E2V3 processor.  This allows the linker to detect attempts to link
81such code with code assembled for other processors.
82
83@cindex @code{-mv850e2v4} command line option, V850
84@item -mv850e2v4
85This is an alias for @option{-mv850e3v5}.
86
87@cindex @code{-mv850e3v5} command line option, V850
88@item -mv850e3v5
89Specifies that the assembled code should be marked as being targeted at
90the V850E3V5 processor.  This allows the linker to detect attempts to link
91such code with code assembled for other processors.
92
93@cindex @code{-mrelax} command line option, V850
94@item -mrelax
95Enables relaxation.  This allows the .longcall and .longjump pseudo
96ops to be used in the assembler source code.  These ops label sections
97of code which are either a long function call or a long branch.  The
98assembler will then flag these sections of code and the linker will
99attempt to relax them.
100
101@cindex @code{-mgcc-abi} command line option, V850
102@item -mgcc-abi
103Marks the generated object file as supporting the old GCC ABI.
104
105@cindex @code{-mrh850-abi} command line option, V850
106@item -mrh850-abi
107Marks the generated object file as supporting the RH850 ABI.  This is
108the default.
109
110@cindex @code{-m8byte-align} command line option, V850
111@item -m8byte-align
112Marks the generated object file as supporting a maximum 64-bits of
113alignment for variables defined in the source code.
114
115@cindex @code{-m4byte-align} command line option, V850
116@item -m4byte-align
117Marks the generated object file as supporting a maximum 32-bits of
118alignment for variables defined in the source code.  This is the
119default.
120
121@cindex @code{-msoft-float} command line option, V850
122@item -msoft-float
123Marks the generated object file as not using any floating point
124instructions - and hence can be linked with other V850 binaries
125that do or do not use floating point.  This is the default for
126binaries for architectures earlier than the @code{e2v3}.
127
128@cindex @code{-mhard-float} command line option, V850
129@item -mhard-float
130Marks the generated object file as one that uses floating point
131instructions - and hence can only be linked with other V850 binaries
132that use the same kind of floating point instructions, or with
133binaries that do not use floating point at all.  This is the default
134for binaries the @code{e2v3} and later architectures.
135
136@end table
137
138@node V850 Syntax
139@section Syntax
140@menu
141* V850-Chars::                Special Characters
142* V850-Regs::                 Register Names
143@end menu
144
145@node V850-Chars
146@subsection Special Characters
147
148@cindex line comment character, V850
149@cindex V850 line comment character
150@samp{#} is the line comment character.  If a @samp{#} appears as the
151first character of a line, the whole line is treated as a comment, but
152in this case the line can also be a logical line number directive
153(@pxref{Comments}) or a preprocessor control command
154(@pxref{Preprocessing}).
155
156Two dashes (@samp{--}) can also be used to start a line comment.
157
158@cindex line separator, V850
159@cindex statement separator, V850
160@cindex V850 line separator
161
162The @samp{;} character can be used to separate statements on the same
163line.
164
165@node V850-Regs
166@subsection Register Names
167
168@cindex V850 register names
169@cindex register names, V850
170@code{@value{AS}} supports the following names for registers:
171@table @code
172@cindex @code{zero} register, V850
173@item general register 0
174r0, zero
175@item general register 1
176r1
177@item general register 2
178r2, hp
179@cindex @code{sp} register, V850
180@item general register 3
181r3, sp
182@cindex @code{gp} register, V850
183@item general register 4
184r4, gp
185@cindex @code{tp} register, V850
186@item general register 5
187r5, tp
188@item general register 6
189r6
190@item general register 7
191r7
192@item general register 8
193r8
194@item general register 9
195r9
196@item general register 10
197r10
198@item general register 11
199r11
200@item general register 12
201r12
202@item general register 13
203r13
204@item general register 14
205r14
206@item general register 15
207r15
208@item general register 16
209r16
210@item general register 17
211r17
212@item general register 18
213r18
214@item general register 19
215r19
216@item general register 20
217r20
218@item general register 21
219r21
220@item general register 22
221r22
222@item general register 23
223r23
224@item general register 24
225r24
226@item general register 25
227r25
228@item general register 26
229r26
230@item general register 27
231r27
232@item general register 28
233r28
234@item general register 29
235r29
236@cindex @code{ep} register, V850
237@item general register 30
238r30, ep
239@cindex @code{lp} register, V850
240@item general register 31
241r31, lp
242@cindex @code{eipc} register, V850
243@item system register 0
244eipc
245@cindex @code{eipsw} register, V850
246@item system register 1
247eipsw
248@cindex @code{fepc} register, V850
249@item system register 2
250fepc
251@cindex @code{fepsw} register, V850
252@item system register 3
253fepsw
254@cindex @code{ecr} register, V850
255@item system register 4
256ecr
257@cindex @code{psw} register, V850
258@item system register 5
259psw
260@cindex @code{ctpc} register, V850
261@item system register 16
262ctpc
263@cindex @code{ctpsw} register, V850
264@item system register 17
265ctpsw
266@cindex @code{dbpc} register, V850
267@item system register 18
268dbpc
269@cindex @code{dbpsw} register, V850
270@item system register 19
271dbpsw
272@cindex @code{ctbp} register, V850
273@item system register 20
274ctbp
275@end table
276
277@node V850 Floating Point
278@section Floating Point
279
280@cindex floating point, V850 (@sc{ieee})
281@cindex V850 floating point (@sc{ieee})
282The V850 family uses @sc{ieee} floating-point numbers.
283
284@node V850 Directives
285@section V850 Machine Directives
286
287@cindex machine directives, V850
288@cindex V850 machine directives
289@table @code
290@cindex @code{offset} directive, V850
291@item .offset @var{<expression>}
292Moves the offset into the current section to the specified amount.
293
294@cindex @code{section} directive, V850
295@item .section "name", <type>
296This is an extension to the standard .section directive.  It sets the
297current section to be <type> and creates an alias for this section
298called "name".
299
300@cindex @code{.v850} directive, V850
301@item .v850
302Specifies that the assembled code should be marked as being targeted at
303the V850 processor.  This allows the linker to detect attempts to link
304such code with code assembled for other processors.
305
306@cindex @code{.v850e} directive, V850
307@item .v850e
308Specifies that the assembled code should be marked as being targeted at
309the V850E processor.  This allows the linker to detect attempts to link
310such code with code assembled for other processors.
311
312@cindex @code{.v850e1} directive, V850
313@item .v850e1
314Specifies that the assembled code should be marked as being targeted at
315the V850E1 processor.  This allows the linker to detect attempts to link
316such code with code assembled for other processors.
317
318@cindex @code{.v850e2} directive, V850
319@item .v850e2
320Specifies that the assembled code should be marked as being targeted at
321the V850E2 processor.  This allows the linker to detect attempts to link
322such code with code assembled for other processors.
323
324@cindex @code{.v850e2v3} directive, V850
325@item .v850e2v3
326Specifies that the assembled code should be marked as being targeted at
327the V850E2V3 processor.  This allows the linker to detect attempts to link
328such code with code assembled for other processors.
329
330@cindex @code{.v850e2v4} directive, V850
331@item .v850e2v4
332Specifies that the assembled code should be marked as being targeted at
333the V850E3V5 processor.  This allows the linker to detect attempts to link
334such code with code assembled for other processors.
335
336@cindex @code{.v850e3v5} directive, V850
337@item .v850e3v5
338Specifies that the assembled code should be marked as being targeted at
339the V850E3V5 processor.  This allows the linker to detect attempts to link
340such code with code assembled for other processors.
341
342@end table
343
344@node V850 Opcodes
345@section Opcodes
346
347@cindex V850 opcodes
348@cindex opcodes for V850
349@code{@value{AS}} implements all the standard V850 opcodes.
350
351@code{@value{AS}} also implements the following pseudo ops:
352
353@table @code
354
355@cindex @code{hi0} pseudo-op, V850
356@item hi0()
357Computes the higher 16 bits of the given expression and stores it into
358the immediate operand field of the given instruction.  For example:
359
360    @samp{mulhi hi0(here - there), r5, r6}
361
362computes the difference between the address of labels 'here' and
363'there', takes the upper 16 bits of this difference, shifts it down 16
364bits and then multiplies it by the lower 16 bits in register 5, putting
365the result into register 6.
366
367@cindex @code{lo} pseudo-op, V850
368@item lo()
369Computes the lower 16 bits of the given expression and stores it into
370the immediate operand field of the given instruction.  For example:
371
372    @samp{addi lo(here - there), r5, r6}
373
374computes the difference between the address of labels 'here' and
375'there', takes the lower 16 bits of this difference and adds it to
376register 5, putting the result into register 6.
377
378@cindex @code{hi} pseudo-op, V850
379@item hi()
380Computes the higher 16 bits of the given expression and then adds the
381value of the most significant bit of the lower 16 bits of the expression
382and stores the result into the immediate operand field of the given
383instruction.  For example the following code can be used to compute the
384address of the label 'here' and store it into register 6:
385
386    @samp{movhi hi(here), r0, r6}
387    @samp{movea lo(here), r6, r6}
388
389The reason for this special behaviour is that movea performs a sign
390extension on its immediate operand.  So for example if the address of
391'here' was 0xFFFFFFFF then without the special behaviour of the hi()
392pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
393movea instruction would takes its immediate operand, 0xFFFF, sign extend
394it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
395which is wrong (the fifth nibble is E).  With the hi() pseudo op adding
396in the top bit of the lo() pseudo op, the movhi instruction actually
397stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
398stores 0xFFFFFFFF into r6 - the right value.
399
400@cindex @code{hilo} pseudo-op, V850
401@item hilo()
402Computes the 32 bit value of the given expression and stores it into
403the immediate operand field of the given instruction (which must be a
404mov instruction).  For example:
405
406    @samp{mov hilo(here), r6}
407
408computes the absolute address of label 'here' and puts the result into
409register 6.
410
411@cindex @code{sdaoff} pseudo-op, V850
412@item sdaoff()
413Computes the offset of the named variable from the start of the Small
414Data Area (whoes address is held in register 4, the GP register) and
415stores the result as a 16 bit signed value in the immediate operand
416field of the given instruction.  For example:
417
418      @samp{ld.w sdaoff(_a_variable)[gp],r6}
419
420loads the contents of the location pointed to by the label '_a_variable'
421into register 6, provided that the label is located somewhere within +/-
42232K of the address held in the GP register.  [Note the linker assumes
423that the GP register contains a fixed address set to the address of the
424label called '__gp'.  This can either be set up automatically by the
425linker, or specifically set by using the @samp{--defsym __gp=<value>}
426command line option].
427
428@cindex @code{tdaoff} pseudo-op, V850
429@item tdaoff()
430Computes the offset of the named variable from the start of the Tiny
431Data Area (whoes address is held in register 30, the EP register) and
432stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
433operand field of the given instruction.  For example:
434
435      @samp{sld.w tdaoff(_a_variable)[ep],r6}
436
437loads the contents of the location pointed to by the label '_a_variable'
438into register 6, provided that the label is located somewhere within +256
439bytes of the address held in the EP register.  [Note the linker assumes
440that the EP register contains a fixed address set to the address of the
441label called '__ep'.  This can either be set up automatically by the
442linker, or specifically set by using the @samp{--defsym __ep=<value>}
443command line option].
444
445@cindex @code{zdaoff} pseudo-op, V850
446@item zdaoff()
447Computes the offset of the named variable from address 0 and stores the
448result as a 16 bit signed value in the immediate operand field of the
449given instruction.  For example:
450
451      @samp{movea zdaoff(_a_variable),zero,r6}
452
453puts the address of the label '_a_variable' into register 6, assuming
454that the label is somewhere within the first 32K of memory.  (Strictly
455speaking it also possible to access the last 32K of memory as well, as
456the offsets are signed).
457
458@cindex @code{ctoff} pseudo-op, V850
459@item ctoff()
460Computes the offset of the named variable from the start of the Call
461Table Area (whoes address is helg in system register 20, the CTBP
462register) and stores the result a 6 or 16 bit unsigned value in the
463immediate field of then given instruction or piece of data.  For
464example:
465
466     @samp{callt ctoff(table_func1)}
467
468will put the call the function whoes address is held in the call table
469at the location labeled 'table_func1'.
470
471@cindex @code{longcall} pseudo-op, V850
472@item .longcall @code{name}
473Indicates that the following sequence of instructions is a long call
474to function @code{name}.  The linker will attempt to shorten this call
475sequence if @code{name} is within a 22bit offset of the call.  Only
476valid if the @code{-mrelax} command line switch has been enabled.
477
478@cindex @code{longjump} pseudo-op, V850
479@item .longjump @code{name}
480Indicates that the following sequence of instructions is a long jump
481to label @code{name}.  The linker will attempt to shorten this code
482sequence if @code{name} is within a 22bit offset of the jump.  Only
483valid if the @code{-mrelax} command line switch has been enabled.
484
485@end table
486
487
488For information on the V850 instruction set, see @cite{V850
489Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.
490Ltd.
491