1 #as: -mcpu=archs 2 #objdump: -dr --show-raw-insn 3 4 .*: +file format .*arc.* 5 6 Disassembly of section .text: 7 8 [0-9a-f]+ <text_label-0x72>: 9 0: 20a8 0e40 lp 72 <text_label> 10 4: 20e8 0de0 lp 72 <text_label> 11 8: 20e8 0d60 lp 72 <text_label> 12 c: 20e8 0ce1 lpeq 72 <text_label> 13 10: 20e8 0c61 lpeq 72 <text_label> 14 14: 20e8 0be2 lpne 72 <text_label> 15 18: 20e8 0b62 lpne 72 <text_label> 16 1c: 20e8 0ae3 lpp 72 <text_label> 17 20: 20e8 0a63 lpp 72 <text_label> 18 24: 20e8 09e4 lpn 72 <text_label> 19 28: 20e8 0964 lpn 72 <text_label> 20 2c: 20e8 08e5 lpc 72 <text_label> 21 30: 20e8 0865 lpc 72 <text_label> 22 34: 20e8 07e5 lpc 72 <text_label> 23 38: 20e8 0766 lpnc 72 <text_label> 24 3c: 20e8 06e6 lpnc 72 <text_label> 25 40: 20e8 0666 lpnc 72 <text_label> 26 44: 20e8 05e7 lpv 72 <text_label> 27 48: 20e8 0567 lpv 72 <text_label> 28 4c: 20e8 04e8 lpnv 72 <text_label> 29 50: 20e8 0468 lpnv 72 <text_label> 30 54: 20e8 03e9 lpgt 72 <text_label> 31 58: 20e8 036a lpge 72 <text_label> 32 5c: 20e8 02eb lplt 72 <text_label> 33 60: 20e8 026c lple 72 <text_label> 34 64: 20e8 01ed lphi 72 <text_label> 35 68: 20e8 016e lpls 72 <text_label> 36 6c: 20e8 00ef lppnz 72 <text_label> 37 70: 78e0 nop_s 38