1@ VFP with Neon-style syntax
2	.syntax unified
3	.arch armv7-a
4
5	.include "itblock.s"
6
7func:
8	.macro testvmov cond="" f32=".f32" f64=".f64"
9	itblock 4 \cond
10        vmov\cond\f32 s0,s1
11        vmov\cond\f64 d0,d1
12        vmov\cond\f32 s0,#0.25
13        vmov\cond\f64 d0,#1.0
14	itblock 4 \cond
15        vmov\cond r0,s1
16        vmov\cond s0,r1
17        vmov\cond r0,r1,s2,s3
18        vmov\cond s0,s1,r2,r4
19	.endm
20
21	@ Test VFP vmov variants. These can all be conditional.
22	testvmov
23	testvmov eq
24
25	.macro monadic op cond="" f32=".f32" f64=".f64"
26	itblock 2 \cond
27	\op\cond\f32 s0,s1
28	\op\cond\f64 d0,d1
29	.endm
30
31	.macro monadic_c op
32	monadic \op
33	monadic \op eq
34	.endm
35
36	.macro dyadic op cond="" f32=".f32" f64=".f64"
37	itblock 2 \cond
38	\op\cond\f32 s0,s1,s2
39	\op\cond\f64 d0,d1,d2
40	.endm
41
42	.macro dyadic_c op
43	dyadic \op
44	dyadic \op eq
45	.endm
46
47	.macro dyadicz op cond="" f32=".f32" f64=".f64"
48	itblock 2 \cond
49	\op\cond\f32 s0,#0
50	\op\cond\f64 d0,#0
51	.endm
52
53	.macro dyadicz_c op
54	dyadicz \op
55	dyadicz \op eq
56	.endm
57
58	monadic_c vsqrt
59	monadic_c vabs
60	monadic_c vneg
61	monadic_c vcmp
62	monadic_c vcmpe
63
64	dyadic_c vnmul
65	dyadic_c vnmla
66	dyadic_c vnmls
67
68	dyadic_c vmul
69	dyadic_c vmla
70	dyadic_c vmls
71
72	dyadic_c vadd
73	dyadic_c vsub
74
75	dyadic_c vdiv
76
77	dyadicz_c vcmp
78	dyadicz_c vcmpe
79
80	.macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
81	itblock 4 \cond
82	vcvtz\cond\s32\f32 s0,s1
83	vcvtz\cond\u32\f32 s0,s1
84	vcvtz\cond\s32\f64 s0,d1
85	vcvtz\cond\u32\f64 s0,d1
86	.endm
87
88	cvtz
89	cvtz eq
90
91	.macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
92	itblock 4 \cond
93	vcvt\cond\s32\f32 s0,s1
94	vcvt\cond\u32\f32 s0,s1
95	vcvt\cond\f32\s32 s0,s1
96	vcvt\cond\f32\u32 s0,s1
97	itblock 4 \cond
98	vcvt\cond\f32\f64 s0,d1
99	vcvt\cond\f64\f32 d0,s1
100	vcvt\cond\s32\f64 s0,d1
101	vcvt\cond\u32\f64 s0,d1
102	itblock 2 \cond
103	vcvt\cond\f64\s32 d0,s1
104	vcvt\cond\f64\u32 d0,s1
105	.endm
106
107	cvt
108	cvt eq
109
110	.macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
111	itblock 4 \cond
112	vcvt\cond\s32\f32 s0,s0,#1
113	vcvt\cond\u32\f32 s0,s0,#1
114	vcvt\cond\f32\s32 s0,s0,#1
115	vcvt\cond\f32\u32 s0,s0,#1
116	itblock 4 \cond
117	vcvt\cond\s32\f64 d0,d0,#1
118	vcvt\cond\u32\f64 d0,d0,#1
119	vcvt\cond\f64\s32 d0,d0,#1
120	vcvt\cond\f64\u32 d0,d0,#1
121	itblock 4 \cond
122	vcvt\cond\f32\s16 s0,s0,#1
123	vcvt\cond\f32\u16 s0,s0,#1
124	vcvt\cond\f64\s16 d0,d0,#1
125	vcvt\cond\f64\u16 d0,d0,#1
126	itblock 4 \cond
127	vcvt\cond\s16\f32 s0,s0,#1
128	vcvt\cond\u16\f32 s0,s0,#1
129	vcvt\cond\s16\f64 d0,d0,#1
130	vcvt\cond\u16\f64 d0,d0,#1
131	.endm
132
133	cvti
134	cvti eq
135
136	.macro multi op cond="" n="" ia="ia" db="db"
137	itblock 4 \cond
138	\op\n\cond r0,{s3-s6}
139	\op\ia\cond r0,{s3-s6}
140	\op\ia\cond r0!,{s3-s6}
141	\op\db\cond r0!,{s3-s6}
142	itblock 4 \cond
143	\op\n\cond r0,{d3-d6}
144	\op\ia\cond r0,{d3-d6}
145	\op\ia\cond r0!,{d3-d6}
146	\op\db\cond r0!,{d3-d6}
147	.endm
148
149	multi vldm
150	multi vldm eq
151	multi vstm
152	multi vstm eq
153
154	.macro single op cond=""
155	itblock 2 \cond
156	\op\cond s0,[r0,#4]
157	\op\cond d0,[r0,#4]
158	.endm
159
160	single vldr
161	single vldr eq
162	single vstr
163	single vstr eq
164