1 /** @file 2 Support for PCI 2.2 standard. 3 4 This file includes the definitions in the following specifications, 5 PCI Local Bus Specification, 2.0 6 PCI-to-PCI Bridge Architecture Specification, 7 PC Card Standard, 8.0 8 9 Copyright (c) 2006 - 2008, Intel Corporation 10 All rights reserved. This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 **/ 19 20 #ifndef _PCI22_H_ 21 #define _PCI22_H_ 22 23 #define PCI_MAX_SEGMENT 0 24 #define PCI_MAX_BUS 255 25 #define PCI_MAX_DEVICE 31 26 #define PCI_MAX_FUNC 7 27 28 29 #pragma pack(1) 30 typedef struct { 31 UINT16 VendorId; 32 UINT16 DeviceId; 33 UINT16 Command; 34 UINT16 Status; 35 UINT8 RevisionID; 36 UINT8 ClassCode[3]; 37 UINT8 CacheLineSize; 38 UINT8 LatencyTimer; 39 UINT8 HeaderType; 40 UINT8 BIST; 41 } PCI_DEVICE_INDEPENDENT_REGION; 42 43 typedef struct { 44 UINT32 Bar[6]; 45 UINT32 CISPtr; 46 UINT16 SubsystemVendorID; 47 UINT16 SubsystemID; 48 UINT32 ExpansionRomBar; 49 UINT8 CapabilityPtr; 50 UINT8 Reserved1[3]; 51 UINT32 Reserved2; 52 UINT8 InterruptLine; 53 UINT8 InterruptPin; 54 UINT8 MinGnt; 55 UINT8 MaxLat; 56 } PCI_DEVICE_HEADER_TYPE_REGION; 57 58 typedef struct { 59 PCI_DEVICE_INDEPENDENT_REGION Hdr; 60 PCI_DEVICE_HEADER_TYPE_REGION Device; 61 } PCI_TYPE00; 62 63 /// 64 /// defined in PCI-to-PCI Bridge Architecture Specification 65 /// 66 typedef struct { 67 UINT32 Bar[2]; 68 UINT8 PrimaryBus; 69 UINT8 SecondaryBus; 70 UINT8 SubordinateBus; 71 UINT8 SecondaryLatencyTimer; 72 UINT8 IoBase; 73 UINT8 IoLimit; 74 UINT16 SecondaryStatus; 75 UINT16 MemoryBase; 76 UINT16 MemoryLimit; 77 UINT16 PrefetchableMemoryBase; 78 UINT16 PrefetchableMemoryLimit; 79 UINT32 PrefetchableBaseUpper32; 80 UINT32 PrefetchableLimitUpper32; 81 UINT16 IoBaseUpper16; 82 UINT16 IoLimitUpper16; 83 UINT8 CapabilityPtr; 84 UINT8 Reserved[3]; 85 UINT32 ExpansionRomBAR; 86 UINT8 InterruptLine; 87 UINT8 InterruptPin; 88 UINT16 BridgeControl; 89 } PCI_BRIDGE_CONTROL_REGISTER; 90 91 typedef struct { 92 PCI_DEVICE_INDEPENDENT_REGION Hdr; 93 PCI_BRIDGE_CONTROL_REGISTER Bridge; 94 } PCI_TYPE01; 95 96 typedef union { 97 PCI_TYPE00 Device; 98 PCI_TYPE01 Bridge; 99 } PCI_TYPE_GENERIC; 100 101 /// 102 /// CardBus Conroller Configuration Space, defined in PC Card Standard. 8.0 103 /// 104 typedef struct { 105 UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base 106 UINT8 Cap_Ptr; 107 UINT8 Reserved; 108 UINT16 SecondaryStatus; ///< Secondary Status 109 UINT8 PciBusNumber; ///< PCI Bus Number 110 UINT8 CardBusBusNumber; ///< CardBus Bus Number 111 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number 112 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer 113 UINT32 MemoryBase0; ///< Memory Base Register 0 114 UINT32 MemoryLimit0; ///< Memory Limit Register 0 115 UINT32 MemoryBase1; 116 UINT32 MemoryLimit1; 117 UINT32 IoBase0; 118 UINT32 IoLimit0; ///< I/O Base Register 0 119 UINT32 IoBase1; ///< I/O Limit Register 0 120 UINT32 IoLimit1; 121 UINT8 InterruptLine; ///< Interrupt Line 122 UINT8 InterruptPin; ///< Interrupt Pin 123 UINT16 BridgeControl; ///< Bridge Control 124 } PCI_CARDBUS_CONTROL_REGISTER; 125 126 /// 127 /// Definitions of PCI class bytes and manipulation macros. 128 /// 129 #define PCI_CLASS_OLD 0x00 130 #define PCI_CLASS_OLD_OTHER 0x00 131 #define PCI_CLASS_OLD_VGA 0x01 132 133 #define PCI_CLASS_MASS_STORAGE 0x01 134 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00 135 #define PCI_CLASS_MASS_STORAGE_IDE 0x01 136 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02 137 #define PCI_CLASS_MASS_STORAGE_IPI 0x03 138 #define PCI_CLASS_MASS_STORAGE_RAID 0x04 139 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80 140 141 #define PCI_CLASS_NETWORK 0x02 142 #define PCI_CLASS_NETWORK_ETHERNET 0x00 143 #define PCI_CLASS_NETWORK_TOKENRING 0x01 144 #define PCI_CLASS_NETWORK_FDDI 0x02 145 #define PCI_CLASS_NETWORK_ATM 0x03 146 #define PCI_CLASS_NETWORK_ISDN 0x04 147 #define PCI_CLASS_NETWORK_OTHER 0x80 148 149 #define PCI_CLASS_DISPLAY 0x03 150 #define PCI_CLASS_DISPLAY_VGA 0x00 151 #define PCI_IF_VGA_VGA 0x00 152 #define PCI_IF_VGA_8514 0x01 153 #define PCI_CLASS_DISPLAY_XGA 0x01 154 #define PCI_CLASS_DISPLAY_3D 0x02 155 #define PCI_CLASS_DISPLAY_OTHER 0x80 156 #define PCI_CLASS_DISPLAY_GFX 0x80 157 158 #define PCI_CLASS_MEDIA 0x04 159 #define PCI_CLASS_MEDIA_VIDEO 0x00 160 #define PCI_CLASS_MEDIA_AUDIO 0x01 161 #define PCI_CLASS_MEDIA_TELEPHONE 0x02 162 #define PCI_CLASS_MEDIA_OTHER 0x80 163 164 #define PCI_CLASS_MEMORY_CONTROLLER 0x05 165 #define PCI_CLASS_MEMORY_RAM 0x00 166 #define PCI_CLASS_MEMORY_FLASH 0x01 167 #define PCI_CLASS_MEMORY_OTHER 0x80 168 169 #define PCI_CLASS_BRIDGE 0x06 170 #define PCI_CLASS_BRIDGE_HOST 0x00 171 #define PCI_CLASS_BRIDGE_ISA 0x01 172 #define PCI_CLASS_BRIDGE_EISA 0x02 173 #define PCI_CLASS_BRIDGE_MCA 0x03 174 #define PCI_CLASS_BRIDGE_P2P 0x04 175 #define PCI_IF_BRIDGE_P2P 0x00 176 #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01 177 #define PCI_CLASS_BRIDGE_PCMCIA 0x05 178 #define PCI_CLASS_BRIDGE_NUBUS 0x06 179 #define PCI_CLASS_BRIDGE_CARDBUS 0x07 180 #define PCI_CLASS_BRIDGE_RACEWAY 0x08 181 #define PCI_CLASS_BRIDGE_OTHER 0x80 182 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80 183 184 #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers 185 #define PCI_SUBCLASS_SERIAL 0x00 186 #define PCI_IF_GENERIC_XT 0x00 187 #define PCI_IF_16450 0x01 188 #define PCI_IF_16550 0x02 189 #define PCI_IF_16650 0x03 190 #define PCI_IF_16750 0x04 191 #define PCI_IF_16850 0x05 192 #define PCI_IF_16950 0x06 193 #define PCI_SUBCLASS_PARALLEL 0x01 194 #define PCI_IF_PARALLEL_PORT 0x00 195 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01 196 #define PCI_IF_ECP_PARALLEL_PORT 0x02 197 #define PCI_IF_1284_CONTROLLER 0x03 198 #define PCI_IF_1284_DEVICE 0xFE 199 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02 200 #define PCI_SUBCLASS_MODEM 0x03 201 #define PCI_IF_GENERIC_MODEM 0x00 202 #define PCI_IF_16450_MODEM 0x01 203 #define PCI_IF_16550_MODEM 0x02 204 #define PCI_IF_16650_MODEM 0x03 205 #define PCI_IF_16750_MODEM 0x04 206 #define PCI_SUBCLASS_SCC_OTHER 0x80 207 208 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08 209 #define PCI_SUBCLASS_PIC 0x00 210 #define PCI_IF_8259_PIC 0x00 211 #define PCI_IF_ISA_PIC 0x01 212 #define PCI_IF_EISA_PIC 0x02 213 #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. 214 #define PCI_IF_APIC_CONTROLLER2 0x20 215 #define PCI_SUBCLASS_DMA 0x01 216 #define PCI_IF_8237_DMA 0x00 217 #define PCI_IF_ISA_DMA 0x01 218 #define PCI_IF_EISA_DMA 0x02 219 #define PCI_SUBCLASS_TIMER 0x02 220 #define PCI_IF_8254_TIMER 0x00 221 #define PCI_IF_ISA_TIMER 0x01 222 #define PCI_IF_EISA_TIMER 0x02 223 #define PCI_SUBCLASS_RTC 0x03 224 #define PCI_IF_GENERIC_RTC 0x00 225 #define PCI_IF_ISA_RTC 0x00 226 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller 227 #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80 228 229 #define PCI_CLASS_INPUT_DEVICE 0x09 230 #define PCI_SUBCLASS_KEYBOARD 0x00 231 #define PCI_SUBCLASS_PEN 0x01 232 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02 233 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03 234 #define PCI_SUBCLASS_GAMEPORT 0x04 235 #define PCI_IF_GAMEPORT 0x00 236 #define PCI_IF_GAMEPORT1 0x01 237 #define PCI_SUBCLASS_INPUT_OTHER 0x80 238 239 #define PCI_CLASS_DOCKING_STATION 0x0A 240 241 #define PCI_CLASS_PROCESSOR 0x0B 242 #define PCI_SUBCLASS_PROC_386 0x00 243 #define PCI_SUBCLASS_PROC_486 0x01 244 #define PCI_SUBCLASS_PROC_PENTIUM 0x02 245 #define PCI_SUBCLASS_PROC_ALPHA 0x10 246 #define PCI_SUBCLASS_PROC_POWERPC 0x20 247 #define PCI_SUBCLASS_PROC_MIPS 0x30 248 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor 249 250 #define PCI_CLASS_SERIAL 0x0C 251 #define PCI_CLASS_SERIAL_FIREWIRE 0x00 252 #define PCI_IF_1394 0x00 253 #define PCI_IF_1394_OPEN_HCI 0x10 254 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01 255 #define PCI_CLASS_SERIAL_SSA 0x02 256 #define PCI_CLASS_SERIAL_USB 0x03 257 #define PCI_IF_UHCI 0x00 258 #define PCI_IF_OHCI 0x10 259 #define PCI_IF_USB_OTHER 0x80 260 #define PCI_IF_USB_DEVICE 0xFE 261 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04 262 #define PCI_CLASS_SERIAL_SMB 0x05 263 264 #define PCI_CLASS_WIRELESS 0x0D 265 #define PCI_SUBCLASS_IRDA 0x00 266 #define PCI_SUBCLASS_IR 0x01 267 #define PCI_SUBCLASS_RF 0x02 268 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80 269 270 #define PCI_CLASS_INTELLIGENT_IO 0x0E 271 272 #define PCI_CLASS_SATELLITE 0x0F 273 #define PCI_SUBCLASS_TV 0x01 274 #define PCI_SUBCLASS_AUDIO 0x02 275 #define PCI_SUBCLASS_VOICE 0x03 276 #define PCI_SUBCLASS_DATA 0x04 277 278 #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller 279 #define PCI_SUBCLASS_NET_COMPUT 0x00 280 #define PCI_SUBCLASS_ENTERTAINMENT 0x10 281 #define PCI_SUBCLASS_SECURITY_OTHER 0x80 282 283 #define PCI_CLASS_DPIO 0x11 284 #define PCI_SUBCLASS_DPIO 0x00 285 #define PCI_SUBCLASS_DPIO_OTHER 0x80 286 287 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c)) 288 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s))) 289 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p))) 290 291 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY) 292 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0) 293 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1) 294 #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0) 295 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD) 296 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) 297 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE) 298 #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0) 299 #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0) 300 #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0) 301 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0) 302 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1) 303 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550) 304 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB) 305 306 // 307 // the definition of Header Type 308 // 309 #define HEADER_TYPE_DEVICE 0x00 310 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01 311 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02 312 #define HEADER_TYPE_MULTI_FUNCTION 0x80 313 // 314 // Mask of Header type 315 // 316 #define HEADER_LAYOUT_CODE 0x7f 317 318 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE)) 319 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) 320 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION) 321 322 /// 323 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification, 324 /// 325 #define PCI_BRIDGE_ROMBAR 0x38 326 327 #define PCI_MAX_BAR 0x0006 328 #define PCI_MAX_CONFIG_OFFSET 0x0100 329 330 #define PCI_VENDOR_ID_OFFSET 0x00 331 #define PCI_DEVICE_ID_OFFSET 0x02 332 #define PCI_COMMAND_OFFSET 0x04 333 #define PCI_PRIMARY_STATUS_OFFSET 0x06 334 #define PCI_REVISION_ID_OFFSET 0x08 335 #define PCI_CLASSCODE_OFFSET 0x09 336 #define PCI_CACHELINE_SIZE_OFFSET 0x0C 337 #define PCI_LATENCY_TIMER_OFFSET 0x0D 338 #define PCI_HEADER_TYPE_OFFSET 0x0E 339 #define PCI_BIST_OFFSET 0x0F 340 #define PCI_BASE_ADDRESSREG_OFFSET 0x10 341 #define PCI_CARDBUS_CIS_OFFSET 0x28 342 #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id 343 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C 344 #define PCI_SID_OFFSET 0x2E ///< SubSystem ID 345 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E 346 #define PCI_EXPANSION_ROM_BASE 0x30 347 #define PCI_CAPBILITY_POINTER_OFFSET 0x34 348 #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register 349 #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register 350 #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register 351 #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register 352 353 /// 354 /// defined in PCI-to-PCI Bridge Architecture Specification 355 /// 356 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 357 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 358 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a 359 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E 360 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E 361 362 /// 363 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system 364 /// 365 #define PCI_INT_LINE_UNKNOWN 0xFF 366 367 typedef union { 368 struct { 369 UINT32 Reg : 8; 370 UINT32 Func : 3; 371 UINT32 Dev : 5; 372 UINT32 Bus : 8; 373 UINT32 Reserved : 7; 374 UINT32 Enable : 1; 375 } Bits; 376 UINT32 Uint32; 377 } PCI_CONFIG_ACCESS_CF8; 378 379 #pragma pack() 380 381 #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001 382 #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002 383 #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004 384 #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008 385 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010 386 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020 387 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040 388 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080 389 #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100 390 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200 391 392 /// 393 /// defined in PCI-to-PCI Bridge Architecture Specification 394 /// 395 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001 396 #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002 397 #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004 398 #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008 399 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010 400 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020 401 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040 402 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080 403 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100 404 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200 405 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400 406 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800 407 408 /// 409 /// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard 410 /// 411 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080 412 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100 413 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200 414 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400 415 416 // 417 // Following are the PCI status control bit 418 // 419 #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010 420 #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020 421 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080 422 #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100 423 424 /// 425 /// defined in PC Card Standard 426 /// 427 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14 428 429 #pragma pack(1) 430 // 431 // PCI Capability List IDs and records 432 // 433 #define EFI_PCI_CAPABILITY_ID_PMI 0x01 434 #define EFI_PCI_CAPABILITY_ID_AGP 0x02 435 #define EFI_PCI_CAPABILITY_ID_VPD 0x03 436 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04 437 #define EFI_PCI_CAPABILITY_ID_MSI 0x05 438 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06 439 typedef struct { 440 UINT8 CapabilityID; 441 UINT8 NextItemPtr; 442 } EFI_PCI_CAPABILITY_HDR; 443 444 /// 445 /// Capability EFI_PCI_CAPABILITY_ID_PMI, defined in PCI Power Management Interface Specifiction 446 /// 447 typedef struct { 448 EFI_PCI_CAPABILITY_HDR Hdr; 449 UINT16 PMC; 450 UINT16 PMCSR; 451 UINT8 BridgeExtention; 452 UINT8 Data; 453 } EFI_PCI_CAPABILITY_PMI; 454 455 /// 456 /// Capability EFI_PCI_CAPABILITY_ID_AGP, defined in Accelerated Graphics Port Interface Specification 457 /// 458 typedef struct { 459 EFI_PCI_CAPABILITY_HDR Hdr; 460 UINT8 Rev; 461 UINT8 Reserved; 462 UINT32 Status; 463 UINT32 Command; 464 } EFI_PCI_CAPABILITY_AGP; 465 466 /// 467 /// Capability EFI_PCI_CAPABILITY_ID_VPD, in PCI2.2 Spec. 468 /// 469 typedef struct { 470 EFI_PCI_CAPABILITY_HDR Hdr; 471 UINT16 AddrReg; 472 UINT32 DataReg; 473 } EFI_PCI_CAPABILITY_VPD; 474 475 /// 476 /// Capability EFI_PCI_CAPABILITY_ID_SLOTID, defined in PCI-to-PCI Bridge Architeture Specification 477 /// 478 typedef struct { 479 EFI_PCI_CAPABILITY_HDR Hdr; 480 UINT8 ExpnsSlotReg; 481 UINT8 ChassisNo; 482 } EFI_PCI_CAPABILITY_SLOTID; 483 484 /// 485 /// Capability EFI_PCI_CAPABILITY_ID_MSI, defined in PCI2.2 486 /// 487 typedef struct { 488 EFI_PCI_CAPABILITY_HDR Hdr; 489 UINT16 MsgCtrlReg; 490 UINT32 MsgAddrReg; 491 UINT16 MsgDataReg; 492 } EFI_PCI_CAPABILITY_MSI32; 493 494 typedef struct { 495 EFI_PCI_CAPABILITY_HDR Hdr; 496 UINT16 MsgCtrlReg; 497 UINT32 MsgAddrRegLsdw; 498 UINT32 MsgAddrRegMsdw; 499 UINT16 MsgDataReg; 500 } EFI_PCI_CAPABILITY_MSI64; 501 502 /// 503 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, defined in CompactPCI Hot Swap Specification PICMG 2.1, R1.0 504 /// 505 typedef struct { 506 EFI_PCI_CAPABILITY_HDR Hdr; 507 /// 508 /// not finished - fields need to go here 509 /// 510 } EFI_PCI_CAPABILITY_HOTPLUG; 511 512 #define DEVICE_ID_NOCARE 0xFFFF 513 514 #define PCI_ACPI_UNUSED 0 515 #define PCI_BAR_NOCHANGE 0 516 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL 517 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL 518 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL 519 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL 520 521 #define PCI_BAR_IDX0 0x00 522 #define PCI_BAR_IDX1 0x01 523 #define PCI_BAR_IDX2 0x02 524 #define PCI_BAR_IDX3 0x03 525 #define PCI_BAR_IDX4 0x04 526 #define PCI_BAR_IDX5 0x05 527 #define PCI_BAR_ALL 0xFF 528 529 /// 530 /// EFI PCI Option ROM definitions 531 /// 532 #define EFI_ROOT_BRIDGE_LIST 'eprb' 533 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec. 534 535 typedef struct { 536 UINT8 Register; 537 UINT8 Function; 538 UINT8 Device; 539 UINT8 Bus; 540 UINT8 Reserved[4]; 541 } DEFIO_PCI_ADDR; 542 543 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55 544 #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R') 545 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00 546 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///<defined in UEFI spec. 547 548 typedef struct { 549 UINT16 Signature; ///< 0xaa55 550 UINT8 Reserved[0x16]; 551 UINT16 PcirOffset; 552 } PCI_EXPANSION_ROM_HEADER; 553 554 typedef struct { 555 UINT16 Signature; ///< 0xaa55 556 UINT8 Size512; 557 UINT8 InitEntryPoint[3]; 558 UINT8 Reserved[0x12]; 559 UINT16 PcirOffset; 560 } EFI_LEGACY_EXPANSION_ROM_HEADER; 561 562 typedef struct { 563 UINT32 Signature; ///< "PCIR" 564 UINT16 VendorId; 565 UINT16 DeviceId; 566 UINT16 Reserved0; 567 UINT16 Length; 568 UINT8 Revision; 569 UINT8 ClassCode[3]; 570 UINT16 ImageLength; 571 UINT16 CodeRevision; 572 UINT8 CodeType; 573 UINT8 Indicator; 574 UINT16 Reserved1; 575 } PCI_DATA_STRUCTURE; 576 577 /// 578 /// defined in EFI/UEFI Spec 579 /// 580 typedef struct { 581 UINT16 Signature; ///< 0xaa55 582 UINT16 InitializationSize; 583 UINT32 EfiSignature; ///< 0x0EF1 584 UINT16 EfiSubsystem; 585 UINT16 EfiMachineType; 586 UINT16 CompressionType; 587 UINT8 Reserved[8]; 588 UINT16 EfiImageHeaderOffset; 589 UINT16 PcirOffset; 590 } EFI_PCI_EXPANSION_ROM_HEADER; 591 592 typedef union { 593 UINT8 *Raw; 594 PCI_EXPANSION_ROM_HEADER *Generic; 595 EFI_PCI_EXPANSION_ROM_HEADER *Efi; 596 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt; 597 } EFI_PCI_ROM_HEADER; 598 599 #pragma pack() 600 601 #endif 602