1%default { "gt_bias":"0" }
2    /*
3     * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
4     * into the destination register based on the comparison results.
5     *
6     * for: cmpl-float, cmpg-float
7     */
8    /* op vAA, vBB, vCC */
9
10    FETCH(a0, 1)                           #  a0 <- CCBB
11    and       a2, a0, 255                  #  a2 <- BB
12    srl       a3, a0, 8
13    GET_VREG_F(ft0, a2)
14    GET_VREG_F(ft1, a3)
15#ifdef MIPS32REVGE6
16    cmp.eq.s  ft2, ft0, ft1
17    li        rTEMP, 0
18    bc1nez    ft2, 1f                      # done if vBB == vCC (ordered)
19    .if $gt_bias
20    cmp.lt.s  ft2, ft0, ft1
21    li        rTEMP, -1
22    bc1nez    ft2, 1f                      # done if vBB < vCC (ordered)
23    li        rTEMP, 1                     # vBB > vCC or unordered
24    .else
25    cmp.lt.s  ft2, ft1, ft0
26    li        rTEMP, 1
27    bc1nez    ft2, 1f                      # done if vBB > vCC (ordered)
28    li        rTEMP, -1                    # vBB < vCC or unordered
29    .endif
30#else
31    c.eq.s    fcc0, ft0, ft1
32    li        rTEMP, 0
33    bc1t      fcc0, 1f                     # done if vBB == vCC (ordered)
34    .if $gt_bias
35    c.olt.s   fcc0, ft0, ft1
36    li        rTEMP, -1
37    bc1t      fcc0, 1f                     # done if vBB < vCC (ordered)
38    li        rTEMP, 1                     # vBB > vCC or unordered
39    .else
40    c.olt.s   fcc0, ft1, ft0
41    li        rTEMP, 1
42    bc1t      fcc0, 1f                     # done if vBB > vCC (ordered)
43    li        rTEMP, -1                    # vBB < vCC or unordered
44    .endif
45#endif
461:
47    GET_OPA(rOBJ)
48    FETCH_ADVANCE_INST(2)                  #  advance rPC, load rINST
49    GET_INST_OPCODE(t0)                    #  extract opcode from rINST
50    SET_VREG_GOTO(rTEMP, rOBJ, t0)         #  vAA <- rTEMP
51