1 /*
2  * Mesa 3-D graphics library
3  *
4  * Copyright (C) 1999-2008  Brian Paul   All Rights Reserved.
5  * Copyright (C) 1999-2009  VMware, Inc.  All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the "Software"),
9  * to deal in the Software without restriction, including without limitation
10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11  * and/or sell copies of the Software, and to permit persons to whom the
12  * Software is furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included
15  * in all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23  * OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 
27 #include "main/glheader.h"
28 #include "main/imports.h"
29 #include "main/mtypes.h"
30 #include "prog_instruction.h"
31 
32 
33 /**
34  * Initialize program instruction fields to defaults.
35  * \param inst  first instruction to initialize
36  * \param count  number of instructions to initialize
37  */
38 void
_mesa_init_instructions(struct prog_instruction * inst,GLuint count)39 _mesa_init_instructions(struct prog_instruction *inst, GLuint count)
40 {
41    GLuint i;
42 
43    memset(inst, 0, count * sizeof(struct prog_instruction));
44 
45    for (i = 0; i < count; i++) {
46       inst[i].SrcReg[0].File = PROGRAM_UNDEFINED;
47       inst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
48       inst[i].SrcReg[1].File = PROGRAM_UNDEFINED;
49       inst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
50       inst[i].SrcReg[2].File = PROGRAM_UNDEFINED;
51       inst[i].SrcReg[2].Swizzle = SWIZZLE_NOOP;
52 
53       inst[i].DstReg.File = PROGRAM_UNDEFINED;
54       inst[i].DstReg.WriteMask = WRITEMASK_XYZW;
55 
56       inst[i].Saturate = GL_FALSE;
57    }
58 }
59 
60 
61 /**
62  * Copy an array of program instructions.
63  * \param dest  pointer to destination.
64  * \param src  pointer to source.
65  * \param n  number of instructions to copy.
66  * \return pointer to destination.
67  */
68 struct prog_instruction *
_mesa_copy_instructions(struct prog_instruction * dest,const struct prog_instruction * src,GLuint n)69 _mesa_copy_instructions(struct prog_instruction *dest,
70                         const struct prog_instruction *src, GLuint n)
71 {
72    memcpy(dest, src, n * sizeof(struct prog_instruction));
73    return dest;
74 }
75 
76 
77 /**
78  * Basic info about each instruction
79  */
80 struct instruction_info
81 {
82    enum prog_opcode Opcode;
83    const char *Name;
84    GLuint NumSrcRegs;
85    GLuint NumDstRegs;
86 };
87 
88 /**
89  * Instruction info
90  * \note Opcode should equal array index!
91  */
92 static const struct instruction_info InstInfo[MAX_OPCODE] = {
93    { OPCODE_NOP,    "NOP",     0, 0 },
94    { OPCODE_ABS,    "ABS",     1, 1 },
95    { OPCODE_ADD,    "ADD",     2, 1 },
96    { OPCODE_ARL,    "ARL",     1, 1 },
97    { OPCODE_BGNLOOP,"BGNLOOP", 0, 0 },
98    { OPCODE_BGNSUB, "BGNSUB",  0, 0 },
99    { OPCODE_BRK,    "BRK",     0, 0 },
100    { OPCODE_CAL,    "CAL",     0, 0 },
101    { OPCODE_CMP,    "CMP",     3, 1 },
102    { OPCODE_CONT,   "CONT",    0, 0 },
103    { OPCODE_COS,    "COS",     1, 1 },
104    { OPCODE_DDX,    "DDX",     1, 1 },
105    { OPCODE_DDY,    "DDY",     1, 1 },
106    { OPCODE_DP2,    "DP2",     2, 1 },
107    { OPCODE_DP3,    "DP3",     2, 1 },
108    { OPCODE_DP4,    "DP4",     2, 1 },
109    { OPCODE_DPH,    "DPH",     2, 1 },
110    { OPCODE_DST,    "DST",     2, 1 },
111    { OPCODE_ELSE,   "ELSE",    0, 0 },
112    { OPCODE_END,    "END",     0, 0 },
113    { OPCODE_ENDIF,  "ENDIF",   0, 0 },
114    { OPCODE_ENDLOOP,"ENDLOOP", 0, 0 },
115    { OPCODE_ENDSUB, "ENDSUB",  0, 0 },
116    { OPCODE_EX2,    "EX2",     1, 1 },
117    { OPCODE_EXP,    "EXP",     1, 1 },
118    { OPCODE_FLR,    "FLR",     1, 1 },
119    { OPCODE_FRC,    "FRC",     1, 1 },
120    { OPCODE_IF,     "IF",      1, 0 },
121    { OPCODE_KIL,    "KIL",     1, 0 },
122    { OPCODE_LG2,    "LG2",     1, 1 },
123    { OPCODE_LIT,    "LIT",     1, 1 },
124    { OPCODE_LOG,    "LOG",     1, 1 },
125    { OPCODE_LRP,    "LRP",     3, 1 },
126    { OPCODE_MAD,    "MAD",     3, 1 },
127    { OPCODE_MAX,    "MAX",     2, 1 },
128    { OPCODE_MIN,    "MIN",     2, 1 },
129    { OPCODE_MOV,    "MOV",     1, 1 },
130    { OPCODE_MUL,    "MUL",     2, 1 },
131    { OPCODE_NOISE1, "NOISE1",  1, 1 },
132    { OPCODE_NOISE2, "NOISE2",  1, 1 },
133    { OPCODE_NOISE3, "NOISE3",  1, 1 },
134    { OPCODE_NOISE4, "NOISE4",  1, 1 },
135    { OPCODE_POW,    "POW",     2, 1 },
136    { OPCODE_RCP,    "RCP",     1, 1 },
137    { OPCODE_RET,    "RET",     0, 0 },
138    { OPCODE_RSQ,    "RSQ",     1, 1 },
139    { OPCODE_SCS,    "SCS",     1, 1 },
140    { OPCODE_SGE,    "SGE",     2, 1 },
141    { OPCODE_SIN,    "SIN",     1, 1 },
142    { OPCODE_SLT,    "SLT",     2, 1 },
143    { OPCODE_SSG,    "SSG",     1, 1 },
144    { OPCODE_SUB,    "SUB",     2, 1 },
145    { OPCODE_SWZ,    "SWZ",     1, 1 },
146    { OPCODE_TEX,    "TEX",     1, 1 },
147    { OPCODE_TXB,    "TXB",     1, 1 },
148    { OPCODE_TXD,    "TXD",     3, 1 },
149    { OPCODE_TXL,    "TXL",     1, 1 },
150    { OPCODE_TXP,    "TXP",     1, 1 },
151    { OPCODE_TRUNC,  "TRUNC",   1, 1 },
152    { OPCODE_XPD,    "XPD",     2, 1 }
153 };
154 
155 
156 /**
157  * Return the number of src registers for the given instruction/opcode.
158  */
159 GLuint
_mesa_num_inst_src_regs(enum prog_opcode opcode)160 _mesa_num_inst_src_regs(enum prog_opcode opcode)
161 {
162    assert(opcode < MAX_OPCODE);
163    assert(opcode == InstInfo[opcode].Opcode);
164    assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
165    return InstInfo[opcode].NumSrcRegs;
166 }
167 
168 
169 /**
170  * Return the number of dst registers for the given instruction/opcode.
171  */
172 GLuint
_mesa_num_inst_dst_regs(enum prog_opcode opcode)173 _mesa_num_inst_dst_regs(enum prog_opcode opcode)
174 {
175    assert(opcode < MAX_OPCODE);
176    assert(opcode == InstInfo[opcode].Opcode);
177    assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
178    return InstInfo[opcode].NumDstRegs;
179 }
180 
181 
182 GLboolean
_mesa_is_tex_instruction(enum prog_opcode opcode)183 _mesa_is_tex_instruction(enum prog_opcode opcode)
184 {
185    return (opcode == OPCODE_TEX ||
186            opcode == OPCODE_TXB ||
187            opcode == OPCODE_TXD ||
188            opcode == OPCODE_TXL ||
189            opcode == OPCODE_TXP);
190 }
191 
192 
193 /**
194  * Check if there's a potential src/dst register data dependency when
195  * using SOA execution.
196  * Example:
197  *   MOV T, T.yxwz;
198  * This would expand into:
199  *   MOV t0, t1;
200  *   MOV t1, t0;
201  *   MOV t2, t3;
202  *   MOV t3, t2;
203  * The second instruction will have the wrong value for t0 if executed as-is.
204  */
205 GLboolean
_mesa_check_soa_dependencies(const struct prog_instruction * inst)206 _mesa_check_soa_dependencies(const struct prog_instruction *inst)
207 {
208    GLuint i, chan;
209 
210    if (inst->DstReg.WriteMask == WRITEMASK_X ||
211        inst->DstReg.WriteMask == WRITEMASK_Y ||
212        inst->DstReg.WriteMask == WRITEMASK_Z ||
213        inst->DstReg.WriteMask == WRITEMASK_W ||
214        inst->DstReg.WriteMask == 0x0) {
215       /* no chance of data dependency */
216       return GL_FALSE;
217    }
218 
219    /* loop over src regs */
220    for (i = 0; i < 3; i++) {
221       if (inst->SrcReg[i].File == inst->DstReg.File &&
222           inst->SrcReg[i].Index == inst->DstReg.Index) {
223          /* loop over dest channels */
224          GLuint channelsWritten = 0x0;
225          for (chan = 0; chan < 4; chan++) {
226             if (inst->DstReg.WriteMask & (1 << chan)) {
227                /* check if we're reading a channel that's been written */
228                GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
229                if (swizzle <= SWIZZLE_W &&
230                    (channelsWritten & (1 << swizzle))) {
231                   return GL_TRUE;
232                }
233 
234                channelsWritten |= (1 << chan);
235             }
236          }
237       }
238    }
239    return GL_FALSE;
240 }
241 
242 
243 /**
244  * Return string name for given program opcode.
245  */
246 const char *
_mesa_opcode_string(enum prog_opcode opcode)247 _mesa_opcode_string(enum prog_opcode opcode)
248 {
249    if (opcode < MAX_OPCODE)
250       return InstInfo[opcode].Name;
251    else {
252       static char s[20];
253       _mesa_snprintf(s, sizeof(s), "OP%u", opcode);
254       return s;
255    }
256 }
257 
258