1 /*
2 * Copyright © 2009 Corbin Simpson
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26 /*
27 * Authors:
28 * Corbin Simpson <MostAwesomeDude@gmail.com>
29 */
30 #ifndef RADEON_DRM_WINSYS_H
31 #define RADEON_DRM_WINSYS_H
32
33 #include "gallium/drivers/radeon/radeon_winsys.h"
34 #include "pipebuffer/pb_cache.h"
35 #include "pipebuffer/pb_slab.h"
36 #include "util/u_queue.h"
37 #include "util/list.h"
38 #include <radeon_drm.h>
39
40 #ifndef DRM_RADEON_GEM_USERPTR
41
42 #define DRM_RADEON_GEM_USERPTR 0x2d
43
44 #define RADEON_GEM_USERPTR_READONLY (1 << 0)
45 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
46 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
47 #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
48
49 struct drm_radeon_gem_userptr {
50 uint64_t addr;
51 uint64_t size;
52 uint32_t flags;
53 uint32_t handle;
54 };
55
56 #endif
57
58 struct radeon_drm_cs;
59
60 enum radeon_generation {
61 DRV_R300,
62 DRV_R600,
63 DRV_SI
64 };
65
66 #define RADEON_SLAB_MIN_SIZE_LOG2 9
67 #define RADEON_SLAB_MAX_SIZE_LOG2 14
68
69 struct radeon_drm_winsys {
70 struct radeon_winsys base;
71 struct pipe_reference reference;
72 struct pb_cache bo_cache;
73 struct pb_slabs bo_slabs;
74
75 int fd; /* DRM file descriptor */
76 int num_cs; /* The number of command streams created. */
77 uint64_t allocated_vram;
78 uint64_t allocated_gtt;
79 uint64_t mapped_vram;
80 uint64_t mapped_gtt;
81 uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
82 uint64_t num_gfx_IBs;
83 uint64_t num_sdma_IBs;
84 uint32_t next_bo_hash;
85
86 enum radeon_generation gen;
87 struct radeon_info info;
88 uint32_t va_start;
89 uint32_t va_unmap_working;
90 uint32_t accel_working2;
91
92 /* List of buffer GEM names. Protected by bo_handles_mutex. */
93 struct util_hash_table *bo_names;
94 /* List of buffer handles. Protectded by bo_handles_mutex. */
95 struct util_hash_table *bo_handles;
96 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
97 struct util_hash_table *bo_vas;
98 pipe_mutex bo_handles_mutex;
99 pipe_mutex bo_va_mutex;
100 pipe_mutex bo_fence_lock;
101
102 uint64_t va_offset;
103 struct list_head va_holes;
104 bool check_vm;
105
106 struct radeon_surface_manager *surf_man;
107
108 uint32_t num_cpus; /* Number of CPUs. */
109
110 struct radeon_drm_cs *hyperz_owner;
111 pipe_mutex hyperz_owner_mutex;
112 struct radeon_drm_cs *cmask_owner;
113 pipe_mutex cmask_owner_mutex;
114
115 /* multithreaded command submission */
116 struct util_queue cs_queue;
117 };
118
119 static inline struct radeon_drm_winsys *
radeon_drm_winsys(struct radeon_winsys * base)120 radeon_drm_winsys(struct radeon_winsys *base)
121 {
122 return (struct radeon_drm_winsys*)base;
123 }
124
125 void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
126
127 #endif
128