1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2    Copyright (C) 2003-2016 Free Software Foundation, Inc.
3 
4    This file is part of GAS, the GNU Assembler.
5 
6    GAS is free software; you can redistribute it and/or modify
7    it under the terms of the GNU General Public License as published by
8    the Free Software Foundation; either version 3, or (at your option)
9    any later version.
10 
11    GAS is distributed in the hope that it will be useful,
12    but WITHOUT ANY WARRANTY; without even the implied warranty of
13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14    GNU General Public License for more details.
15 
16    You should have received a copy of the GNU General Public License
17    along with GAS; see the file COPYING.  If not, write to
18    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19    MA 02110-1301, USA.  */
20 
21 #include "as.h"
22 #include <limits.h>
23 #include "sb.h"
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
26 #include "subsegs.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
32 #include "elf/xtensa.h"
33 
34 /* Provide default values for new configuration settings.  */
35 #ifndef XSHAL_ABI
36 #define XSHAL_ABI 0
37 #endif
38 
39 #ifndef uint32
40 #define uint32 unsigned int
41 #endif
42 #ifndef int32
43 #define int32 signed int
44 #endif
45 
46 /* Notes:
47 
48    Naming conventions (used somewhat inconsistently):
49       The xtensa_ functions are exported
50       The xg_ functions are internal
51 
52    We also have a couple of different extensibility mechanisms.
53    1) The idiom replacement:
54       This is used when a line is first parsed to
55       replace an instruction pattern with another instruction
56       It is currently limited to replacements of instructions
57       with constant operands.
58    2) The xtensa-relax.c mechanism that has stronger instruction
59       replacement patterns.  When an instruction's immediate field
60       does not fit the next instruction sequence is attempted.
61       In addition, "narrow" opcodes are supported this way.  */
62 
63 
64 /* Define characters with special meanings to GAS.  */
65 const char comment_chars[] = "#";
66 const char line_comment_chars[] = "#";
67 const char line_separator_chars[] = ";";
68 const char EXP_CHARS[] = "eE";
69 const char FLT_CHARS[] = "rRsSfFdDxXpP";
70 
71 
72 /* Flags to indicate whether the hardware supports the density and
73    absolute literals options.  */
74 
75 bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
76 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
77 
78 static vliw_insn cur_vinsn;
79 
80 unsigned xtensa_num_pipe_stages;
81 unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
82 
83 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
84 
85 /* Some functions are only valid in the front end.  This variable
86    allows us to assert that we haven't crossed over into the
87    back end.  */
88 static bfd_boolean past_xtensa_end = FALSE;
89 
90 /* Flags for properties of the last instruction in a segment.  */
91 #define FLAG_IS_A0_WRITER	0x1
92 #define FLAG_IS_BAD_LOOPEND	0x2
93 
94 
95 /* We define a special segment names ".literal" to place literals
96    into.  The .fini and .init sections are special because they
97    contain code that is moved together by the linker.  We give them
98    their own special .fini.literal and .init.literal sections.  */
99 
100 #define LITERAL_SECTION_NAME		xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME		xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME		xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME		xtensa_section_rename (".fini")
104 
105 
106 /* This type is used for the directive_stack to keep track of the
107    state of the literal collection pools.  If lit_prefix is set, it is
108    used to determine the literal section names; otherwise, the literal
109    sections are determined based on the current text section.  The
110    lit_seg and lit4_seg fields cache these literal sections, with the
111    current_text_seg field used a tag to indicate whether the cached
112    values are valid.  */
113 
114 typedef struct lit_state_struct
115 {
116   char *lit_prefix;
117   segT current_text_seg;
118   segT lit_seg;
119   segT lit4_seg;
120 } lit_state;
121 
122 static lit_state default_lit_sections;
123 
124 
125 /* We keep a list of literal segments.  The seg_list type is the node
126    for this list.  The literal_head pointer is the head of the list,
127    with the literal_head_h dummy node at the start.  */
128 
129 typedef struct seg_list_struct
130 {
131   struct seg_list_struct *next;
132   segT seg;
133 } seg_list;
134 
135 static seg_list literal_head_h;
136 static seg_list *literal_head = &literal_head_h;
137 
138 
139 /* Lists of symbols.  We keep a list of symbols that label the current
140    instruction, so that we can adjust the symbols when inserting alignment
141    for various instructions.  We also keep a list of all the symbols on
142    literals, so that we can fix up those symbols when the literals are
143    later moved into the text sections.  */
144 
145 typedef struct sym_list_struct
146 {
147   struct sym_list_struct *next;
148   symbolS *sym;
149 } sym_list;
150 
151 static sym_list *insn_labels = NULL;
152 static sym_list *free_insn_labels = NULL;
153 static sym_list *saved_insn_labels = NULL;
154 
155 static sym_list *literal_syms;
156 
157 
158 /* Flags to determine whether to prefer const16 or l32r
159    if both options are available.  */
160 int prefer_const16 = 0;
161 int prefer_l32r = 0;
162 
163 /* Global flag to indicate when we are emitting literals.  */
164 int generating_literals = 0;
165 
166 /* The following PROPERTY table definitions are copied from
167    <elf/xtensa.h> and must be kept in sync with the code there.  */
168 
169 /* Flags in the property tables to specify whether blocks of memory
170    are literals, instructions, data, or unreachable.  For
171    instructions, blocks that begin loop targets and branch targets are
172    designated.  Blocks that do not allow density, instruction
173    reordering or transformation are also specified.  Finally, for
174    branch targets, branch target alignment priority is included.
175    Alignment of the next block is specified in the current block
176    and the size of the current block does not include any fill required
177    to align to the next block.  */
178 
179 #define XTENSA_PROP_LITERAL		0x00000001
180 #define XTENSA_PROP_INSN		0x00000002
181 #define XTENSA_PROP_DATA		0x00000004
182 #define XTENSA_PROP_UNREACHABLE		0x00000008
183 /* Instruction only properties at beginning of code.  */
184 #define XTENSA_PROP_INSN_LOOP_TARGET	0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET	0x00000020
186 /* Instruction only properties about code.  */
187 #define XTENSA_PROP_INSN_NO_DENSITY	0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER	0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190    but it should apply to literals under certain circumstances.  */
191 #define XTENSA_PROP_NO_TRANSFORM	0x00000100
192 
193 /*  Branch target alignment information.  This transmits information
194     to the linker optimization about the priority of aligning a
195     particular block for branch target alignment: None, low priority,
196     high priority, or required.  These only need to be checked in
197     instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
198     Common usage is
199 
200     switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201     case XTENSA_PROP_BT_ALIGN_NONE:
202     case XTENSA_PROP_BT_ALIGN_LOW:
203     case XTENSA_PROP_BT_ALIGN_HIGH:
204     case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 */
206 #define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
207 
208 /* No branch target alignment.  */
209 #define XTENSA_PROP_BT_ALIGN_NONE       0x0
210 /* Low priority branch target alignment.  */
211 #define XTENSA_PROP_BT_ALIGN_LOW        0x1
212 /* High priority branch target alignment.  */
213 #define XTENSA_PROP_BT_ALIGN_HIGH       0x2
214 /* Required branch target alignment.  */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
216 
217 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
218   (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
219     (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
220 
221 
222 /* Alignment is specified in the block BEFORE the one that needs
223    alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
224    get the required alignment specified as a power of 2.  Use
225    SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
226    alignment.  Be careful of side effects since the SET will evaluate
227    flags twice.  Also, note that the SIZE of a block in the property
228    table does not include the alignment size, so the alignment fill
229    must be calculated to determine if two blocks are contiguous.
230    TEXT_ALIGN is not currently implemented but is a placeholder for a
231    possible future implementation.  */
232 
233 #define XTENSA_PROP_ALIGN		0x00000800
234 
235 #define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
236 
237 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
238   (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
239     (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
240 
241 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
242 
243 
244 /* Structure for saving instruction and alignment per-fragment data
245    that will be written to the object file.  This structure is
246    equivalent to the actual data that will be written out to the file
247    but is easier to use.   We provide a conversion to file flags
248    in frag_flags_to_number.  */
249 
250 typedef struct frag_flags_struct frag_flags;
251 
252 struct frag_flags_struct
253 {
254   /* is_literal should only be used after xtensa_move_literals.
255      If you need to check if you are generating a literal fragment,
256      then use the generating_literals global.  */
257 
258   unsigned is_literal : 1;
259   unsigned is_insn : 1;
260   unsigned is_data : 1;
261   unsigned is_unreachable : 1;
262 
263   /* is_specific_opcode implies no_transform.  */
264   unsigned is_no_transform : 1;
265 
266   struct
267   {
268     unsigned is_loop_target : 1;
269     unsigned is_branch_target : 1; /* Branch targets have a priority.  */
270     unsigned bt_align_priority : 2;
271 
272     unsigned is_no_density : 1;
273     /* no_longcalls flag does not need to be placed in the object file.  */
274 
275     unsigned is_no_reorder : 1;
276 
277     /* Uses absolute literal addressing for l32r.  */
278     unsigned is_abslit : 1;
279   } insn;
280   unsigned is_align : 1;
281   unsigned alignment : 5;
282 };
283 
284 
285 /* Structure for saving information about a block of property data
286    for frags that have the same flags.  */
287 struct xtensa_block_info_struct
288 {
289   segT sec;
290   bfd_vma offset;
291   size_t size;
292   frag_flags flags;
293   struct xtensa_block_info_struct *next;
294 };
295 
296 
297 /* Structure for saving the current state before emitting literals.  */
298 typedef struct emit_state_struct
299 {
300   const char *name;
301   segT now_seg;
302   subsegT now_subseg;
303   int generating_literals;
304 } emit_state;
305 
306 
307 /* Opcode placement information */
308 
309 typedef unsigned long long bitfield;
310 #define bit_is_set(bit, bf)	((bf) & (0x01ll << (bit)))
311 #define set_bit(bit, bf)	((bf) |= (0x01ll << (bit)))
312 #define clear_bit(bit, bf)	((bf) &= ~(0x01ll << (bit)))
313 
314 #define MAX_FORMATS 32
315 
316 typedef struct op_placement_info_struct
317 {
318   int num_formats;
319   /* A number describing how restrictive the issue is for this
320      opcode.  For example, an opcode that fits lots of different
321      formats has a high freedom, as does an opcode that fits
322      only one format but many slots in that format.  The most
323      restrictive is the opcode that fits only one slot in one
324      format.  */
325   int issuef;
326   xtensa_format narrowest;
327   char narrowest_size;
328   char narrowest_slot;
329 
330   /* formats is a bitfield with the Nth bit set
331      if the opcode fits in the Nth xtensa_format.  */
332   bitfield formats;
333 
334   /* slots[N]'s Mth bit is set if the op fits in the
335      Mth slot of the Nth xtensa_format.  */
336   bitfield slots[MAX_FORMATS];
337 
338   /* A count of the number of slots in a given format
339      an op can fit (i.e., the bitcount of the slot field above).  */
340   char slots_in_format[MAX_FORMATS];
341 
342 } op_placement_info, *op_placement_info_table;
343 
344 op_placement_info_table op_placement_table;
345 
346 
347 /* Extra expression types.  */
348 
349 #define O_pltrel	O_md1	/* like O_symbol but use a PLT reloc */
350 #define O_hi16		O_md2	/* use high 16 bits of symbolic value */
351 #define O_lo16		O_md3	/* use low 16 bits of symbolic value */
352 #define O_pcrel		O_md4	/* value is a PC-relative offset */
353 #define O_tlsfunc	O_md5	/* TLS_FUNC/TLSDESC_FN relocation */
354 #define O_tlsarg	O_md6	/* TLS_ARG/TLSDESC_ARG relocation */
355 #define O_tlscall	O_md7	/* TLS_CALL relocation */
356 #define O_tpoff		O_md8	/* TPOFF relocation */
357 #define O_dtpoff	O_md9	/* DTPOFF relocation */
358 
359 struct suffix_reloc_map
360 {
361   const char *suffix;
362   int length;
363   bfd_reloc_code_real_type reloc;
364   operatorT operator;
365 };
366 
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 
369 static struct suffix_reloc_map suffix_relocs[] =
370 {
371   SUFFIX_MAP ("l",	BFD_RELOC_LO16,			O_lo16),
372   SUFFIX_MAP ("h",	BFD_RELOC_HI16,			O_hi16),
373   SUFFIX_MAP ("plt",	BFD_RELOC_XTENSA_PLT,		O_pltrel),
374   SUFFIX_MAP ("pcrel",	BFD_RELOC_32_PCREL,		O_pcrel),
375   SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC,	O_tlsfunc),
376   SUFFIX_MAP ("tlsarg",	BFD_RELOC_XTENSA_TLS_ARG,	O_tlsarg),
377   SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL,	O_tlscall),
378   SUFFIX_MAP ("tpoff",	BFD_RELOC_XTENSA_TLS_TPOFF,	O_tpoff),
379   SUFFIX_MAP ("dtpoff",	BFD_RELOC_XTENSA_TLS_DTPOFF,	O_dtpoff),
380 };
381 
382 
383 /* Directives.  */
384 
385 typedef enum
386 {
387   directive_none = 0,
388   directive_literal,
389   directive_density,
390   directive_transform,
391   directive_freeregs,
392   directive_longcalls,
393   directive_literal_prefix,
394   directive_schedule,
395   directive_absolute_literals,
396   directive_last_directive
397 } directiveE;
398 
399 typedef struct
400 {
401   const char *name;
402   bfd_boolean can_be_negated;
403 } directive_infoS;
404 
405 const directive_infoS directive_info[] =
406 {
407   { "none",		FALSE },
408   { "literal",		FALSE },
409   { "density",		TRUE },
410   { "transform",	TRUE },
411   { "freeregs",		FALSE },
412   { "longcalls",	TRUE },
413   { "literal_prefix",	FALSE },
414   { "schedule",		TRUE },
415   { "absolute-literals", TRUE }
416 };
417 
418 bfd_boolean directive_state[] =
419 {
420   FALSE,			/* none */
421   FALSE,			/* literal */
422 #if !XCHAL_HAVE_DENSITY
423   FALSE,			/* density */
424 #else
425   TRUE,				/* density */
426 #endif
427   TRUE,				/* transform */
428   FALSE,			/* freeregs */
429   FALSE,			/* longcalls */
430   FALSE,			/* literal_prefix */
431   FALSE,			/* schedule */
432 #if XSHAL_USE_ABSOLUTE_LITERALS
433   TRUE				/* absolute_literals */
434 #else
435   FALSE				/* absolute_literals */
436 #endif
437 };
438 
439 /* A circular list of all potential and actual literal pool locations
440    in a segment.  */
441 struct litpool_frag
442 {
443   struct litpool_frag *next;
444   struct litpool_frag *prev;
445   fragS *fragP;
446   addressT addr;
447   short priority; /* 1, 2, or 3 -- 1 is highest  */
448   short original_priority;
449 };
450 
451 /* Map a segment to its litpool_frag list.  */
452 struct litpool_seg
453 {
454   struct litpool_seg *next;
455   asection *seg;
456   struct litpool_frag frag_list;
457   int frag_count; /* since last litpool location  */
458 };
459 
460 static struct litpool_seg litpool_seg_list;
461 
462 
463 /* Directive functions.  */
464 
465 static void xtensa_begin_directive (int);
466 static void xtensa_end_directive (int);
467 static void xtensa_literal_prefix (void);
468 static void xtensa_literal_position (int);
469 static void xtensa_literal_pseudo (int);
470 static void xtensa_frequency_pseudo (int);
471 static void xtensa_elf_cons (int);
472 static void xtensa_leb128 (int);
473 
474 /* Parsing and Idiom Translation.  */
475 
476 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
477 
478 /* Various Other Internal Functions.  */
479 
480 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
481 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
482 static void xtensa_mark_literal_pool_location (void);
483 static addressT get_expanded_loop_offset (xtensa_opcode);
484 static fragS *get_literal_pool_location (segT);
485 static void set_literal_pool_location (segT, fragS *);
486 static void xtensa_set_frag_assembly_state (fragS *);
487 static void finish_vinsn (vliw_insn *);
488 static bfd_boolean emit_single_op (TInsn *);
489 static int total_frag_text_expansion (fragS *);
490 static bfd_boolean use_trampolines = TRUE;
491 static void xtensa_check_frag_count (void);
492 static void xtensa_create_trampoline_frag (bfd_boolean);
493 static void xtensa_maybe_create_trampoline_frag (void);
494 struct trampoline_frag;
495 static int init_trampoline_frag (struct trampoline_frag *);
496 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean);
497 static bfd_boolean auto_litpools = FALSE;
498 static int auto_litpool_limit = 10000;
499 
500 /* Alignment Functions.  */
501 
502 static int get_text_align_power (unsigned);
503 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
504 static int branch_align_power (segT);
505 
506 /* Helpers for xtensa_relax_frag().  */
507 
508 static long relax_frag_add_nop (fragS *);
509 
510 /* Accessors for additional per-subsegment information.  */
511 
512 static unsigned get_last_insn_flags (segT, subsegT);
513 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
514 static float get_subseg_total_freq (segT, subsegT);
515 static float get_subseg_target_freq (segT, subsegT);
516 static void set_subseg_freq (segT, subsegT, float, float);
517 
518 /* Segment list functions.  */
519 
520 static void xtensa_move_literals (void);
521 static void xtensa_reorder_segments (void);
522 static void xtensa_switch_to_literal_fragment (emit_state *);
523 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
524 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
525 static void xtensa_restore_emit_state (emit_state *);
526 static segT cache_literal_section (bfd_boolean);
527 
528 /* op_placement_info functions.  */
529 
530 static void init_op_placement_info_table (void);
531 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
532 static int xg_get_single_size (xtensa_opcode);
533 static xtensa_format xg_get_single_format (xtensa_opcode);
534 static int xg_get_single_slot (xtensa_opcode);
535 
536 /* TInsn and IStack functions.  */
537 
538 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
539 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
540 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
541 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
542 static bfd_boolean tinsn_check_arguments (const TInsn *);
543 static void tinsn_from_chars (TInsn *, char *, int);
544 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
545 static int get_num_stack_text_bytes (IStack *);
546 static int get_num_stack_literal_bytes (IStack *);
547 static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf);
548 
549 /* vliw_insn functions.  */
550 
551 static void xg_init_vinsn (vliw_insn *);
552 static void xg_copy_vinsn (vliw_insn *, vliw_insn *);
553 static void xg_clear_vinsn (vliw_insn *);
554 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
555 static void xg_free_vinsn (vliw_insn *);
556 static bfd_boolean vinsn_to_insnbuf
557   (vliw_insn *, char *, fragS *, bfd_boolean);
558 static void vinsn_from_chars (vliw_insn *, char *);
559 
560 /* Expression Utilities.  */
561 
562 bfd_boolean expr_is_const (const expressionS *);
563 offsetT get_expr_const (const expressionS *);
564 void set_expr_const (expressionS *, offsetT);
565 bfd_boolean expr_is_register (const expressionS *);
566 offsetT get_expr_register (const expressionS *);
567 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
568 bfd_boolean expr_is_equal (expressionS *, expressionS *);
569 static void copy_expr (expressionS *, const expressionS *);
570 
571 /* Section renaming.  */
572 
573 static void build_section_rename (const char *);
574 
575 
576 /* ISA imported from bfd.  */
577 extern xtensa_isa xtensa_default_isa;
578 
579 extern int target_big_endian;
580 
581 static xtensa_opcode xtensa_addi_opcode;
582 static xtensa_opcode xtensa_addmi_opcode;
583 static xtensa_opcode xtensa_call0_opcode;
584 static xtensa_opcode xtensa_call4_opcode;
585 static xtensa_opcode xtensa_call8_opcode;
586 static xtensa_opcode xtensa_call12_opcode;
587 static xtensa_opcode xtensa_callx0_opcode;
588 static xtensa_opcode xtensa_callx4_opcode;
589 static xtensa_opcode xtensa_callx8_opcode;
590 static xtensa_opcode xtensa_callx12_opcode;
591 static xtensa_opcode xtensa_const16_opcode;
592 static xtensa_opcode xtensa_entry_opcode;
593 static xtensa_opcode xtensa_extui_opcode;
594 static xtensa_opcode xtensa_movi_opcode;
595 static xtensa_opcode xtensa_movi_n_opcode;
596 static xtensa_opcode xtensa_isync_opcode;
597 static xtensa_opcode xtensa_j_opcode;
598 static xtensa_opcode xtensa_jx_opcode;
599 static xtensa_opcode xtensa_l32r_opcode;
600 static xtensa_opcode xtensa_loop_opcode;
601 static xtensa_opcode xtensa_loopnez_opcode;
602 static xtensa_opcode xtensa_loopgtz_opcode;
603 static xtensa_opcode xtensa_nop_opcode;
604 static xtensa_opcode xtensa_nop_n_opcode;
605 static xtensa_opcode xtensa_or_opcode;
606 static xtensa_opcode xtensa_ret_opcode;
607 static xtensa_opcode xtensa_ret_n_opcode;
608 static xtensa_opcode xtensa_retw_opcode;
609 static xtensa_opcode xtensa_retw_n_opcode;
610 static xtensa_opcode xtensa_rsr_lcount_opcode;
611 static xtensa_opcode xtensa_waiti_opcode;
612 static int config_max_slots = 0;
613 
614 
615 /* Command-line Options.  */
616 
617 bfd_boolean use_literal_section = TRUE;
618 enum flix_level produce_flix = FLIX_ALL;
619 static bfd_boolean align_targets = TRUE;
620 static bfd_boolean warn_unaligned_branch_targets = FALSE;
621 static bfd_boolean has_a0_b_retw = FALSE;
622 static bfd_boolean workaround_a0_b_retw = FALSE;
623 static bfd_boolean workaround_b_j_loop_end = FALSE;
624 static bfd_boolean workaround_short_loop = FALSE;
625 static bfd_boolean maybe_has_short_loop = FALSE;
626 static bfd_boolean workaround_close_loop_end = FALSE;
627 static bfd_boolean maybe_has_close_loop_end = FALSE;
628 static bfd_boolean enforce_three_byte_loop_align = FALSE;
629 
630 /* When workaround_short_loops is TRUE, all loops with early exits must
631    have at least 3 instructions.  workaround_all_short_loops is a modifier
632    to the workaround_short_loop flag.  In addition to the
633    workaround_short_loop actions, all straightline loopgtz and loopnez
634    must have at least 3 instructions.  */
635 
636 static bfd_boolean workaround_all_short_loops = FALSE;
637 
638 
639 static void
xtensa_setup_hw_workarounds(int earliest,int latest)640 xtensa_setup_hw_workarounds (int earliest, int latest)
641 {
642   if (earliest > latest)
643     as_fatal (_("illegal range of target hardware versions"));
644 
645   /* Enable all workarounds for pre-T1050.0 hardware.  */
646   if (earliest < 105000 || latest < 105000)
647     {
648       workaround_a0_b_retw |= TRUE;
649       workaround_b_j_loop_end |= TRUE;
650       workaround_short_loop |= TRUE;
651       workaround_close_loop_end |= TRUE;
652       workaround_all_short_loops |= TRUE;
653       enforce_three_byte_loop_align = TRUE;
654     }
655 }
656 
657 
658 enum
659 {
660   option_density = OPTION_MD_BASE,
661   option_no_density,
662 
663   option_flix,
664   option_no_generate_flix,
665   option_no_flix,
666 
667   option_relax,
668   option_no_relax,
669 
670   option_link_relax,
671   option_no_link_relax,
672 
673   option_generics,
674   option_no_generics,
675 
676   option_transform,
677   option_no_transform,
678 
679   option_text_section_literals,
680   option_no_text_section_literals,
681 
682   option_absolute_literals,
683   option_no_absolute_literals,
684 
685   option_align_targets,
686   option_no_align_targets,
687 
688   option_warn_unaligned_targets,
689 
690   option_longcalls,
691   option_no_longcalls,
692 
693   option_workaround_a0_b_retw,
694   option_no_workaround_a0_b_retw,
695 
696   option_workaround_b_j_loop_end,
697   option_no_workaround_b_j_loop_end,
698 
699   option_workaround_short_loop,
700   option_no_workaround_short_loop,
701 
702   option_workaround_all_short_loops,
703   option_no_workaround_all_short_loops,
704 
705   option_workaround_close_loop_end,
706   option_no_workaround_close_loop_end,
707 
708   option_no_workarounds,
709 
710   option_rename_section_name,
711 
712   option_prefer_l32r,
713   option_prefer_const16,
714 
715   option_target_hardware,
716 
717   option_trampolines,
718   option_no_trampolines,
719 
720   option_auto_litpools,
721   option_no_auto_litpools,
722   option_auto_litpool_limit,
723 };
724 
725 const char *md_shortopts = "";
726 
727 struct option md_longopts[] =
728 {
729   { "density", no_argument, NULL, option_density },
730   { "no-density", no_argument, NULL, option_no_density },
731 
732   { "flix", no_argument, NULL, option_flix },
733   { "no-generate-flix", no_argument, NULL, option_no_generate_flix },
734   { "no-allow-flix", no_argument, NULL, option_no_flix },
735 
736   /* Both "relax" and "generics" are deprecated and treated as equivalent
737      to the "transform" option.  */
738   { "relax", no_argument, NULL, option_relax },
739   { "no-relax", no_argument, NULL, option_no_relax },
740   { "generics", no_argument, NULL, option_generics },
741   { "no-generics", no_argument, NULL, option_no_generics },
742 
743   { "transform", no_argument, NULL, option_transform },
744   { "no-transform", no_argument, NULL, option_no_transform },
745   { "text-section-literals", no_argument, NULL, option_text_section_literals },
746   { "no-text-section-literals", no_argument, NULL,
747     option_no_text_section_literals },
748   { "absolute-literals", no_argument, NULL, option_absolute_literals },
749   { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
750   /* This option was changed from -align-target to -target-align
751      because it conflicted with the "-al" option.  */
752   { "target-align", no_argument, NULL, option_align_targets },
753   { "no-target-align", no_argument, NULL, option_no_align_targets },
754   { "warn-unaligned-targets", no_argument, NULL,
755     option_warn_unaligned_targets },
756   { "longcalls", no_argument, NULL, option_longcalls },
757   { "no-longcalls", no_argument, NULL, option_no_longcalls },
758 
759   { "no-workaround-a0-b-retw", no_argument, NULL,
760     option_no_workaround_a0_b_retw },
761   { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
762 
763   { "no-workaround-b-j-loop-end", no_argument, NULL,
764     option_no_workaround_b_j_loop_end },
765   { "workaround-b-j-loop-end", no_argument, NULL,
766     option_workaround_b_j_loop_end },
767 
768   { "no-workaround-short-loops", no_argument, NULL,
769     option_no_workaround_short_loop },
770   { "workaround-short-loops", no_argument, NULL,
771     option_workaround_short_loop },
772 
773   { "no-workaround-all-short-loops", no_argument, NULL,
774     option_no_workaround_all_short_loops },
775   { "workaround-all-short-loop", no_argument, NULL,
776     option_workaround_all_short_loops },
777 
778   { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
779   { "prefer-const16", no_argument, NULL, option_prefer_const16 },
780 
781   { "no-workarounds", no_argument, NULL, option_no_workarounds },
782 
783   { "no-workaround-close-loop-end", no_argument, NULL,
784     option_no_workaround_close_loop_end },
785   { "workaround-close-loop-end", no_argument, NULL,
786     option_workaround_close_loop_end },
787 
788   { "rename-section", required_argument, NULL, option_rename_section_name },
789 
790   { "link-relax", no_argument, NULL, option_link_relax },
791   { "no-link-relax", no_argument, NULL, option_no_link_relax },
792 
793   { "target-hardware", required_argument, NULL, option_target_hardware },
794 
795   { "trampolines", no_argument, NULL, option_trampolines },
796   { "no-trampolines", no_argument, NULL, option_no_trampolines },
797 
798   { "auto-litpools", no_argument, NULL, option_auto_litpools },
799   { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools },
800   { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit },
801 
802   { NULL, no_argument, NULL, 0 }
803 };
804 
805 size_t md_longopts_size = sizeof md_longopts;
806 
807 
808 int
md_parse_option(int c,const char * arg)809 md_parse_option (int c, const char *arg)
810 {
811   switch (c)
812     {
813     case option_density:
814       as_warn (_("--density option is ignored"));
815       return 1;
816     case option_no_density:
817       as_warn (_("--no-density option is ignored"));
818       return 1;
819     case option_link_relax:
820       linkrelax = 1;
821       return 1;
822     case option_no_link_relax:
823       linkrelax = 0;
824       return 1;
825     case option_flix:
826       produce_flix = FLIX_ALL;
827       return 1;
828     case option_no_generate_flix:
829       produce_flix = FLIX_NO_GENERATE;
830       return 1;
831     case option_no_flix:
832       produce_flix = FLIX_NONE;
833       return 1;
834     case option_generics:
835       as_warn (_("--generics is deprecated; use --transform instead"));
836       return md_parse_option (option_transform, arg);
837     case option_no_generics:
838       as_warn (_("--no-generics is deprecated; use --no-transform instead"));
839       return md_parse_option (option_no_transform, arg);
840     case option_relax:
841       as_warn (_("--relax is deprecated; use --transform instead"));
842       return md_parse_option (option_transform, arg);
843     case option_no_relax:
844       as_warn (_("--no-relax is deprecated; use --no-transform instead"));
845       return md_parse_option (option_no_transform, arg);
846     case option_longcalls:
847       directive_state[directive_longcalls] = TRUE;
848       return 1;
849     case option_no_longcalls:
850       directive_state[directive_longcalls] = FALSE;
851       return 1;
852     case option_text_section_literals:
853       use_literal_section = FALSE;
854       return 1;
855     case option_no_text_section_literals:
856       use_literal_section = TRUE;
857       return 1;
858     case option_absolute_literals:
859       if (!absolute_literals_supported)
860 	{
861 	  as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
862 	  return 0;
863 	}
864       directive_state[directive_absolute_literals] = TRUE;
865       return 1;
866     case option_no_absolute_literals:
867       directive_state[directive_absolute_literals] = FALSE;
868       return 1;
869 
870     case option_workaround_a0_b_retw:
871       workaround_a0_b_retw = TRUE;
872       return 1;
873     case option_no_workaround_a0_b_retw:
874       workaround_a0_b_retw = FALSE;
875       return 1;
876     case option_workaround_b_j_loop_end:
877       workaround_b_j_loop_end = TRUE;
878       return 1;
879     case option_no_workaround_b_j_loop_end:
880       workaround_b_j_loop_end = FALSE;
881       return 1;
882 
883     case option_workaround_short_loop:
884       workaround_short_loop = TRUE;
885       return 1;
886     case option_no_workaround_short_loop:
887       workaround_short_loop = FALSE;
888       return 1;
889 
890     case option_workaround_all_short_loops:
891       workaround_all_short_loops = TRUE;
892       return 1;
893     case option_no_workaround_all_short_loops:
894       workaround_all_short_loops = FALSE;
895       return 1;
896 
897     case option_workaround_close_loop_end:
898       workaround_close_loop_end = TRUE;
899       return 1;
900     case option_no_workaround_close_loop_end:
901       workaround_close_loop_end = FALSE;
902       return 1;
903 
904     case option_no_workarounds:
905       workaround_a0_b_retw = FALSE;
906       workaround_b_j_loop_end = FALSE;
907       workaround_short_loop = FALSE;
908       workaround_all_short_loops = FALSE;
909       workaround_close_loop_end = FALSE;
910       return 1;
911 
912     case option_align_targets:
913       align_targets = TRUE;
914       return 1;
915     case option_no_align_targets:
916       align_targets = FALSE;
917       return 1;
918 
919     case option_warn_unaligned_targets:
920       warn_unaligned_branch_targets = TRUE;
921       return 1;
922 
923     case option_rename_section_name:
924       build_section_rename (arg);
925       return 1;
926 
927     case 'Q':
928       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
929          should be emitted or not.  FIXME: Not implemented.  */
930       return 1;
931 
932     case option_prefer_l32r:
933       if (prefer_const16)
934 	as_fatal (_("prefer-l32r conflicts with prefer-const16"));
935       prefer_l32r = 1;
936       return 1;
937 
938     case option_prefer_const16:
939       if (prefer_l32r)
940 	as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
941       prefer_const16 = 1;
942       return 1;
943 
944     case option_target_hardware:
945       {
946 	int earliest, latest = 0;
947 	char *end;
948 	if (*arg == 0 || *arg == '-')
949 	  as_fatal (_("invalid target hardware version"));
950 
951 	earliest = strtol (arg, &end, 0);
952 
953 	if (*end == 0)
954 	  latest = earliest;
955 	else if (*end == '-')
956 	  {
957 	    if (*++end == 0)
958 	      as_fatal (_("invalid target hardware version"));
959 	    latest = strtol (end, &end, 0);
960 	  }
961 	if (*end != 0)
962 	  as_fatal (_("invalid target hardware version"));
963 
964 	xtensa_setup_hw_workarounds (earliest, latest);
965 	return 1;
966       }
967 
968     case option_transform:
969       /* This option has no affect other than to use the defaults,
970 	 which are already set.  */
971       return 1;
972 
973     case option_no_transform:
974       /* This option turns off all transformations of any kind.
975 	 However, because we want to preserve the state of other
976 	 directives, we only change its own field.  Thus, before
977 	 you perform any transformation, always check if transform
978 	 is available.  If you use the functions we provide for this
979 	 purpose, you will be ok.  */
980       directive_state[directive_transform] = FALSE;
981       return 1;
982 
983     case option_trampolines:
984       use_trampolines = TRUE;
985       return 1;
986 
987     case option_no_trampolines:
988       use_trampolines = FALSE;
989       return 1;
990 
991     case option_auto_litpools:
992       auto_litpools = TRUE;
993       use_literal_section = FALSE;
994       return 1;
995 
996     case option_no_auto_litpools:
997       auto_litpools = FALSE;
998       auto_litpool_limit = -1;
999       return 1;
1000 
1001     case option_auto_litpool_limit:
1002       {
1003 	int value = 0;
1004 	char *end;
1005 	if (auto_litpool_limit < 0)
1006 	  as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1007 	if (*arg == 0 || *arg == '-')
1008 	  as_fatal (_("invalid auto-litpool-limit argument"));
1009 	value = strtol (arg, &end, 10);
1010 	if (*end != 0)
1011 	  as_fatal (_("invalid auto-litpool-limit argument"));
1012 	if (value < 100 || value > 10000)
1013 	  as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1014 	auto_litpool_limit = value;
1015 	auto_litpools = TRUE;
1016 	use_literal_section = FALSE;
1017 	return 1;
1018       }
1019 
1020     default:
1021       return 0;
1022     }
1023 }
1024 
1025 
1026 void
md_show_usage(FILE * stream)1027 md_show_usage (FILE *stream)
1028 {
1029   fputs ("\n\
1030 Xtensa options:\n\
1031   --[no-]text-section-literals\n\
1032                           [Do not] put literals in the text section\n\
1033   --[no-]absolute-literals\n\
1034                           [Do not] default to use non-PC-relative literals\n\
1035   --[no-]target-align     [Do not] try to align branch targets\n\
1036   --[no-]longcalls        [Do not] emit 32-bit call sequences\n\
1037   --[no-]transform        [Do not] transform instructions\n\
1038   --flix                  both allow hand-written and generate flix bundles\n\
1039   --no-generate-flix      allow hand-written but do not generate\n\
1040                           flix bundles\n\
1041   --no-allow-flix         neither allow hand-written nor generate\n\
1042                           flix bundles\n\
1043   --rename-section old=new Rename section 'old' to 'new'\n\
1044   --[no-]trampolines      [Do not] generate trampolines (jumps to jumps)\n\
1045                           when jumps do not reach their targets\n\
1046   --[no-]auto-litpools    [Do not] automatically create literal pools\n\
1047   --auto-litpool-limit=<value>\n\
1048                           (range 100-10000) Maximum number of blocks of\n\
1049                           instructions to emit between literal pool\n\
1050                           locations; implies --auto-litpools flag\n", stream);
1051 }
1052 
1053 
1054 /* Functions related to the list of current label symbols.  */
1055 
1056 static void
xtensa_add_insn_label(symbolS * sym)1057 xtensa_add_insn_label (symbolS *sym)
1058 {
1059   sym_list *l;
1060 
1061   if (!free_insn_labels)
1062     l = XNEW (sym_list);
1063   else
1064     {
1065       l = free_insn_labels;
1066       free_insn_labels = l->next;
1067     }
1068 
1069   l->sym = sym;
1070   l->next = insn_labels;
1071   insn_labels = l;
1072 }
1073 
1074 
1075 static void
xtensa_clear_insn_labels(void)1076 xtensa_clear_insn_labels (void)
1077 {
1078   sym_list **pl;
1079 
1080   for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1081     ;
1082   *pl = insn_labels;
1083   insn_labels = NULL;
1084 }
1085 
1086 
1087 static void
xtensa_move_labels(fragS * new_frag,valueT new_offset)1088 xtensa_move_labels (fragS *new_frag, valueT new_offset)
1089 {
1090   sym_list *lit;
1091 
1092   for (lit = insn_labels; lit; lit = lit->next)
1093     {
1094       symbolS *lit_sym = lit->sym;
1095       S_SET_VALUE (lit_sym, new_offset);
1096       symbol_set_frag (lit_sym, new_frag);
1097     }
1098 }
1099 
1100 
1101 /* Directive data and functions.  */
1102 
1103 typedef struct state_stackS_struct
1104 {
1105   directiveE directive;
1106   bfd_boolean negated;
1107   bfd_boolean old_state;
1108   const char *file;
1109   unsigned int line;
1110   const void *datum;
1111   struct state_stackS_struct *prev;
1112 } state_stackS;
1113 
1114 state_stackS *directive_state_stack;
1115 
1116 const pseudo_typeS md_pseudo_table[] =
1117 {
1118   { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
1119   { "literal_position", xtensa_literal_position, 0 },
1120   { "frame", s_ignore, 0 },	/* Formerly used for STABS debugging.  */
1121   { "long", xtensa_elf_cons, 4 },
1122   { "word", xtensa_elf_cons, 4 },
1123   { "4byte", xtensa_elf_cons, 4 },
1124   { "short", xtensa_elf_cons, 2 },
1125   { "2byte", xtensa_elf_cons, 2 },
1126   { "sleb128", xtensa_leb128, 1},
1127   { "uleb128", xtensa_leb128, 0},
1128   { "begin", xtensa_begin_directive, 0 },
1129   { "end", xtensa_end_directive, 0 },
1130   { "literal", xtensa_literal_pseudo, 0 },
1131   { "frequency", xtensa_frequency_pseudo, 0 },
1132   { NULL, 0, 0 },
1133 };
1134 
1135 
1136 static bfd_boolean
use_transform(void)1137 use_transform (void)
1138 {
1139   /* After md_end, you should be checking frag by frag, rather
1140      than state directives.  */
1141   gas_assert (!past_xtensa_end);
1142   return directive_state[directive_transform];
1143 }
1144 
1145 
1146 static bfd_boolean
do_align_targets(void)1147 do_align_targets (void)
1148 {
1149   /* Do not use this function after md_end; just look at align_targets
1150      instead.  There is no target-align directive, so alignment is either
1151      enabled for all frags or not done at all.  */
1152   gas_assert (!past_xtensa_end);
1153   return align_targets && use_transform ();
1154 }
1155 
1156 
1157 static void
directive_push(directiveE directive,bfd_boolean negated,const void * datum)1158 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1159 {
1160   const char *file;
1161   unsigned int line;
1162   state_stackS *stack = XNEW (state_stackS);
1163 
1164   file = as_where (&line);
1165 
1166   stack->directive = directive;
1167   stack->negated = negated;
1168   stack->old_state = directive_state[directive];
1169   stack->file = file;
1170   stack->line = line;
1171   stack->datum = datum;
1172   stack->prev = directive_state_stack;
1173   directive_state_stack = stack;
1174 
1175   directive_state[directive] = !negated;
1176 }
1177 
1178 
1179 static void
directive_pop(directiveE * directive,bfd_boolean * negated,const char ** file,unsigned int * line,const void ** datum)1180 directive_pop (directiveE *directive,
1181 	       bfd_boolean *negated,
1182 	       const char **file,
1183 	       unsigned int *line,
1184 	       const void **datum)
1185 {
1186   state_stackS *top = directive_state_stack;
1187 
1188   if (!directive_state_stack)
1189     {
1190       as_bad (_("unmatched end directive"));
1191       *directive = directive_none;
1192       return;
1193     }
1194 
1195   directive_state[directive_state_stack->directive] = top->old_state;
1196   *directive = top->directive;
1197   *negated = top->negated;
1198   *file = top->file;
1199   *line = top->line;
1200   *datum = top->datum;
1201   directive_state_stack = top->prev;
1202   free (top);
1203 }
1204 
1205 
1206 static void
directive_balance(void)1207 directive_balance (void)
1208 {
1209   while (directive_state_stack)
1210     {
1211       directiveE directive;
1212       bfd_boolean negated;
1213       const char *file;
1214       unsigned int line;
1215       const void *datum;
1216 
1217       directive_pop (&directive, &negated, &file, &line, &datum);
1218       as_warn_where ((char *) file, line,
1219 		     _(".begin directive with no matching .end directive"));
1220     }
1221 }
1222 
1223 
1224 static bfd_boolean
inside_directive(directiveE dir)1225 inside_directive (directiveE dir)
1226 {
1227   state_stackS *top = directive_state_stack;
1228 
1229   while (top && top->directive != dir)
1230     top = top->prev;
1231 
1232   return (top != NULL);
1233 }
1234 
1235 
1236 static void
get_directive(directiveE * directive,bfd_boolean * negated)1237 get_directive (directiveE *directive, bfd_boolean *negated)
1238 {
1239   int len;
1240   unsigned i;
1241   const char *directive_string;
1242 
1243   if (strncmp (input_line_pointer, "no-", 3) != 0)
1244     *negated = FALSE;
1245   else
1246     {
1247       *negated = TRUE;
1248       input_line_pointer += 3;
1249     }
1250 
1251   len = strspn (input_line_pointer,
1252 		"abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1253 
1254   /* This code is a hack to make .begin [no-][generics|relax] exactly
1255      equivalent to .begin [no-]transform.  We should remove it when
1256      we stop accepting those options.  */
1257 
1258   if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1259     {
1260       as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1261       directive_string = "transform";
1262     }
1263   else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1264     {
1265       as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1266       directive_string = "transform";
1267     }
1268   else
1269     directive_string = input_line_pointer;
1270 
1271   for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1272     {
1273       if (strncmp (directive_string, directive_info[i].name, len) == 0)
1274 	{
1275 	  input_line_pointer += len;
1276 	  *directive = (directiveE) i;
1277 	  if (*negated && !directive_info[i].can_be_negated)
1278 	    as_bad (_("directive %s cannot be negated"),
1279 		    directive_info[i].name);
1280 	  return;
1281 	}
1282     }
1283 
1284   as_bad (_("unknown directive"));
1285   *directive = (directiveE) XTENSA_UNDEFINED;
1286 }
1287 
1288 
1289 static void
xtensa_begin_directive(int ignore ATTRIBUTE_UNUSED)1290 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1291 {
1292   directiveE directive;
1293   bfd_boolean negated;
1294   emit_state *state;
1295   lit_state *ls;
1296 
1297   get_directive (&directive, &negated);
1298   if (directive == (directiveE) XTENSA_UNDEFINED)
1299     {
1300       discard_rest_of_line ();
1301       return;
1302     }
1303 
1304   if (cur_vinsn.inside_bundle)
1305     as_bad (_("directives are not valid inside bundles"));
1306 
1307   switch (directive)
1308     {
1309     case directive_literal:
1310       if (!inside_directive (directive_literal))
1311 	{
1312 	  /* Previous labels go with whatever follows this directive, not with
1313 	     the literal, so save them now.  */
1314 	  saved_insn_labels = insn_labels;
1315 	  insn_labels = NULL;
1316 	}
1317       as_warn (_(".begin literal is deprecated; use .literal instead"));
1318       state = XNEW (emit_state);
1319       xtensa_switch_to_literal_fragment (state);
1320       directive_push (directive_literal, negated, state);
1321       break;
1322 
1323     case directive_literal_prefix:
1324       /* Have to flush pending output because a movi relaxed to an l32r
1325 	 might produce a literal.  */
1326       md_flush_pending_output ();
1327       /* Check to see if the current fragment is a literal
1328 	 fragment.  If it is, then this operation is not allowed.  */
1329       if (generating_literals)
1330 	{
1331 	  as_bad (_("cannot set literal_prefix inside literal fragment"));
1332 	  return;
1333 	}
1334 
1335       /* Allocate the literal state for this section and push
1336 	 onto the directive stack.  */
1337       ls = XNEW (lit_state);
1338       gas_assert (ls);
1339 
1340       *ls = default_lit_sections;
1341       directive_push (directive_literal_prefix, negated, ls);
1342 
1343       /* Process the new prefix.  */
1344       xtensa_literal_prefix ();
1345       break;
1346 
1347     case directive_freeregs:
1348       /* This information is currently unused, but we'll accept the statement
1349          and just discard the rest of the line.  This won't check the syntax,
1350          but it will accept every correct freeregs directive.  */
1351       input_line_pointer += strcspn (input_line_pointer, "\n");
1352       directive_push (directive_freeregs, negated, 0);
1353       break;
1354 
1355     case directive_schedule:
1356       md_flush_pending_output ();
1357       frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1358 		frag_now->fr_symbol, frag_now->fr_offset, NULL);
1359       directive_push (directive_schedule, negated, 0);
1360       xtensa_set_frag_assembly_state (frag_now);
1361       break;
1362 
1363     case directive_density:
1364       as_warn (_(".begin [no-]density is ignored"));
1365       break;
1366 
1367     case directive_absolute_literals:
1368       md_flush_pending_output ();
1369       if (!absolute_literals_supported && !negated)
1370 	{
1371 	  as_warn (_("Xtensa absolute literals option not supported; ignored"));
1372 	  break;
1373 	}
1374       xtensa_set_frag_assembly_state (frag_now);
1375       directive_push (directive, negated, 0);
1376       break;
1377 
1378     default:
1379       md_flush_pending_output ();
1380       xtensa_set_frag_assembly_state (frag_now);
1381       directive_push (directive, negated, 0);
1382       break;
1383     }
1384 
1385   demand_empty_rest_of_line ();
1386 }
1387 
1388 
1389 static void
xtensa_end_directive(int ignore ATTRIBUTE_UNUSED)1390 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1391 {
1392   directiveE begin_directive, end_directive;
1393   bfd_boolean begin_negated, end_negated;
1394   const char *file;
1395   unsigned int line;
1396   emit_state *state;
1397   emit_state **state_ptr;
1398   lit_state *s;
1399 
1400   if (cur_vinsn.inside_bundle)
1401     as_bad (_("directives are not valid inside bundles"));
1402 
1403   get_directive (&end_directive, &end_negated);
1404 
1405   md_flush_pending_output ();
1406 
1407   switch ((int) end_directive)
1408     {
1409     case XTENSA_UNDEFINED:
1410       discard_rest_of_line ();
1411       return;
1412 
1413     case (int) directive_density:
1414       as_warn (_(".end [no-]density is ignored"));
1415       demand_empty_rest_of_line ();
1416       break;
1417 
1418     case (int) directive_absolute_literals:
1419       if (!absolute_literals_supported && !end_negated)
1420 	{
1421 	  as_warn (_("Xtensa absolute literals option not supported; ignored"));
1422 	  demand_empty_rest_of_line ();
1423 	  return;
1424 	}
1425       break;
1426 
1427     default:
1428       break;
1429     }
1430 
1431   state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1432   directive_pop (&begin_directive, &begin_negated, &file, &line,
1433 		 (const void **) state_ptr);
1434 
1435   if (begin_directive != directive_none)
1436     {
1437       if (begin_directive != end_directive || begin_negated != end_negated)
1438 	{
1439 	  as_bad (_("does not match begin %s%s at %s:%d"),
1440 		  begin_negated ? "no-" : "",
1441 		  directive_info[begin_directive].name, file, line);
1442 	}
1443       else
1444 	{
1445 	  switch (end_directive)
1446 	    {
1447 	    case directive_literal:
1448 	      frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1449 	      xtensa_restore_emit_state (state);
1450 	      xtensa_set_frag_assembly_state (frag_now);
1451 	      free (state);
1452 	      if (!inside_directive (directive_literal))
1453 		{
1454 		  /* Restore the list of current labels.  */
1455 		  xtensa_clear_insn_labels ();
1456 		  insn_labels = saved_insn_labels;
1457 		}
1458 	      break;
1459 
1460 	    case directive_literal_prefix:
1461 	      /* Restore the default collection sections from saved state.  */
1462 	      s = (lit_state *) state;
1463 	      gas_assert (s);
1464 	      default_lit_sections = *s;
1465 
1466 	      /* Free the state storage.  */
1467 	      free (s->lit_prefix);
1468 	      free (s);
1469 	      break;
1470 
1471 	    case directive_schedule:
1472 	    case directive_freeregs:
1473 	      break;
1474 
1475 	    default:
1476 	      xtensa_set_frag_assembly_state (frag_now);
1477 	      break;
1478 	    }
1479 	}
1480     }
1481 
1482   demand_empty_rest_of_line ();
1483 }
1484 
1485 
1486 /* Place an aligned literal fragment at the current location.  */
1487 
1488 static void
xtensa_literal_position(int ignore ATTRIBUTE_UNUSED)1489 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1490 {
1491   md_flush_pending_output ();
1492 
1493   if (inside_directive (directive_literal))
1494     as_warn (_(".literal_position inside literal directive; ignoring"));
1495   xtensa_mark_literal_pool_location ();
1496 
1497   demand_empty_rest_of_line ();
1498   xtensa_clear_insn_labels ();
1499 }
1500 
1501 
1502 /* Support .literal label, expr, ...  */
1503 
1504 static void
xtensa_literal_pseudo(int ignored ATTRIBUTE_UNUSED)1505 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1506 {
1507   emit_state state;
1508   char *p, *base_name;
1509   char c;
1510   segT dest_seg;
1511 
1512   if (inside_directive (directive_literal))
1513     {
1514       as_bad (_(".literal not allowed inside .begin literal region"));
1515       ignore_rest_of_line ();
1516       return;
1517     }
1518 
1519   md_flush_pending_output ();
1520 
1521   /* Previous labels go with whatever follows this directive, not with
1522      the literal, so save them now.  */
1523   saved_insn_labels = insn_labels;
1524   insn_labels = NULL;
1525 
1526   /* If we are using text-section literals, then this is the right value... */
1527   dest_seg = now_seg;
1528 
1529   base_name = input_line_pointer;
1530 
1531   xtensa_switch_to_literal_fragment (&state);
1532 
1533   /* ...but if we aren't using text-section-literals, then we
1534      need to put them in the section we just switched to.  */
1535   if (use_literal_section || directive_state[directive_absolute_literals])
1536     dest_seg = now_seg;
1537 
1538   /* FIXME, despite the previous comments, dest_seg is unused...  */
1539   (void) dest_seg;
1540 
1541   /* All literals are aligned to four-byte boundaries.  */
1542   frag_align (2, 0, 0);
1543   record_alignment (now_seg, 2);
1544 
1545   c = get_symbol_name (&base_name);
1546   /* Just after name is now '\0'.  */
1547   p = input_line_pointer;
1548   *p = c;
1549   SKIP_WHITESPACE_AFTER_NAME ();
1550 
1551   if (*input_line_pointer != ',' && *input_line_pointer != ':')
1552     {
1553       as_bad (_("expected comma or colon after symbol name; "
1554 		"rest of line ignored"));
1555       ignore_rest_of_line ();
1556       xtensa_restore_emit_state (&state);
1557       return;
1558     }
1559 
1560   *p = 0;
1561   colon (base_name);
1562   *p = c;
1563 
1564   input_line_pointer++;		/* skip ',' or ':' */
1565 
1566   xtensa_elf_cons (4);
1567 
1568   xtensa_restore_emit_state (&state);
1569 
1570   /* Restore the list of current labels.  */
1571   xtensa_clear_insn_labels ();
1572   insn_labels = saved_insn_labels;
1573 }
1574 
1575 
1576 static void
xtensa_literal_prefix(void)1577 xtensa_literal_prefix (void)
1578 {
1579   char *name;
1580   int len;
1581 
1582   /* Parse the new prefix from the input_line_pointer.  */
1583   SKIP_WHITESPACE ();
1584   len = strspn (input_line_pointer,
1585 		"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1586 		"abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1587 
1588   /* Get a null-terminated copy of the name.  */
1589   name = xmemdup0 (input_line_pointer, len);
1590 
1591   /* Skip the name in the input line.  */
1592   input_line_pointer += len;
1593 
1594   default_lit_sections.lit_prefix = name;
1595 
1596   /* Clear cached literal sections, since the prefix has changed.  */
1597   default_lit_sections.lit_seg = NULL;
1598   default_lit_sections.lit4_seg = NULL;
1599 }
1600 
1601 
1602 /* Support ".frequency branch_target_frequency fall_through_frequency".  */
1603 
1604 static void
xtensa_frequency_pseudo(int ignored ATTRIBUTE_UNUSED)1605 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1606 {
1607   float fall_through_f, target_f;
1608 
1609   fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1610   if (fall_through_f < 0)
1611     {
1612       as_bad (_("fall through frequency must be greater than 0"));
1613       ignore_rest_of_line ();
1614       return;
1615     }
1616 
1617   target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1618   if (target_f < 0)
1619     {
1620       as_bad (_("branch target frequency must be greater than 0"));
1621       ignore_rest_of_line ();
1622       return;
1623     }
1624 
1625   set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1626 
1627   demand_empty_rest_of_line ();
1628 }
1629 
1630 
1631 /* Like normal .long/.short/.word, except support @plt, etc.
1632    Clobbers input_line_pointer, checks end-of-line.  */
1633 
1634 static void
xtensa_elf_cons(int nbytes)1635 xtensa_elf_cons (int nbytes)
1636 {
1637   expressionS exp;
1638   bfd_reloc_code_real_type reloc;
1639 
1640   md_flush_pending_output ();
1641 
1642   if (cur_vinsn.inside_bundle)
1643     as_bad (_("directives are not valid inside bundles"));
1644 
1645   if (is_it_end_of_statement ())
1646     {
1647       demand_empty_rest_of_line ();
1648       return;
1649     }
1650 
1651   do
1652     {
1653       expression (&exp);
1654       if (exp.X_op == O_symbol
1655 	  && *input_line_pointer == '@'
1656 	  && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1657 	      != BFD_RELOC_NONE))
1658 	{
1659 	  reloc_howto_type *reloc_howto =
1660 	    bfd_reloc_type_lookup (stdoutput, reloc);
1661 
1662 	  if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1663 	    as_bad (_("unsupported relocation"));
1664 	  else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1665 		    && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1666 		   || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1667 		       && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1668 	    as_bad (_("opcode-specific %s relocation used outside "
1669 		      "an instruction"), reloc_howto->name);
1670 	  else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1671 	    as_bad (_("%s relocations do not fit in %d bytes"),
1672 		    reloc_howto->name, nbytes);
1673 	  else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC
1674 		   || reloc == BFD_RELOC_XTENSA_TLS_ARG
1675 		   || reloc == BFD_RELOC_XTENSA_TLS_CALL)
1676 	    as_bad (_("invalid use of %s relocation"), reloc_howto->name);
1677 	  else
1678 	    {
1679 	      char *p = frag_more ((int) nbytes);
1680 	      xtensa_set_frag_assembly_state (frag_now);
1681 	      fix_new_exp (frag_now, p - frag_now->fr_literal,
1682 			   nbytes, &exp, reloc_howto->pc_relative, reloc);
1683 	    }
1684 	}
1685       else
1686 	{
1687 	  xtensa_set_frag_assembly_state (frag_now);
1688 	  emit_expr (&exp, (unsigned int) nbytes);
1689 	}
1690     }
1691   while (*input_line_pointer++ == ',');
1692 
1693   input_line_pointer--;		/* Put terminator back into stream.  */
1694   demand_empty_rest_of_line ();
1695 }
1696 
1697 static bfd_boolean is_leb128_expr;
1698 
1699 static void
xtensa_leb128(int sign)1700 xtensa_leb128 (int sign)
1701 {
1702   is_leb128_expr = TRUE;
1703   s_leb128 (sign);
1704   is_leb128_expr = FALSE;
1705 }
1706 
1707 
1708 /* Parsing and Idiom Translation.  */
1709 
1710 /* Parse @plt, etc. and return the desired relocation.  */
1711 static bfd_reloc_code_real_type
xtensa_elf_suffix(char ** str_p,expressionS * exp_p)1712 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1713 {
1714   char ident[20];
1715   char *str = *str_p;
1716   char *str2;
1717   int ch;
1718   int len;
1719   unsigned int i;
1720 
1721   if (*str++ != '@')
1722     return BFD_RELOC_NONE;
1723 
1724   for (ch = *str, str2 = ident;
1725        (str2 < ident + sizeof (ident) - 1
1726 	&& (ISALNUM (ch) || ch == '@'));
1727        ch = *++str)
1728     {
1729       *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1730     }
1731 
1732   *str2 = '\0';
1733   len = str2 - ident;
1734 
1735   ch = ident[0];
1736   for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1737     if (ch == suffix_relocs[i].suffix[0]
1738 	&& len == suffix_relocs[i].length
1739 	&& memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0)
1740       {
1741 	/* Now check for "identifier@suffix+constant".  */
1742 	if (*str == '-' || *str == '+')
1743 	  {
1744 	    char *orig_line = input_line_pointer;
1745 	    expressionS new_exp;
1746 
1747 	    input_line_pointer = str;
1748 	    expression (&new_exp);
1749 	    if (new_exp.X_op == O_constant)
1750 	      {
1751 		exp_p->X_add_number += new_exp.X_add_number;
1752 		str = input_line_pointer;
1753 	      }
1754 
1755 	    if (&input_line_pointer != str_p)
1756 	      input_line_pointer = orig_line;
1757 	  }
1758 
1759 	*str_p = str;
1760 	return suffix_relocs[i].reloc;
1761       }
1762 
1763   return BFD_RELOC_UNUSED;
1764 }
1765 
1766 
1767 /* Find the matching operator type.  */
1768 static operatorT
map_suffix_reloc_to_operator(bfd_reloc_code_real_type reloc)1769 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
1770 {
1771   operatorT operator = O_illegal;
1772   unsigned int i;
1773 
1774   for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1775     {
1776       if (suffix_relocs[i].reloc == reloc)
1777 	{
1778 	  operator = suffix_relocs[i].operator;
1779 	  break;
1780 	}
1781     }
1782   gas_assert (operator != O_illegal);
1783   return operator;
1784 }
1785 
1786 
1787 /* Find the matching reloc type.  */
1788 static bfd_reloc_code_real_type
map_operator_to_reloc(unsigned char operator,bfd_boolean is_literal)1789 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal)
1790 {
1791   unsigned int i;
1792   bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
1793 
1794   for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1795     {
1796       if (suffix_relocs[i].operator == operator)
1797 	{
1798 	  reloc = suffix_relocs[i].reloc;
1799 	  break;
1800 	}
1801     }
1802 
1803   if (is_literal)
1804     {
1805       if (reloc == BFD_RELOC_XTENSA_TLS_FUNC)
1806 	return BFD_RELOC_XTENSA_TLSDESC_FN;
1807       else if (reloc == BFD_RELOC_XTENSA_TLS_ARG)
1808 	return BFD_RELOC_XTENSA_TLSDESC_ARG;
1809     }
1810 
1811   if (reloc == BFD_RELOC_UNUSED)
1812     return BFD_RELOC_32;
1813 
1814   return reloc;
1815 }
1816 
1817 
1818 static const char *
expression_end(const char * name)1819 expression_end (const char *name)
1820 {
1821   while (1)
1822     {
1823       switch (*name)
1824 	{
1825 	case '}':
1826 	case ';':
1827 	case '\0':
1828 	case ',':
1829 	case ':':
1830 	  return name;
1831 	case ' ':
1832 	case '\t':
1833 	  ++name;
1834 	  continue;
1835 	default:
1836 	  return 0;
1837 	}
1838     }
1839 }
1840 
1841 
1842 #define ERROR_REG_NUM ((unsigned) -1)
1843 
1844 static unsigned
tc_get_register(const char * prefix)1845 tc_get_register (const char *prefix)
1846 {
1847   unsigned reg;
1848   const char *next_expr;
1849   const char *old_line_pointer;
1850 
1851   SKIP_WHITESPACE ();
1852   old_line_pointer = input_line_pointer;
1853 
1854   if (*input_line_pointer == '$')
1855     ++input_line_pointer;
1856 
1857   /* Accept "sp" as a synonym for "a1".  */
1858   if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1859       && expression_end (input_line_pointer + 2))
1860     {
1861       input_line_pointer += 2;
1862       return 1;  /* AR[1] */
1863     }
1864 
1865   while (*input_line_pointer++ == *prefix++)
1866     ;
1867   --input_line_pointer;
1868   --prefix;
1869 
1870   if (*prefix)
1871     {
1872       as_bad (_("bad register name: %s"), old_line_pointer);
1873       return ERROR_REG_NUM;
1874     }
1875 
1876   if (!ISDIGIT ((unsigned char) *input_line_pointer))
1877     {
1878       as_bad (_("bad register number: %s"), input_line_pointer);
1879       return ERROR_REG_NUM;
1880     }
1881 
1882   reg = 0;
1883 
1884   while (ISDIGIT ((int) *input_line_pointer))
1885     reg = reg * 10 + *input_line_pointer++ - '0';
1886 
1887   if (!(next_expr = expression_end (input_line_pointer)))
1888     {
1889       as_bad (_("bad register name: %s"), old_line_pointer);
1890       return ERROR_REG_NUM;
1891     }
1892 
1893   input_line_pointer = (char *) next_expr;
1894 
1895   return reg;
1896 }
1897 
1898 
1899 static void
expression_maybe_register(xtensa_opcode opc,int opnd,expressionS * tok)1900 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1901 {
1902   xtensa_isa isa = xtensa_default_isa;
1903 
1904   /* Check if this is an immediate operand.  */
1905   if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1906     {
1907       bfd_reloc_code_real_type reloc;
1908       segT t = expression (tok);
1909 
1910       if (t == absolute_section
1911 	  && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1912 	{
1913 	  gas_assert (tok->X_op == O_constant);
1914 	  tok->X_op = O_symbol;
1915 	  tok->X_add_symbol = &abs_symbol;
1916 	}
1917 
1918       if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1919 	  && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1920 	      != BFD_RELOC_NONE))
1921 	{
1922 	  switch (reloc)
1923 	    {
1924 	    case BFD_RELOC_LO16:
1925 	      if (tok->X_op == O_constant)
1926 		{
1927 		  tok->X_add_number &= 0xffff;
1928 		  return;
1929 		}
1930 	      break;
1931 	    case BFD_RELOC_HI16:
1932 	      if (tok->X_op == O_constant)
1933 		{
1934 		  tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1935 		  return;
1936 		}
1937 	      break;
1938 	    case BFD_RELOC_UNUSED:
1939 	      as_bad (_("unsupported relocation"));
1940 	      return;
1941 	    case BFD_RELOC_32_PCREL:
1942 	      as_bad (_("pcrel relocation not allowed in an instruction"));
1943 	      return;
1944 	    default:
1945 	      break;
1946 	    }
1947 	  tok->X_op = map_suffix_reloc_to_operator (reloc);
1948 	}
1949     }
1950   else
1951     {
1952       xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1953       unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1954 
1955       if (reg != ERROR_REG_NUM)	/* Already errored */
1956 	{
1957 	  uint32 buf = reg;
1958 	  if (xtensa_operand_encode (isa, opc, opnd, &buf))
1959 	    as_bad (_("register number out of range"));
1960 	}
1961 
1962       tok->X_op = O_register;
1963       tok->X_add_symbol = 0;
1964       tok->X_add_number = reg;
1965     }
1966 }
1967 
1968 
1969 /* Split up the arguments for an opcode or pseudo-op.  */
1970 
1971 static int
tokenize_arguments(char ** args,char * str)1972 tokenize_arguments (char **args, char *str)
1973 {
1974   char *old_input_line_pointer;
1975   bfd_boolean saw_comma = FALSE;
1976   bfd_boolean saw_arg = FALSE;
1977   bfd_boolean saw_colon = FALSE;
1978   int num_args = 0;
1979   char *arg_end, *arg;
1980   int arg_len;
1981 
1982   /* Save and restore input_line_pointer around this function.  */
1983   old_input_line_pointer = input_line_pointer;
1984   input_line_pointer = str;
1985 
1986   while (*input_line_pointer)
1987     {
1988       SKIP_WHITESPACE ();
1989       switch (*input_line_pointer)
1990 	{
1991 	case '\0':
1992 	case '}':
1993 	  goto fini;
1994 
1995 	case ':':
1996 	  input_line_pointer++;
1997 	  if (saw_comma || saw_colon || !saw_arg)
1998 	    goto err;
1999 	  saw_colon = TRUE;
2000 	  break;
2001 
2002 	case ',':
2003 	  input_line_pointer++;
2004 	  if (saw_comma || saw_colon || !saw_arg)
2005 	    goto err;
2006 	  saw_comma = TRUE;
2007 	  break;
2008 
2009 	default:
2010 	  if (!saw_comma && !saw_colon && saw_arg)
2011 	    goto err;
2012 
2013 	  arg_end = input_line_pointer + 1;
2014 	  while (!expression_end (arg_end))
2015 	    arg_end += 1;
2016 
2017 	  arg_len = arg_end - input_line_pointer;
2018 	  arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1);
2019 	  args[num_args] = arg;
2020 
2021 	  if (saw_colon)
2022 	    *arg++ = ':';
2023 	  strncpy (arg, input_line_pointer, arg_len);
2024 	  arg[arg_len] = '\0';
2025 
2026 	  input_line_pointer = arg_end;
2027 	  num_args += 1;
2028 	  saw_comma = FALSE;
2029 	  saw_colon = FALSE;
2030 	  saw_arg = TRUE;
2031 	  break;
2032 	}
2033     }
2034 
2035 fini:
2036   if (saw_comma || saw_colon)
2037     goto err;
2038   input_line_pointer = old_input_line_pointer;
2039   return num_args;
2040 
2041 err:
2042   if (saw_comma)
2043     as_bad (_("extra comma"));
2044   else if (saw_colon)
2045     as_bad (_("extra colon"));
2046   else if (!saw_arg)
2047     as_bad (_("missing argument"));
2048   else
2049     as_bad (_("missing comma or colon"));
2050   input_line_pointer = old_input_line_pointer;
2051   return -1;
2052 }
2053 
2054 
2055 /* Parse the arguments to an opcode.  Return TRUE on error.  */
2056 
2057 static bfd_boolean
parse_arguments(TInsn * insn,int num_args,char ** arg_strings)2058 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
2059 {
2060   expressionS *tok, *last_tok;
2061   xtensa_opcode opcode = insn->opcode;
2062   bfd_boolean had_error = TRUE;
2063   xtensa_isa isa = xtensa_default_isa;
2064   int n, num_regs = 0;
2065   int opcode_operand_count;
2066   int opnd_cnt, last_opnd_cnt;
2067   unsigned int next_reg = 0;
2068   char *old_input_line_pointer;
2069 
2070   if (insn->insn_type == ITYPE_LITERAL)
2071     opcode_operand_count = 1;
2072   else
2073     opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
2074 
2075   tok = insn->tok;
2076   memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
2077 
2078   /* Save and restore input_line_pointer around this function.  */
2079   old_input_line_pointer = input_line_pointer;
2080 
2081   last_tok = 0;
2082   last_opnd_cnt = -1;
2083   opnd_cnt = 0;
2084 
2085   /* Skip invisible operands.  */
2086   while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2087     {
2088       opnd_cnt += 1;
2089       tok++;
2090     }
2091 
2092   for (n = 0; n < num_args; n++)
2093     {
2094       input_line_pointer = arg_strings[n];
2095       if (*input_line_pointer == ':')
2096 	{
2097 	  xtensa_regfile opnd_rf;
2098 	  input_line_pointer++;
2099 	  if (num_regs == 0)
2100 	    goto err;
2101 	  gas_assert (opnd_cnt > 0);
2102 	  num_regs--;
2103 	  opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2104 	  if (next_reg
2105 	      != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2106 	    as_warn (_("incorrect register number, ignoring"));
2107 	  next_reg++;
2108 	}
2109       else
2110 	{
2111 	  if (opnd_cnt >= opcode_operand_count)
2112 	    {
2113 	      as_warn (_("too many arguments"));
2114 	      goto err;
2115 	    }
2116 	  gas_assert (opnd_cnt < MAX_INSN_ARGS);
2117 
2118 	  expression_maybe_register (opcode, opnd_cnt, tok);
2119 	  next_reg = tok->X_add_number + 1;
2120 
2121 	  if (tok->X_op == O_illegal || tok->X_op == O_absent)
2122 	    goto err;
2123 	  if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2124 	    {
2125 	      num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2126 	      /* minus 1 because we are seeing one right now */
2127 	    }
2128 	  else
2129 	    num_regs = 0;
2130 
2131 	  last_tok = tok;
2132 	  last_opnd_cnt = opnd_cnt;
2133 	  demand_empty_rest_of_line ();
2134 
2135 	  do
2136 	    {
2137 	      opnd_cnt += 1;
2138 	      tok++;
2139 	    }
2140 	  while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2141 	}
2142     }
2143 
2144   if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2145     goto err;
2146 
2147   insn->ntok = tok - insn->tok;
2148   had_error = FALSE;
2149 
2150  err:
2151   input_line_pointer = old_input_line_pointer;
2152   return had_error;
2153 }
2154 
2155 
2156 static int
get_invisible_operands(TInsn * insn)2157 get_invisible_operands (TInsn *insn)
2158 {
2159   xtensa_isa isa = xtensa_default_isa;
2160   static xtensa_insnbuf slotbuf = NULL;
2161   xtensa_format fmt;
2162   xtensa_opcode opc = insn->opcode;
2163   int slot, opnd, fmt_found;
2164   unsigned val;
2165 
2166   if (!slotbuf)
2167     slotbuf = xtensa_insnbuf_alloc (isa);
2168 
2169   /* Find format/slot where this can be encoded.  */
2170   fmt_found = 0;
2171   slot = 0;
2172   for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2173     {
2174       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2175 	{
2176 	  if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2177 	    {
2178 	      fmt_found = 1;
2179 	      break;
2180 	    }
2181 	}
2182       if (fmt_found) break;
2183     }
2184 
2185   if (!fmt_found)
2186     {
2187       as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2188       return -1;
2189     }
2190 
2191   /* First encode all the visible operands
2192      (to deal with shared field operands).  */
2193   for (opnd = 0; opnd < insn->ntok; opnd++)
2194     {
2195       if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2196 	  && (insn->tok[opnd].X_op == O_register
2197 	      || insn->tok[opnd].X_op == O_constant))
2198 	{
2199 	  val = insn->tok[opnd].X_add_number;
2200 	  xtensa_operand_encode (isa, opc, opnd, &val);
2201 	  xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2202 	}
2203     }
2204 
2205   /* Then pull out the values for the invisible ones.  */
2206   for (opnd = 0; opnd < insn->ntok; opnd++)
2207     {
2208       if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2209 	{
2210 	  xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2211 	  xtensa_operand_decode (isa, opc, opnd, &val);
2212 	  insn->tok[opnd].X_add_number = val;
2213 	  if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2214 	    insn->tok[opnd].X_op = O_register;
2215 	  else
2216 	    insn->tok[opnd].X_op = O_constant;
2217 	}
2218     }
2219 
2220   return 0;
2221 }
2222 
2223 
2224 static void
xg_reverse_shift_count(char ** cnt_argp)2225 xg_reverse_shift_count (char **cnt_argp)
2226 {
2227   char *cnt_arg, *new_arg;
2228   cnt_arg = *cnt_argp;
2229 
2230   /* replace the argument with "31-(argument)" */
2231   new_arg = concat ("31-(", cnt_argp, ")", (char *) NULL);
2232 
2233   free (cnt_arg);
2234   *cnt_argp = new_arg;
2235 }
2236 
2237 
2238 /* If "arg" is a constant expression, return non-zero with the value
2239    in *valp.  */
2240 
2241 static int
xg_arg_is_constant(char * arg,offsetT * valp)2242 xg_arg_is_constant (char *arg, offsetT *valp)
2243 {
2244   expressionS exp;
2245   char *save_ptr = input_line_pointer;
2246 
2247   input_line_pointer = arg;
2248   expression (&exp);
2249   input_line_pointer = save_ptr;
2250 
2251   if (exp.X_op == O_constant)
2252     {
2253       *valp = exp.X_add_number;
2254       return 1;
2255     }
2256 
2257   return 0;
2258 }
2259 
2260 
2261 static void
xg_replace_opname(char ** popname,const char * newop)2262 xg_replace_opname (char **popname, const char *newop)
2263 {
2264   free (*popname);
2265   *popname = xstrdup (newop);
2266 }
2267 
2268 
2269 static int
xg_check_num_args(int * pnum_args,int expected_num,char * opname,char ** arg_strings)2270 xg_check_num_args (int *pnum_args,
2271 		   int expected_num,
2272 		   char *opname,
2273 		   char **arg_strings)
2274 {
2275   int num_args = *pnum_args;
2276 
2277   if (num_args < expected_num)
2278     {
2279       as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2280 	      num_args, opname, expected_num);
2281       return -1;
2282     }
2283 
2284   if (num_args > expected_num)
2285     {
2286       as_warn (_("too many operands (%d) for '%s'; expected %d"),
2287 	       num_args, opname, expected_num);
2288       while (num_args-- > expected_num)
2289 	{
2290 	  free (arg_strings[num_args]);
2291 	  arg_strings[num_args] = 0;
2292 	}
2293       *pnum_args = expected_num;
2294       return -1;
2295     }
2296 
2297   return 0;
2298 }
2299 
2300 
2301 /* If the register is not specified as part of the opcode,
2302    then get it from the operand and move it to the opcode.  */
2303 
2304 static int
xg_translate_sysreg_op(char ** popname,int * pnum_args,char ** arg_strings)2305 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2306 {
2307   xtensa_isa isa = xtensa_default_isa;
2308   xtensa_sysreg sr;
2309   char *opname, *new_opname;
2310   const char *sr_name;
2311   int is_user, is_write;
2312 
2313   opname = *popname;
2314   if (*opname == '_')
2315     opname += 1;
2316   is_user = (opname[1] == 'u');
2317   is_write = (opname[0] == 'w');
2318 
2319   /* Opname == [rw]ur or [rwx]sr... */
2320 
2321   if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2322     return -1;
2323 
2324   /* Check if the argument is a symbolic register name.  */
2325   sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2326   /* Handle WSR to "INTSET" as a special case.  */
2327   if (sr == XTENSA_UNDEFINED && is_write && !is_user
2328       && !strcasecmp (arg_strings[1], "intset"))
2329     sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2330   if (sr == XTENSA_UNDEFINED
2331       || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2332     {
2333       /* Maybe it's a register number.... */
2334       offsetT val;
2335       if (!xg_arg_is_constant (arg_strings[1], &val))
2336 	{
2337 	  as_bad (_("invalid register '%s' for '%s' instruction"),
2338 		  arg_strings[1], opname);
2339 	  return -1;
2340 	}
2341       sr = xtensa_sysreg_lookup (isa, val, is_user);
2342       if (sr == XTENSA_UNDEFINED)
2343 	{
2344 	  as_bad (_("invalid register number (%ld) for '%s' instruction"),
2345 		  (long) val, opname);
2346 	  return -1;
2347 	}
2348     }
2349 
2350   /* Remove the last argument, which is now part of the opcode.  */
2351   free (arg_strings[1]);
2352   arg_strings[1] = 0;
2353   *pnum_args = 1;
2354 
2355   /* Translate the opcode.  */
2356   sr_name = xtensa_sysreg_name (isa, sr);
2357   /* Another special case for "WSR.INTSET"....  */
2358   if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2359     sr_name = "intset";
2360   new_opname = concat (*popname, ".", sr_name, (char *) NULL);
2361   free (*popname);
2362   *popname = new_opname;
2363 
2364   return 0;
2365 }
2366 
2367 
2368 static int
xtensa_translate_old_userreg_ops(char ** popname)2369 xtensa_translate_old_userreg_ops (char **popname)
2370 {
2371   xtensa_isa isa = xtensa_default_isa;
2372   xtensa_sysreg sr;
2373   char *opname, *new_opname;
2374   const char *sr_name;
2375   bfd_boolean has_underbar = FALSE;
2376 
2377   opname = *popname;
2378   if (opname[0] == '_')
2379     {
2380       has_underbar = TRUE;
2381       opname += 1;
2382     }
2383 
2384   sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2385   if (sr != XTENSA_UNDEFINED)
2386     {
2387       /* The new default name ("nnn") is different from the old default
2388 	 name ("URnnn").  The old default is handled below, and we don't
2389 	 want to recognize [RW]nnn, so do nothing if the name is the (new)
2390 	 default.  */
2391       static char namebuf[10];
2392       sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2393       if (strcmp (namebuf, opname + 1) == 0)
2394 	return 0;
2395     }
2396   else
2397     {
2398       offsetT val;
2399       char *end;
2400 
2401       /* Only continue if the reg name is "URnnn".  */
2402       if (opname[1] != 'u' || opname[2] != 'r')
2403 	return 0;
2404       val = strtoul (opname + 3, &end, 10);
2405       if (*end != '\0')
2406 	return 0;
2407 
2408       sr = xtensa_sysreg_lookup (isa, val, 1);
2409       if (sr == XTENSA_UNDEFINED)
2410 	{
2411 	  as_bad (_("invalid register number (%ld) for '%s'"),
2412 		  (long) val, opname);
2413 	  return -1;
2414 	}
2415     }
2416 
2417   /* Translate the opcode.  */
2418   sr_name = xtensa_sysreg_name (isa, sr);
2419   new_opname = XNEWVEC (char, strlen (sr_name) + 6);
2420   sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2421 	   opname[0], sr_name);
2422   free (*popname);
2423   *popname = new_opname;
2424 
2425   return 0;
2426 }
2427 
2428 
2429 static int
xtensa_translate_zero_immed(const char * old_op,const char * new_op,char ** popname,int * pnum_args,char ** arg_strings)2430 xtensa_translate_zero_immed (const char *old_op,
2431 			     const char *new_op,
2432 			     char **popname,
2433 			     int *pnum_args,
2434 			     char **arg_strings)
2435 {
2436   char *opname;
2437   offsetT val;
2438 
2439   opname = *popname;
2440   gas_assert (opname[0] != '_');
2441 
2442   if (strcmp (opname, old_op) != 0)
2443     return 0;
2444 
2445   if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2446     return -1;
2447   if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2448     {
2449       xg_replace_opname (popname, new_op);
2450       free (arg_strings[1]);
2451       arg_strings[1] = arg_strings[2];
2452       arg_strings[2] = 0;
2453       *pnum_args = 2;
2454     }
2455 
2456   return 0;
2457 }
2458 
2459 
2460 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2461    Returns non-zero if an error was found.  */
2462 
2463 static int
xg_translate_idioms(char ** popname,int * pnum_args,char ** arg_strings)2464 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2465 {
2466   char *opname = *popname;
2467   bfd_boolean has_underbar = FALSE;
2468 
2469   if (*opname == '_')
2470     {
2471       has_underbar = TRUE;
2472       opname += 1;
2473     }
2474 
2475   if (strcmp (opname, "mov") == 0)
2476     {
2477       if (use_transform () && !has_underbar && density_supported)
2478 	xg_replace_opname (popname, "mov.n");
2479       else
2480 	{
2481 	  if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2482 	    return -1;
2483 	  xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2484 	  arg_strings[2] = xstrdup (arg_strings[1]);
2485 	  *pnum_args = 3;
2486 	}
2487       return 0;
2488     }
2489 
2490   if (strcmp (opname, "bbsi.l") == 0)
2491     {
2492       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2493 	return -1;
2494       xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2495       if (target_big_endian)
2496 	xg_reverse_shift_count (&arg_strings[1]);
2497       return 0;
2498     }
2499 
2500   if (strcmp (opname, "bbci.l") == 0)
2501     {
2502       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2503 	return -1;
2504       xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2505       if (target_big_endian)
2506 	xg_reverse_shift_count (&arg_strings[1]);
2507       return 0;
2508     }
2509 
2510   /* Don't do anything special with NOPs inside FLIX instructions.  They
2511      are handled elsewhere.  Real NOP instructions are always available
2512      in configurations with FLIX, so this should never be an issue but
2513      check for it anyway.  */
2514   if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
2515       && strcmp (opname, "nop") == 0)
2516     {
2517       if (use_transform () && !has_underbar && density_supported)
2518 	xg_replace_opname (popname, "nop.n");
2519       else
2520 	{
2521 	  if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2522 	    return -1;
2523 	  xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2524 	  arg_strings[0] = xstrdup ("a1");
2525 	  arg_strings[1] = xstrdup ("a1");
2526 	  arg_strings[2] = xstrdup ("a1");
2527 	  *pnum_args = 3;
2528 	}
2529       return 0;
2530     }
2531 
2532   /* Recognize [RW]UR and [RWX]SR.  */
2533   if ((((opname[0] == 'r' || opname[0] == 'w')
2534 	&& (opname[1] == 'u' || opname[1] == 's'))
2535        || (opname[0] == 'x' && opname[1] == 's'))
2536       && opname[2] == 'r'
2537       && opname[3] == '\0')
2538     return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2539 
2540   /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2541      [RW]<name> if <name> is the non-default name of a user register.  */
2542   if ((opname[0] == 'r' || opname[0] == 'w')
2543       && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2544     return xtensa_translate_old_userreg_ops (popname);
2545 
2546   /* Relax branches that don't allow comparisons against an immediate value
2547      of zero to the corresponding branches with implicit zero immediates.  */
2548   if (!has_underbar && use_transform ())
2549     {
2550       if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2551 				       pnum_args, arg_strings))
2552 	return -1;
2553 
2554       if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2555 				       pnum_args, arg_strings))
2556 	return -1;
2557 
2558       if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2559 				       pnum_args, arg_strings))
2560 	return -1;
2561 
2562       if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2563 				       pnum_args, arg_strings))
2564 	return -1;
2565     }
2566 
2567   return 0;
2568 }
2569 
2570 
2571 /* Functions for dealing with the Xtensa ISA.  */
2572 
2573 /* Currently the assembler only allows us to use a single target per
2574    fragment.  Because of this, only one operand for a given
2575    instruction may be symbolic.  If there is a PC-relative operand,
2576    the last one is chosen.  Otherwise, the result is the number of the
2577    last immediate operand, and if there are none of those, we fail and
2578    return -1.  */
2579 
2580 static int
get_relaxable_immed(xtensa_opcode opcode)2581 get_relaxable_immed (xtensa_opcode opcode)
2582 {
2583   int last_immed = -1;
2584   int noperands, opi;
2585 
2586   if (opcode == XTENSA_UNDEFINED)
2587     return -1;
2588 
2589   noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2590   for (opi = noperands - 1; opi >= 0; opi--)
2591     {
2592       if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2593 	continue;
2594       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2595 	return opi;
2596       if (last_immed == -1
2597 	  && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2598 	last_immed = opi;
2599     }
2600   return last_immed;
2601 }
2602 
2603 
2604 static xtensa_opcode
get_opcode_from_buf(const char * buf,int slot)2605 get_opcode_from_buf (const char *buf, int slot)
2606 {
2607   static xtensa_insnbuf insnbuf = NULL;
2608   static xtensa_insnbuf slotbuf = NULL;
2609   xtensa_isa isa = xtensa_default_isa;
2610   xtensa_format fmt;
2611 
2612   if (!insnbuf)
2613     {
2614       insnbuf = xtensa_insnbuf_alloc (isa);
2615       slotbuf = xtensa_insnbuf_alloc (isa);
2616     }
2617 
2618   xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
2619   fmt = xtensa_format_decode (isa, insnbuf);
2620   if (fmt == XTENSA_UNDEFINED)
2621     return XTENSA_UNDEFINED;
2622 
2623   if (slot >= xtensa_format_num_slots (isa, fmt))
2624     return XTENSA_UNDEFINED;
2625 
2626   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2627   return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2628 }
2629 
2630 
2631 #ifdef TENSILICA_DEBUG
2632 
2633 /* For debugging, print out the mapping of opcode numbers to opcodes.  */
2634 
2635 static void
xtensa_print_insn_table(void)2636 xtensa_print_insn_table (void)
2637 {
2638   int num_opcodes, num_operands;
2639   xtensa_opcode opcode;
2640   xtensa_isa isa = xtensa_default_isa;
2641 
2642   num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2643   for (opcode = 0; opcode < num_opcodes; opcode++)
2644     {
2645       int opn;
2646       fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2647       num_operands = xtensa_opcode_num_operands (isa, opcode);
2648       for (opn = 0; opn < num_operands; opn++)
2649 	{
2650 	  if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2651 	    continue;
2652 	  if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2653 	    {
2654 	      xtensa_regfile opnd_rf =
2655 		xtensa_operand_regfile (isa, opcode, opn);
2656 	      fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2657 	    }
2658 	  else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2659 	    fputs ("[lLr] ", stderr);
2660 	  else
2661 	    fputs ("i ", stderr);
2662 	}
2663       fprintf (stderr, "\n");
2664     }
2665 }
2666 
2667 
2668 static void
print_vliw_insn(xtensa_insnbuf vbuf)2669 print_vliw_insn (xtensa_insnbuf vbuf)
2670 {
2671   xtensa_isa isa = xtensa_default_isa;
2672   xtensa_format f = xtensa_format_decode (isa, vbuf);
2673   xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2674   int op;
2675 
2676   fprintf (stderr, "format = %d\n", f);
2677 
2678   for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2679     {
2680       xtensa_opcode opcode;
2681       const char *opname;
2682       int operands;
2683 
2684       xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2685       opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2686       opname = xtensa_opcode_name (isa, opcode);
2687 
2688       fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2689       fprintf (stderr, "   operands = ");
2690       for (operands = 0;
2691 	   operands < xtensa_opcode_num_operands (isa, opcode);
2692 	   operands++)
2693 	{
2694 	  unsigned int val;
2695 	  if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2696 	    continue;
2697 	  xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2698 	  xtensa_operand_decode (isa, opcode, operands, &val);
2699 	  fprintf (stderr, "%d ", val);
2700 	}
2701       fprintf (stderr, "\n");
2702     }
2703   xtensa_insnbuf_free (isa, sbuf);
2704 }
2705 
2706 #endif /* TENSILICA_DEBUG */
2707 
2708 
2709 static bfd_boolean
is_direct_call_opcode(xtensa_opcode opcode)2710 is_direct_call_opcode (xtensa_opcode opcode)
2711 {
2712   xtensa_isa isa = xtensa_default_isa;
2713   int n, num_operands;
2714 
2715   if (xtensa_opcode_is_call (isa, opcode) != 1)
2716     return FALSE;
2717 
2718   num_operands = xtensa_opcode_num_operands (isa, opcode);
2719   for (n = 0; n < num_operands; n++)
2720     {
2721       if (xtensa_operand_is_register (isa, opcode, n) == 0
2722 	  && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2723 	return TRUE;
2724     }
2725   return FALSE;
2726 }
2727 
2728 
2729 /* Convert from BFD relocation type code to slot and operand number.
2730    Returns non-zero on failure.  */
2731 
2732 static int
decode_reloc(bfd_reloc_code_real_type reloc,int * slot,bfd_boolean * is_alt)2733 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2734 {
2735   if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2736       && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2737     {
2738       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2739       *is_alt = FALSE;
2740     }
2741   else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2742       && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2743     {
2744       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2745       *is_alt = TRUE;
2746     }
2747   else
2748     return -1;
2749 
2750   return 0;
2751 }
2752 
2753 
2754 /* Convert from slot number to BFD relocation type code for the
2755    standard PC-relative relocations.  Return BFD_RELOC_NONE on
2756    failure.  */
2757 
2758 static bfd_reloc_code_real_type
encode_reloc(int slot)2759 encode_reloc (int slot)
2760 {
2761   if (slot < 0 || slot > 14)
2762     return BFD_RELOC_NONE;
2763 
2764   return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2765 }
2766 
2767 
2768 /* Convert from slot numbers to BFD relocation type code for the
2769    "alternate" relocations.  Return BFD_RELOC_NONE on failure.  */
2770 
2771 static bfd_reloc_code_real_type
encode_alt_reloc(int slot)2772 encode_alt_reloc (int slot)
2773 {
2774   if (slot < 0 || slot > 14)
2775     return BFD_RELOC_NONE;
2776 
2777   return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2778 }
2779 
2780 
2781 static void
xtensa_insnbuf_set_operand(xtensa_insnbuf slotbuf,xtensa_format fmt,int slot,xtensa_opcode opcode,int operand,uint32 value,const char * file,unsigned int line)2782 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2783 			    xtensa_format fmt,
2784 			    int slot,
2785 			    xtensa_opcode opcode,
2786 			    int operand,
2787 			    uint32 value,
2788 			    const char *file,
2789 			    unsigned int line)
2790 {
2791   uint32 valbuf = value;
2792 
2793   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2794     {
2795       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2796 	  == 1)
2797 	as_bad_where ((char *) file, line,
2798 		      _("operand %d of '%s' has out of range value '%u'"),
2799 		      operand + 1,
2800 		      xtensa_opcode_name (xtensa_default_isa, opcode),
2801 		      value);
2802       else
2803 	as_bad_where ((char *) file, line,
2804 		      _("operand %d of '%s' has invalid value '%u'"),
2805 		      operand + 1,
2806 		      xtensa_opcode_name (xtensa_default_isa, opcode),
2807 		      value);
2808       return;
2809     }
2810 
2811   xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2812 			    slotbuf, valbuf);
2813 }
2814 
2815 
2816 static uint32
xtensa_insnbuf_get_operand(xtensa_insnbuf slotbuf,xtensa_format fmt,int slot,xtensa_opcode opcode,int opnum)2817 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2818 			    xtensa_format fmt,
2819 			    int slot,
2820 			    xtensa_opcode opcode,
2821 			    int opnum)
2822 {
2823   uint32 val = 0;
2824   (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2825 				   fmt, slot, slotbuf, &val);
2826   (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2827   return val;
2828 }
2829 
2830 
2831 /* Checks for rules from xtensa-relax tables.  */
2832 
2833 /* The routine xg_instruction_matches_option_term must return TRUE
2834    when a given option term is true.  The meaning of all of the option
2835    terms is given interpretation by this function.  */
2836 
2837 static bfd_boolean
xg_instruction_matches_option_term(TInsn * insn,const ReqOrOption * option)2838 xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
2839 {
2840   if (strcmp (option->option_name, "realnop") == 0
2841       || strncmp (option->option_name, "IsaUse", 6) == 0)
2842     {
2843       /* These conditions were evaluated statically when building the
2844 	 relaxation table.  There's no need to reevaluate them now.  */
2845       return TRUE;
2846     }
2847   else if (strcmp (option->option_name, "FREEREG") == 0)
2848     return insn->extra_arg.X_op == O_register;
2849   else
2850     {
2851       as_fatal (_("internal error: unknown option name '%s'"),
2852 		option->option_name);
2853     }
2854 }
2855 
2856 
2857 static bfd_boolean
xg_instruction_matches_or_options(TInsn * insn,const ReqOrOptionList * or_option)2858 xg_instruction_matches_or_options (TInsn *insn,
2859 				   const ReqOrOptionList *or_option)
2860 {
2861   const ReqOrOption *option;
2862   /* Must match each of the AND terms.  */
2863   for (option = or_option; option != NULL; option = option->next)
2864     {
2865       if (xg_instruction_matches_option_term (insn, option))
2866 	return TRUE;
2867     }
2868   return FALSE;
2869 }
2870 
2871 
2872 static bfd_boolean
xg_instruction_matches_options(TInsn * insn,const ReqOptionList * options)2873 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2874 {
2875   const ReqOption *req_options;
2876   /* Must match each of the AND terms.  */
2877   for (req_options = options;
2878        req_options != NULL;
2879        req_options = req_options->next)
2880     {
2881       /* Must match one of the OR clauses.  */
2882       if (!xg_instruction_matches_or_options (insn,
2883 					      req_options->or_option_terms))
2884 	return FALSE;
2885     }
2886   return TRUE;
2887 }
2888 
2889 
2890 /* Return the transition rule that matches or NULL if none matches.  */
2891 
2892 static bfd_boolean
xg_instruction_matches_rule(TInsn * insn,TransitionRule * rule)2893 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2894 {
2895   PreconditionList *condition_l;
2896 
2897   if (rule->opcode != insn->opcode)
2898     return FALSE;
2899 
2900   for (condition_l = rule->conditions;
2901        condition_l != NULL;
2902        condition_l = condition_l->next)
2903     {
2904       expressionS *exp1;
2905       expressionS *exp2;
2906       Precondition *cond = condition_l->precond;
2907 
2908       switch (cond->typ)
2909 	{
2910 	case OP_CONSTANT:
2911 	  /* The expression must be the constant.  */
2912 	  gas_assert (cond->op_num < insn->ntok);
2913 	  exp1 = &insn->tok[cond->op_num];
2914 	  if (expr_is_const (exp1))
2915 	    {
2916 	      switch (cond->cmp)
2917 		{
2918 		case OP_EQUAL:
2919 		  if (get_expr_const (exp1) != cond->op_data)
2920 		    return FALSE;
2921 		  break;
2922 		case OP_NOTEQUAL:
2923 		  if (get_expr_const (exp1) == cond->op_data)
2924 		    return FALSE;
2925 		  break;
2926 		default:
2927 		  return FALSE;
2928 		}
2929 	    }
2930 	  else if (expr_is_register (exp1))
2931 	    {
2932 	      switch (cond->cmp)
2933 		{
2934 		case OP_EQUAL:
2935 		  if (get_expr_register (exp1) != cond->op_data)
2936 		    return FALSE;
2937 		  break;
2938 		case OP_NOTEQUAL:
2939 		  if (get_expr_register (exp1) == cond->op_data)
2940 		    return FALSE;
2941 		  break;
2942 		default:
2943 		  return FALSE;
2944 		}
2945 	    }
2946 	  else
2947 	    return FALSE;
2948 	  break;
2949 
2950 	case OP_OPERAND:
2951 	  gas_assert (cond->op_num < insn->ntok);
2952 	  gas_assert (cond->op_data < insn->ntok);
2953 	  exp1 = &insn->tok[cond->op_num];
2954 	  exp2 = &insn->tok[cond->op_data];
2955 
2956 	  switch (cond->cmp)
2957 	    {
2958 	    case OP_EQUAL:
2959 	      if (!expr_is_equal (exp1, exp2))
2960 		return FALSE;
2961 	      break;
2962 	    case OP_NOTEQUAL:
2963 	      if (expr_is_equal (exp1, exp2))
2964 		return FALSE;
2965 	      break;
2966 	    }
2967 	  break;
2968 
2969 	case OP_LITERAL:
2970 	case OP_LABEL:
2971 	default:
2972 	  return FALSE;
2973 	}
2974     }
2975   if (!xg_instruction_matches_options (insn, rule->options))
2976     return FALSE;
2977 
2978   return TRUE;
2979 }
2980 
2981 
2982 static int
transition_rule_cmp(const TransitionRule * a,const TransitionRule * b)2983 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2984 {
2985   bfd_boolean a_greater = FALSE;
2986   bfd_boolean b_greater = FALSE;
2987 
2988   ReqOptionList *l_a = a->options;
2989   ReqOptionList *l_b = b->options;
2990 
2991   /* We only care if they both are the same except for
2992      a const16 vs. an l32r.  */
2993 
2994   while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2995     {
2996       ReqOrOptionList *l_or_a = l_a->or_option_terms;
2997       ReqOrOptionList *l_or_b = l_b->or_option_terms;
2998       while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2999 	{
3000 	  if (l_or_a->is_true != l_or_b->is_true)
3001 	    return 0;
3002 	  if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
3003 	    {
3004 	      /* This is the case we care about.  */
3005 	      if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
3006 		  && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
3007 		{
3008 		  if (prefer_const16)
3009 		    a_greater = TRUE;
3010 		  else
3011 		    b_greater = TRUE;
3012 		}
3013 	      else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
3014 		       && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
3015 		{
3016 		  if (prefer_const16)
3017 		    b_greater = TRUE;
3018 		  else
3019 		    a_greater = TRUE;
3020 		}
3021 	      else
3022 		return 0;
3023 	    }
3024 	  l_or_a = l_or_a->next;
3025 	  l_or_b = l_or_b->next;
3026 	}
3027       if (l_or_a || l_or_b)
3028 	return 0;
3029 
3030       l_a = l_a->next;
3031       l_b = l_b->next;
3032     }
3033   if (l_a || l_b)
3034     return 0;
3035 
3036   /* Incomparable if the substitution was used differently in two cases.  */
3037   if (a_greater && b_greater)
3038     return 0;
3039 
3040   if (b_greater)
3041     return 1;
3042   if (a_greater)
3043     return -1;
3044 
3045   return 0;
3046 }
3047 
3048 
3049 static TransitionRule *
xg_instruction_match(TInsn * insn)3050 xg_instruction_match (TInsn *insn)
3051 {
3052   TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
3053   TransitionList *l;
3054   gas_assert (insn->opcode < table->num_opcodes);
3055 
3056   /* Walk through all of the possible transitions.  */
3057   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3058     {
3059       TransitionRule *rule = l->rule;
3060       if (xg_instruction_matches_rule (insn, rule))
3061 	return rule;
3062     }
3063   return NULL;
3064 }
3065 
3066 
3067 /* Various Other Internal Functions.  */
3068 
3069 static bfd_boolean
is_unique_insn_expansion(TransitionRule * r)3070 is_unique_insn_expansion (TransitionRule *r)
3071 {
3072   if (!r->to_instr || r->to_instr->next != NULL)
3073     return FALSE;
3074   if (r->to_instr->typ != INSTR_INSTR)
3075     return FALSE;
3076   return TRUE;
3077 }
3078 
3079 
3080 /* Check if there is exactly one relaxation for INSN that converts it to
3081    another instruction of equal or larger size.  If so, and if TARG is
3082    non-null, go ahead and generate the relaxed instruction into TARG.  If
3083    NARROW_ONLY is true, then only consider relaxations that widen a narrow
3084    instruction, i.e., ignore relaxations that convert to an instruction of
3085    equal size.  In some contexts where this function is used, only
3086    a single widening is allowed and the NARROW_ONLY argument is used to
3087    exclude cases like ADDI being "widened" to an ADDMI, which may
3088    later be relaxed to an ADDMI/ADDI pair.  */
3089 
3090 bfd_boolean
xg_is_single_relaxable_insn(TInsn * insn,TInsn * targ,bfd_boolean narrow_only)3091 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
3092 {
3093   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3094   TransitionList *l;
3095   TransitionRule *match = 0;
3096 
3097   gas_assert (insn->insn_type == ITYPE_INSN);
3098   gas_assert (insn->opcode < table->num_opcodes);
3099 
3100   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3101     {
3102       TransitionRule *rule = l->rule;
3103 
3104       if (xg_instruction_matches_rule (insn, rule)
3105 	  && is_unique_insn_expansion (rule)
3106 	  && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
3107 	      <= xg_get_single_size (rule->to_instr->opcode)))
3108 	{
3109 	  if (match)
3110 	    return FALSE;
3111 	  match = rule;
3112 	}
3113     }
3114   if (!match)
3115     return FALSE;
3116 
3117   if (targ)
3118     xg_build_to_insn (targ, insn, match->to_instr);
3119   return TRUE;
3120 }
3121 
3122 
3123 /* Return the maximum number of bytes this opcode can expand to.  */
3124 
3125 static int
xg_get_max_insn_widen_size(xtensa_opcode opcode)3126 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3127 {
3128   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3129   TransitionList *l;
3130   int max_size = xg_get_single_size (opcode);
3131 
3132   gas_assert (opcode < table->num_opcodes);
3133 
3134   for (l = table->table[opcode]; l != NULL; l = l->next)
3135     {
3136       TransitionRule *rule = l->rule;
3137       BuildInstr *build_list;
3138       int this_size = 0;
3139 
3140       if (!rule)
3141 	continue;
3142       build_list = rule->to_instr;
3143       if (is_unique_insn_expansion (rule))
3144 	{
3145 	  gas_assert (build_list->typ == INSTR_INSTR);
3146 	  this_size = xg_get_max_insn_widen_size (build_list->opcode);
3147 	}
3148       else
3149 	for (; build_list != NULL; build_list = build_list->next)
3150 	  {
3151 	    switch (build_list->typ)
3152 	      {
3153 	      case INSTR_INSTR:
3154 		this_size += xg_get_single_size (build_list->opcode);
3155 		break;
3156 	      case INSTR_LITERAL_DEF:
3157 	      case INSTR_LABEL_DEF:
3158 	      default:
3159 		break;
3160 	      }
3161 	  }
3162       if (this_size > max_size)
3163 	max_size = this_size;
3164     }
3165   return max_size;
3166 }
3167 
3168 
3169 /* Return the maximum number of literal bytes this opcode can generate.  */
3170 
3171 static int
xg_get_max_insn_widen_literal_size(xtensa_opcode opcode)3172 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3173 {
3174   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3175   TransitionList *l;
3176   int max_size = 0;
3177 
3178   gas_assert (opcode < table->num_opcodes);
3179 
3180   for (l = table->table[opcode]; l != NULL; l = l->next)
3181     {
3182       TransitionRule *rule = l->rule;
3183       BuildInstr *build_list;
3184       int this_size = 0;
3185 
3186       if (!rule)
3187 	continue;
3188       build_list = rule->to_instr;
3189       if (is_unique_insn_expansion (rule))
3190 	{
3191 	  gas_assert (build_list->typ == INSTR_INSTR);
3192 	  this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3193 	}
3194       else
3195 	for (; build_list != NULL; build_list = build_list->next)
3196 	  {
3197 	    switch (build_list->typ)
3198 	      {
3199 	      case INSTR_LITERAL_DEF:
3200 		/* Hard-coded 4-byte literal.  */
3201 		this_size += 4;
3202 		break;
3203 	      case INSTR_INSTR:
3204 	      case INSTR_LABEL_DEF:
3205 	      default:
3206 		break;
3207 	      }
3208 	  }
3209       if (this_size > max_size)
3210 	max_size = this_size;
3211     }
3212   return max_size;
3213 }
3214 
3215 
3216 static bfd_boolean
xg_is_relaxable_insn(TInsn * insn,int lateral_steps)3217 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3218 {
3219   int steps_taken = 0;
3220   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3221   TransitionList *l;
3222 
3223   gas_assert (insn->insn_type == ITYPE_INSN);
3224   gas_assert (insn->opcode < table->num_opcodes);
3225 
3226   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3227     {
3228       TransitionRule *rule = l->rule;
3229 
3230       if (xg_instruction_matches_rule (insn, rule))
3231 	{
3232 	  if (steps_taken == lateral_steps)
3233 	    return TRUE;
3234 	  steps_taken++;
3235 	}
3236     }
3237   return FALSE;
3238 }
3239 
3240 
3241 static symbolS *
get_special_literal_symbol(void)3242 get_special_literal_symbol (void)
3243 {
3244   static symbolS *sym = NULL;
3245 
3246   if (sym == NULL)
3247     sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3248   return sym;
3249 }
3250 
3251 
3252 static symbolS *
get_special_label_symbol(void)3253 get_special_label_symbol (void)
3254 {
3255   static symbolS *sym = NULL;
3256 
3257   if (sym == NULL)
3258     sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3259   return sym;
3260 }
3261 
3262 
3263 static bfd_boolean
xg_valid_literal_expression(const expressionS * exp)3264 xg_valid_literal_expression (const expressionS *exp)
3265 {
3266   switch (exp->X_op)
3267     {
3268     case O_constant:
3269     case O_symbol:
3270     case O_big:
3271     case O_uminus:
3272     case O_subtract:
3273     case O_pltrel:
3274     case O_pcrel:
3275     case O_tlsfunc:
3276     case O_tlsarg:
3277     case O_tpoff:
3278     case O_dtpoff:
3279       return TRUE;
3280     default:
3281       return FALSE;
3282     }
3283 }
3284 
3285 
3286 /* This will check to see if the value can be converted into the
3287    operand type.  It will return TRUE if it does not fit.  */
3288 
3289 static bfd_boolean
xg_check_operand(int32 value,xtensa_opcode opcode,int operand)3290 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3291 {
3292   uint32 valbuf = value;
3293   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3294     return TRUE;
3295   return FALSE;
3296 }
3297 
3298 
3299 /* Assumes: All immeds are constants.  Check that all constants fit
3300    into their immeds; return FALSE if not.  */
3301 
3302 static bfd_boolean
xg_immeds_fit(const TInsn * insn)3303 xg_immeds_fit (const TInsn *insn)
3304 {
3305   xtensa_isa isa = xtensa_default_isa;
3306   int i;
3307 
3308   int n = insn->ntok;
3309   gas_assert (insn->insn_type == ITYPE_INSN);
3310   for (i = 0; i < n; ++i)
3311     {
3312       const expressionS *exp = &insn->tok[i];
3313 
3314       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3315 	continue;
3316 
3317       switch (exp->X_op)
3318 	{
3319 	case O_register:
3320 	case O_constant:
3321 	  if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3322 	    return FALSE;
3323 	  break;
3324 
3325 	default:
3326 	  /* The symbol should have a fixup associated with it.  */
3327 	  gas_assert (FALSE);
3328 	  break;
3329 	}
3330     }
3331   return TRUE;
3332 }
3333 
3334 
3335 /* This should only be called after we have an initial
3336    estimate of the addresses.  */
3337 
3338 static bfd_boolean
xg_symbolic_immeds_fit(const TInsn * insn,segT pc_seg,fragS * pc_frag,offsetT pc_offset,long stretch)3339 xg_symbolic_immeds_fit (const TInsn *insn,
3340 			segT pc_seg,
3341 			fragS *pc_frag,
3342 			offsetT pc_offset,
3343 			long stretch)
3344 {
3345   xtensa_isa isa = xtensa_default_isa;
3346   symbolS *symbolP;
3347   fragS *sym_frag;
3348   offsetT target, pc;
3349   uint32 new_offset;
3350   int i;
3351   int n = insn->ntok;
3352 
3353   gas_assert (insn->insn_type == ITYPE_INSN);
3354 
3355   for (i = 0; i < n; ++i)
3356     {
3357       const expressionS *exp = &insn->tok[i];
3358 
3359       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3360 	continue;
3361 
3362       switch (exp->X_op)
3363 	{
3364 	case O_register:
3365 	case O_constant:
3366 	  if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3367 	    return FALSE;
3368 	  break;
3369 
3370 	case O_lo16:
3371 	case O_hi16:
3372 	  /* Check for the worst case.  */
3373 	  if (xg_check_operand (0xffff, insn->opcode, i))
3374 	    return FALSE;
3375 	  break;
3376 
3377 	case O_symbol:
3378 	  /* We only allow symbols for PC-relative references.
3379 	     If pc_frag == 0, then we don't have frag locations yet.  */
3380 	  if (pc_frag == 0
3381 	      || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
3382 	    return FALSE;
3383 
3384 	  /* If it is a weak symbol or a symbol in a different section,
3385 	     it cannot be known to fit at assembly time.  */
3386 	  if (S_IS_WEAK (exp->X_add_symbol)
3387 	      || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg)
3388 	    {
3389 	      /* For a direct call with --no-longcalls, be optimistic and
3390 		 assume it will be in range.  If the symbol is weak and
3391 		 undefined, it may remain undefined at link-time, in which
3392 		 case it will have a zero value and almost certainly be out
3393 		 of range for a direct call; thus, relax for undefined weak
3394 		 symbols even if longcalls is not enabled.  */
3395 	      if (is_direct_call_opcode (insn->opcode)
3396 		  && ! pc_frag->tc_frag_data.use_longcalls
3397 		  && (! S_IS_WEAK (exp->X_add_symbol)
3398 		      || S_IS_DEFINED (exp->X_add_symbol)))
3399 		return TRUE;
3400 
3401 	      return FALSE;
3402 	    }
3403 
3404 	  symbolP = exp->X_add_symbol;
3405 	  sym_frag = symbol_get_frag (symbolP);
3406 	  target = S_GET_VALUE (symbolP) + exp->X_add_number;
3407 	  pc = pc_frag->fr_address + pc_offset;
3408 
3409 	  /* If frag has yet to be reached on this pass, assume it
3410 	     will move by STRETCH just as we did.  If this is not so,
3411 	     it will be because some frag between grows, and that will
3412 	     force another pass.  Beware zero-length frags.  There
3413 	     should be a faster way to do this.  */
3414 
3415 	  if (stretch != 0
3416 	      && sym_frag->relax_marker != pc_frag->relax_marker
3417 	      && S_GET_SEGMENT (symbolP) == pc_seg)
3418 	    {
3419 	      target += stretch;
3420 	    }
3421 
3422 	  new_offset = target;
3423 	  xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3424 	  if (xg_check_operand (new_offset, insn->opcode, i))
3425 	    return FALSE;
3426 	  break;
3427 
3428 	default:
3429 	  /* The symbol should have a fixup associated with it.  */
3430 	  return FALSE;
3431 	}
3432     }
3433 
3434   return TRUE;
3435 }
3436 
3437 
3438 /* Return TRUE on success.  */
3439 
3440 static bfd_boolean
xg_build_to_insn(TInsn * targ,TInsn * insn,BuildInstr * bi)3441 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3442 {
3443   BuildOp *op;
3444   symbolS *sym;
3445 
3446   tinsn_init (targ);
3447   targ->debug_line = insn->debug_line;
3448   targ->loc_directive_seen = insn->loc_directive_seen;
3449   switch (bi->typ)
3450     {
3451     case INSTR_INSTR:
3452       op = bi->ops;
3453       targ->opcode = bi->opcode;
3454       targ->insn_type = ITYPE_INSN;
3455       targ->is_specific_opcode = FALSE;
3456 
3457       for (; op != NULL; op = op->next)
3458 	{
3459 	  int op_num = op->op_num;
3460 	  int op_data = op->op_data;
3461 
3462 	  gas_assert (op->op_num < MAX_INSN_ARGS);
3463 
3464 	  if (targ->ntok <= op_num)
3465 	    targ->ntok = op_num + 1;
3466 
3467 	  switch (op->typ)
3468 	    {
3469 	    case OP_CONSTANT:
3470 	      set_expr_const (&targ->tok[op_num], op_data);
3471 	      break;
3472 	    case OP_OPERAND:
3473 	      gas_assert (op_data < insn->ntok);
3474 	      copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3475 	      break;
3476 	    case OP_FREEREG:
3477 	      if (insn->extra_arg.X_op != O_register)
3478 		return FALSE;
3479 	      copy_expr (&targ->tok[op_num], &insn->extra_arg);
3480 	      break;
3481 	    case OP_LITERAL:
3482 	      sym = get_special_literal_symbol ();
3483 	      set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3484 	      if (insn->tok[op_data].X_op == O_tlsfunc
3485 		  || insn->tok[op_data].X_op == O_tlsarg)
3486 		copy_expr (&targ->extra_arg, &insn->tok[op_data]);
3487 	      break;
3488 	    case OP_LABEL:
3489 	      sym = get_special_label_symbol ();
3490 	      set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3491 	      break;
3492 	    case OP_OPERAND_HI16U:
3493 	    case OP_OPERAND_LOW16U:
3494 	      gas_assert (op_data < insn->ntok);
3495 	      if (expr_is_const (&insn->tok[op_data]))
3496 		{
3497 		  long val;
3498 		  copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3499 		  val = xg_apply_userdef_op_fn (op->typ,
3500 						targ->tok[op_num].
3501 						X_add_number);
3502 		  targ->tok[op_num].X_add_number = val;
3503 		}
3504 	      else
3505 		{
3506 		  /* For const16 we can create relocations for these.  */
3507 		  if (targ->opcode == XTENSA_UNDEFINED
3508 		      || (targ->opcode != xtensa_const16_opcode))
3509 		    return FALSE;
3510 		  gas_assert (op_data < insn->ntok);
3511 		  /* Need to build a O_lo16 or O_hi16.  */
3512 		  copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3513 		  if (targ->tok[op_num].X_op == O_symbol)
3514 		    {
3515 		      if (op->typ == OP_OPERAND_HI16U)
3516 			targ->tok[op_num].X_op = O_hi16;
3517 		      else if (op->typ == OP_OPERAND_LOW16U)
3518 			targ->tok[op_num].X_op = O_lo16;
3519 		      else
3520 			return FALSE;
3521 		    }
3522 		}
3523 	      break;
3524 	    default:
3525 	      /* currently handles:
3526 		 OP_OPERAND_LOW8
3527 		 OP_OPERAND_HI24S
3528 		 OP_OPERAND_F32MINUS */
3529 	      if (xg_has_userdef_op_fn (op->typ))
3530 		{
3531 		  gas_assert (op_data < insn->ntok);
3532 		  if (expr_is_const (&insn->tok[op_data]))
3533 		    {
3534 		      long val;
3535 		      copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3536 		      val = xg_apply_userdef_op_fn (op->typ,
3537 						    targ->tok[op_num].
3538 						    X_add_number);
3539 		      targ->tok[op_num].X_add_number = val;
3540 		    }
3541 		  else
3542 		    return FALSE; /* We cannot use a relocation for this.  */
3543 		  break;
3544 		}
3545 	      gas_assert (0);
3546 	      break;
3547 	    }
3548 	}
3549       break;
3550 
3551     case INSTR_LITERAL_DEF:
3552       op = bi->ops;
3553       targ->opcode = XTENSA_UNDEFINED;
3554       targ->insn_type = ITYPE_LITERAL;
3555       targ->is_specific_opcode = FALSE;
3556       for (; op != NULL; op = op->next)
3557 	{
3558 	  int op_num = op->op_num;
3559 	  int op_data = op->op_data;
3560 	  gas_assert (op->op_num < MAX_INSN_ARGS);
3561 
3562 	  if (targ->ntok <= op_num)
3563 	    targ->ntok = op_num + 1;
3564 
3565 	  switch (op->typ)
3566 	    {
3567 	    case OP_OPERAND:
3568 	      gas_assert (op_data < insn->ntok);
3569 	      /* We can only pass resolvable literals through.  */
3570 	      if (!xg_valid_literal_expression (&insn->tok[op_data]))
3571 		return FALSE;
3572 	      copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3573 	      break;
3574 	    case OP_LITERAL:
3575 	    case OP_CONSTANT:
3576 	    case OP_LABEL:
3577 	    default:
3578 	      gas_assert (0);
3579 	      break;
3580 	    }
3581 	}
3582       break;
3583 
3584     case INSTR_LABEL_DEF:
3585       op = bi->ops;
3586       targ->opcode = XTENSA_UNDEFINED;
3587       targ->insn_type = ITYPE_LABEL;
3588       targ->is_specific_opcode = FALSE;
3589       /* Literal with no ops is a label?  */
3590       gas_assert (op == NULL);
3591       break;
3592 
3593     default:
3594       gas_assert (0);
3595     }
3596 
3597   return TRUE;
3598 }
3599 
3600 
3601 /* Return TRUE on success.  */
3602 
3603 static bfd_boolean
xg_build_to_stack(IStack * istack,TInsn * insn,BuildInstr * bi)3604 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3605 {
3606   for (; bi != NULL; bi = bi->next)
3607     {
3608       TInsn *next_insn = istack_push_space (istack);
3609 
3610       if (!xg_build_to_insn (next_insn, insn, bi))
3611 	return FALSE;
3612     }
3613   return TRUE;
3614 }
3615 
3616 
3617 /* Return TRUE on valid expansion.  */
3618 
3619 static bfd_boolean
xg_expand_to_stack(IStack * istack,TInsn * insn,int lateral_steps)3620 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3621 {
3622   int stack_size = istack->ninsn;
3623   int steps_taken = 0;
3624   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3625   TransitionList *l;
3626 
3627   gas_assert (insn->insn_type == ITYPE_INSN);
3628   gas_assert (insn->opcode < table->num_opcodes);
3629 
3630   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3631     {
3632       TransitionRule *rule = l->rule;
3633 
3634       if (xg_instruction_matches_rule (insn, rule))
3635 	{
3636 	  if (lateral_steps == steps_taken)
3637 	    {
3638 	      int i;
3639 
3640 	      /* This is it.  Expand the rule to the stack.  */
3641 	      if (!xg_build_to_stack (istack, insn, rule->to_instr))
3642 		return FALSE;
3643 
3644 	      /* Check to see if it fits.  */
3645 	      for (i = stack_size; i < istack->ninsn; i++)
3646 		{
3647 		  TInsn *tinsn = &istack->insn[i];
3648 
3649 		  if (tinsn->insn_type == ITYPE_INSN
3650 		      && !tinsn_has_symbolic_operands (tinsn)
3651 		      && !xg_immeds_fit (tinsn))
3652 		    {
3653 		      istack->ninsn = stack_size;
3654 		      return FALSE;
3655 		    }
3656 		}
3657 	      return TRUE;
3658 	    }
3659 	  steps_taken++;
3660 	}
3661     }
3662   return FALSE;
3663 }
3664 
3665 
3666 /* Relax the assembly instruction at least "min_steps".
3667    Return the number of steps taken.
3668 
3669    For relaxation to correctly terminate, every relaxation chain must
3670    terminate in one of two ways:
3671 
3672    1.  If the chain from one instruction to the next consists entirely of
3673        single instructions, then the chain *must* handle all possible
3674        immediates without failing.  It must not ever fail because an
3675        immediate is out of range.  The MOVI.N -> MOVI -> L32R relaxation
3676        chain is one example.  L32R loads 32 bits, and there cannot be an
3677        immediate larger than 32 bits, so it satisfies this condition.
3678        Single instruction relaxation chains are as defined by
3679        xg_is_single_relaxable_instruction.
3680 
3681    2.  Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3682        BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3683 
3684    Strictly speaking, in most cases you can violate condition 1 and be OK
3685    -- in particular when the last two instructions have the same single
3686    size.  But nevertheless, you should guarantee the above two conditions.
3687 
3688    We could fix this so that single-instruction expansions correctly
3689    terminate when they can't handle the range, but the error messages are
3690    worse, and it actually turns out that in every case but one (18-bit wide
3691    branches), you need a multi-instruction expansion to get the full range
3692    anyway.  And because 18-bit branches are handled identically to 15-bit
3693    branches, there isn't any point in changing it.  */
3694 
3695 static int
xg_assembly_relax(IStack * istack,TInsn * insn,segT pc_seg,fragS * pc_frag,offsetT pc_offset,int min_steps,long stretch)3696 xg_assembly_relax (IStack *istack,
3697 		   TInsn *insn,
3698 		   segT pc_seg,
3699 		   fragS *pc_frag,	/* if pc_frag == 0, not pc-relative */
3700 		   offsetT pc_offset,	/* offset in fragment */
3701 		   int min_steps,	/* minimum conversion steps */
3702 		   long stretch)	/* number of bytes stretched so far */
3703 {
3704   int steps_taken = 0;
3705 
3706   /* Some of its immeds don't fit.  Try to build a relaxed version.
3707      This may go through a couple of stages of single instruction
3708      transformations before we get there.  */
3709 
3710   TInsn single_target;
3711   TInsn current_insn;
3712   int lateral_steps = 0;
3713   int istack_size = istack->ninsn;
3714 
3715   if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3716       && steps_taken >= min_steps)
3717     {
3718       istack_push (istack, insn);
3719       return steps_taken;
3720     }
3721   current_insn = *insn;
3722 
3723   /* Walk through all of the single instruction expansions.  */
3724   while (xg_is_single_relaxable_insn (&current_insn, &single_target, FALSE))
3725     {
3726       steps_taken++;
3727       if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3728 				  stretch))
3729 	{
3730 	  if (steps_taken >= min_steps)
3731 	    {
3732 	      istack_push (istack, &single_target);
3733 	      return steps_taken;
3734 	    }
3735 	}
3736       current_insn = single_target;
3737     }
3738 
3739   /* Now check for a multi-instruction expansion.  */
3740   while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3741     {
3742       if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3743 				  stretch))
3744 	{
3745 	  if (steps_taken >= min_steps)
3746 	    {
3747 	      istack_push (istack, &current_insn);
3748 	      return steps_taken;
3749 	    }
3750 	}
3751       steps_taken++;
3752       if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3753 	{
3754 	  if (steps_taken >= min_steps)
3755 	    return steps_taken;
3756 	}
3757       lateral_steps++;
3758       istack->ninsn = istack_size;
3759     }
3760 
3761   /* It's not going to work -- use the original.  */
3762   istack_push (istack, insn);
3763   return steps_taken;
3764 }
3765 
3766 
3767 static void
xg_finish_frag(char * last_insn,enum xtensa_relax_statesE frag_state,enum xtensa_relax_statesE slot0_state,int max_growth,bfd_boolean is_insn)3768 xg_finish_frag (char *last_insn,
3769 		enum xtensa_relax_statesE frag_state,
3770 		enum xtensa_relax_statesE slot0_state,
3771 		int max_growth,
3772 		bfd_boolean is_insn)
3773 {
3774   /* Finish off this fragment so that it has at LEAST the desired
3775      max_growth.  If it doesn't fit in this fragment, close this one
3776      and start a new one.  In either case, return a pointer to the
3777      beginning of the growth area.  */
3778 
3779   fragS *old_frag;
3780 
3781   frag_grow (max_growth);
3782   old_frag = frag_now;
3783 
3784   frag_now->fr_opcode = last_insn;
3785   if (is_insn)
3786     frag_now->tc_frag_data.is_insn = TRUE;
3787 
3788   frag_var (rs_machine_dependent, max_growth, max_growth,
3789 	    frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3790 
3791   old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3792   xtensa_set_frag_assembly_state (frag_now);
3793 
3794   /* Just to make sure that we did not split it up.  */
3795   gas_assert (old_frag->fr_next == frag_now);
3796 }
3797 
3798 
3799 /* Return TRUE if the target frag is one of the next non-empty frags.  */
3800 
3801 static bfd_boolean
is_next_frag_target(const fragS * fragP,const fragS * target)3802 is_next_frag_target (const fragS *fragP, const fragS *target)
3803 {
3804   if (fragP == NULL)
3805     return FALSE;
3806 
3807   for (; fragP; fragP = fragP->fr_next)
3808     {
3809       if (fragP == target)
3810 	return TRUE;
3811       if (fragP->fr_fix != 0)
3812 	return FALSE;
3813       if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3814 	return FALSE;
3815       if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3816 	  && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3817 	return FALSE;
3818       if (fragP->fr_type == rs_space)
3819 	return FALSE;
3820     }
3821   return FALSE;
3822 }
3823 
3824 
3825 static bfd_boolean
is_branch_jmp_to_next(TInsn * insn,fragS * fragP)3826 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3827 {
3828   xtensa_isa isa = xtensa_default_isa;
3829   int i;
3830   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3831   int target_op = -1;
3832   symbolS *sym;
3833   fragS *target_frag;
3834 
3835   if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
3836       && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
3837     return FALSE;
3838 
3839   for (i = 0; i < num_ops; i++)
3840     {
3841       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3842 	{
3843 	  target_op = i;
3844 	  break;
3845 	}
3846     }
3847   if (target_op == -1)
3848     return FALSE;
3849 
3850   if (insn->ntok <= target_op)
3851     return FALSE;
3852 
3853   if (insn->tok[target_op].X_op != O_symbol)
3854     return FALSE;
3855 
3856   sym = insn->tok[target_op].X_add_symbol;
3857   if (sym == NULL)
3858     return FALSE;
3859 
3860   if (insn->tok[target_op].X_add_number != 0)
3861     return FALSE;
3862 
3863   target_frag = symbol_get_frag (sym);
3864   if (target_frag == NULL)
3865     return FALSE;
3866 
3867   if (is_next_frag_target (fragP->fr_next, target_frag)
3868       && S_GET_VALUE (sym) == target_frag->fr_address)
3869     return TRUE;
3870 
3871   return FALSE;
3872 }
3873 
3874 
3875 static void
xg_add_branch_and_loop_targets(TInsn * insn)3876 xg_add_branch_and_loop_targets (TInsn *insn)
3877 {
3878   xtensa_isa isa = xtensa_default_isa;
3879   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3880 
3881   if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3882     {
3883       int i = 1;
3884       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3885 	  && insn->tok[i].X_op == O_symbol)
3886 	symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3887       return;
3888     }
3889 
3890   if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3891       || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3892     {
3893       int i;
3894 
3895       for (i = 0; i < insn->ntok && i < num_ops; i++)
3896 	{
3897 	  if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3898 	      && insn->tok[i].X_op == O_symbol)
3899 	    {
3900 	      symbolS *sym = insn->tok[i].X_add_symbol;
3901 	      symbol_get_tc (sym)->is_branch_target = TRUE;
3902 	      if (S_IS_DEFINED (sym))
3903 		symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3904 	    }
3905 	}
3906     }
3907 }
3908 
3909 
3910 /* Return FALSE if no error.  */
3911 
3912 static bfd_boolean
xg_build_token_insn(BuildInstr * instr_spec,TInsn * old_insn,TInsn * new_insn)3913 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3914 {
3915   int num_ops = 0;
3916   BuildOp *b_op;
3917 
3918   switch (instr_spec->typ)
3919     {
3920     case INSTR_INSTR:
3921       new_insn->insn_type = ITYPE_INSN;
3922       new_insn->opcode = instr_spec->opcode;
3923       break;
3924     case INSTR_LITERAL_DEF:
3925       new_insn->insn_type = ITYPE_LITERAL;
3926       new_insn->opcode = XTENSA_UNDEFINED;
3927       break;
3928     case INSTR_LABEL_DEF:
3929       abort ();
3930     }
3931   new_insn->is_specific_opcode = FALSE;
3932   new_insn->debug_line = old_insn->debug_line;
3933   new_insn->loc_directive_seen = old_insn->loc_directive_seen;
3934 
3935   for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3936     {
3937       expressionS *exp;
3938       const expressionS *src_exp;
3939 
3940       num_ops++;
3941       switch (b_op->typ)
3942 	{
3943 	case OP_CONSTANT:
3944 	  /* The expression must be the constant.  */
3945 	  gas_assert (b_op->op_num < MAX_INSN_ARGS);
3946 	  exp = &new_insn->tok[b_op->op_num];
3947 	  set_expr_const (exp, b_op->op_data);
3948 	  break;
3949 
3950 	case OP_OPERAND:
3951 	  gas_assert (b_op->op_num < MAX_INSN_ARGS);
3952 	  gas_assert (b_op->op_data < (unsigned) old_insn->ntok);
3953 	  src_exp = &old_insn->tok[b_op->op_data];
3954 	  exp = &new_insn->tok[b_op->op_num];
3955 	  copy_expr (exp, src_exp);
3956 	  break;
3957 
3958 	case OP_LITERAL:
3959 	case OP_LABEL:
3960 	  as_bad (_("can't handle generation of literal/labels yet"));
3961 	  gas_assert (0);
3962 
3963 	default:
3964 	  as_bad (_("can't handle undefined OP TYPE"));
3965 	  gas_assert (0);
3966 	}
3967     }
3968 
3969   new_insn->ntok = num_ops;
3970   return FALSE;
3971 }
3972 
3973 
3974 /* Return TRUE if it was simplified.  */
3975 
3976 static bfd_boolean
xg_simplify_insn(TInsn * old_insn,TInsn * new_insn)3977 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
3978 {
3979   TransitionRule *rule;
3980   BuildInstr *insn_spec;
3981 
3982   if (old_insn->is_specific_opcode || !density_supported)
3983     return FALSE;
3984 
3985   rule = xg_instruction_match (old_insn);
3986   if (rule == NULL)
3987     return FALSE;
3988 
3989   insn_spec = rule->to_instr;
3990   /* There should only be one.  */
3991   gas_assert (insn_spec != NULL);
3992   gas_assert (insn_spec->next == NULL);
3993   if (insn_spec->next != NULL)
3994     return FALSE;
3995 
3996   xg_build_token_insn (insn_spec, old_insn, new_insn);
3997 
3998   return TRUE;
3999 }
4000 
4001 
4002 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4003    l32i.n. (2) Check the number of operands.  (3) Place the instruction
4004    tokens into the stack or relax it and place multiple
4005    instructions/literals onto the stack.  Return FALSE if no error.  */
4006 
4007 static bfd_boolean
xg_expand_assembly_insn(IStack * istack,TInsn * orig_insn)4008 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
4009 {
4010   int noperands;
4011   TInsn new_insn;
4012   bfd_boolean do_expand;
4013 
4014   tinsn_init (&new_insn);
4015 
4016   /* Narrow it if we can.  xg_simplify_insn now does all the
4017      appropriate checking (e.g., for the density option).  */
4018   if (xg_simplify_insn (orig_insn, &new_insn))
4019     orig_insn = &new_insn;
4020 
4021   noperands = xtensa_opcode_num_operands (xtensa_default_isa,
4022 					  orig_insn->opcode);
4023   if (orig_insn->ntok < noperands)
4024     {
4025       as_bad (_("found %d operands for '%s':  Expected %d"),
4026 	      orig_insn->ntok,
4027 	      xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4028 	      noperands);
4029       return TRUE;
4030     }
4031   if (orig_insn->ntok > noperands)
4032     as_warn (_("found too many (%d) operands for '%s':  Expected %d"),
4033 	     orig_insn->ntok,
4034 	     xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4035 	     noperands);
4036 
4037   /* If there are not enough operands, we will assert above.  If there
4038      are too many, just cut out the extras here.  */
4039   orig_insn->ntok = noperands;
4040 
4041   if (tinsn_has_invalid_symbolic_operands (orig_insn))
4042     return TRUE;
4043 
4044   /* Special case for extui opcode which has constraints not handled
4045      by the ordinary operand encoding checks.  The number of operands
4046      and related syntax issues have already been checked.  */
4047   if (orig_insn->opcode == xtensa_extui_opcode)
4048     {
4049       int shiftimm = orig_insn->tok[2].X_add_number;
4050       int maskimm = orig_insn->tok[3].X_add_number;
4051       if (shiftimm + maskimm > 32)
4052 	{
4053 	  as_bad (_("immediate operands sum to greater than 32"));
4054 	  return TRUE;
4055 	}
4056     }
4057 
4058   /* If the instruction will definitely need to be relaxed, it is better
4059      to expand it now for better scheduling.  Decide whether to expand
4060      now....  */
4061   do_expand = (!orig_insn->is_specific_opcode && use_transform ());
4062 
4063   /* Calls should be expanded to longcalls only in the backend relaxation
4064      so that the assembly scheduler will keep the L32R/CALLX instructions
4065      adjacent.  */
4066   if (is_direct_call_opcode (orig_insn->opcode))
4067     do_expand = FALSE;
4068 
4069   if (tinsn_has_symbolic_operands (orig_insn))
4070     {
4071       /* The values of symbolic operands are not known yet, so only expand
4072 	 now if an operand is "complex" (e.g., difference of symbols) and
4073 	 will have to be stored as a literal regardless of the value.  */
4074       if (!tinsn_has_complex_operands (orig_insn))
4075 	do_expand = FALSE;
4076     }
4077   else if (xg_immeds_fit (orig_insn))
4078     do_expand = FALSE;
4079 
4080   if (do_expand)
4081     xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4082   else
4083     istack_push (istack, orig_insn);
4084 
4085   return FALSE;
4086 }
4087 
4088 
4089 /* Return TRUE if the section flags are marked linkonce
4090    or the name is .gnu.linkonce.*.  */
4091 
4092 static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
4093 
4094 static bfd_boolean
get_is_linkonce_section(bfd * abfd ATTRIBUTE_UNUSED,segT sec)4095 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4096 {
4097   flagword flags, link_once_flags;
4098 
4099   flags = bfd_get_section_flags (abfd, sec);
4100   link_once_flags = (flags & SEC_LINK_ONCE);
4101 
4102   /* Flags might not be set yet.  */
4103   if (!link_once_flags
4104       && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
4105     link_once_flags = SEC_LINK_ONCE;
4106 
4107   return (link_once_flags != 0);
4108 }
4109 
4110 
4111 static void
xtensa_add_literal_sym(symbolS * sym)4112 xtensa_add_literal_sym (symbolS *sym)
4113 {
4114   sym_list *l;
4115 
4116   l = XNEW (sym_list);
4117   l->sym = sym;
4118   l->next = literal_syms;
4119   literal_syms = l;
4120 }
4121 
4122 
4123 static symbolS *
xtensa_create_literal_symbol(segT sec,fragS * frag)4124 xtensa_create_literal_symbol (segT sec, fragS *frag)
4125 {
4126   static int lit_num = 0;
4127   static char name[256];
4128   symbolS *symbolP;
4129 
4130   sprintf (name, ".L_lit_sym%d", lit_num);
4131 
4132   /* Create a local symbol.  If it is in a linkonce section, we have to
4133      be careful to make sure that if it is used in a relocation that the
4134      symbol will be in the output file.  */
4135   if (get_is_linkonce_section (stdoutput, sec))
4136     {
4137       symbolP = symbol_new (name, sec, 0, frag);
4138       S_CLEAR_EXTERNAL (symbolP);
4139       /* symbolP->local = 1; */
4140     }
4141   else
4142     symbolP = symbol_new (name, sec, 0, frag);
4143 
4144   xtensa_add_literal_sym (symbolP);
4145 
4146   lit_num++;
4147   return symbolP;
4148 }
4149 
4150 
4151 /* Currently all literals that are generated here are 32-bit L32R targets.  */
4152 
4153 static symbolS *
xg_assemble_literal(TInsn * insn)4154 xg_assemble_literal (/* const */ TInsn *insn)
4155 {
4156   emit_state state;
4157   symbolS *lit_sym = NULL;
4158   bfd_reloc_code_real_type reloc;
4159   bfd_boolean pcrel = FALSE;
4160   char *p;
4161 
4162   /* size = 4 for L32R.  It could easily be larger when we move to
4163      larger constants.  Add a parameter later.  */
4164   offsetT litsize = 4;
4165   offsetT litalign = 2;		/* 2^2 = 4 */
4166   expressionS saved_loc;
4167   expressionS * emit_val;
4168 
4169   set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4170 
4171   gas_assert (insn->insn_type == ITYPE_LITERAL);
4172   gas_assert (insn->ntok == 1);	/* must be only one token here */
4173 
4174   xtensa_switch_to_literal_fragment (&state);
4175 
4176   emit_val = &insn->tok[0];
4177   if (emit_val->X_op == O_big)
4178     {
4179       int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4180       if (size > litsize)
4181 	{
4182 	  /* This happens when someone writes a "movi a2, big_number".  */
4183 	  as_bad_where (frag_now->fr_file, frag_now->fr_line,
4184 			_("invalid immediate"));
4185 	  xtensa_restore_emit_state (&state);
4186 	  return NULL;
4187 	}
4188     }
4189 
4190   /* Force a 4-byte align here.  Note that this opens a new frag, so all
4191      literals done with this function have a frag to themselves.  That's
4192      important for the way text section literals work.  */
4193   frag_align (litalign, 0, 0);
4194   record_alignment (now_seg, litalign);
4195 
4196   switch (emit_val->X_op)
4197     {
4198     case O_pcrel:
4199       pcrel = TRUE;
4200       /* fall through */
4201     case O_pltrel:
4202     case O_tlsfunc:
4203     case O_tlsarg:
4204     case O_tpoff:
4205     case O_dtpoff:
4206       p = frag_more (litsize);
4207       xtensa_set_frag_assembly_state (frag_now);
4208       reloc = map_operator_to_reloc (emit_val->X_op, TRUE);
4209       if (emit_val->X_add_symbol)
4210 	emit_val->X_op = O_symbol;
4211       else
4212 	emit_val->X_op = O_constant;
4213       fix_new_exp (frag_now, p - frag_now->fr_literal,
4214 		   litsize, emit_val, pcrel, reloc);
4215       break;
4216 
4217     default:
4218       emit_expr (emit_val, litsize);
4219       break;
4220     }
4221 
4222   gas_assert (frag_now->tc_frag_data.literal_frag == NULL);
4223   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4224   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4225   lit_sym = frag_now->fr_symbol;
4226 
4227   /* Go back.  */
4228   xtensa_restore_emit_state (&state);
4229   return lit_sym;
4230 }
4231 
4232 
4233 static void
xg_assemble_literal_space(int size,int slot)4234 xg_assemble_literal_space (/* const */ int size, int slot)
4235 {
4236   emit_state state;
4237   /* We might have to do something about this alignment.  It only
4238      takes effect if something is placed here.  */
4239   offsetT litalign = 2;		/* 2^2 = 4 */
4240   fragS *lit_saved_frag;
4241 
4242   gas_assert (size % 4 == 0);
4243 
4244   xtensa_switch_to_literal_fragment (&state);
4245 
4246   /* Force a 4-byte align here.  */
4247   frag_align (litalign, 0, 0);
4248   record_alignment (now_seg, litalign);
4249 
4250   frag_grow (size);
4251 
4252   lit_saved_frag = frag_now;
4253   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4254   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4255   xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4256 
4257   /* Go back.  */
4258   xtensa_restore_emit_state (&state);
4259   frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4260 }
4261 
4262 
4263 /* Put in a fixup record based on the opcode.
4264    Return TRUE on success.  */
4265 
4266 static bfd_boolean
xg_add_opcode_fix(TInsn * tinsn,int opnum,xtensa_format fmt,int slot,expressionS * exp,fragS * fragP,offsetT offset)4267 xg_add_opcode_fix (TInsn *tinsn,
4268 		   int opnum,
4269 		   xtensa_format fmt,
4270 		   int slot,
4271 		   expressionS *exp,
4272 		   fragS *fragP,
4273 		   offsetT offset)
4274 {
4275   xtensa_opcode opcode = tinsn->opcode;
4276   bfd_reloc_code_real_type reloc;
4277   reloc_howto_type *howto;
4278   int fmt_length;
4279   fixS *the_fix;
4280 
4281   reloc = BFD_RELOC_NONE;
4282 
4283   /* First try the special cases for "alternate" relocs.  */
4284   if (opcode == xtensa_l32r_opcode)
4285     {
4286       if (fragP->tc_frag_data.use_absolute_literals)
4287 	reloc = encode_alt_reloc (slot);
4288     }
4289   else if (opcode == xtensa_const16_opcode)
4290     {
4291       if (exp->X_op == O_lo16)
4292 	{
4293 	  reloc = encode_reloc (slot);
4294 	  exp->X_op = O_symbol;
4295 	}
4296       else if (exp->X_op == O_hi16)
4297 	{
4298 	  reloc = encode_alt_reloc (slot);
4299 	  exp->X_op = O_symbol;
4300 	}
4301     }
4302 
4303   if (opnum != get_relaxable_immed (opcode))
4304     {
4305       as_bad (_("invalid relocation for operand %i of '%s'"),
4306 	      opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4307       return FALSE;
4308     }
4309 
4310   /* Handle erroneous "@h" and "@l" expressions here before they propagate
4311      into the symbol table where the generic portions of the assembler
4312      won't know what to do with them.  */
4313   if (exp->X_op == O_lo16 || exp->X_op == O_hi16)
4314     {
4315       as_bad (_("invalid expression for operand %i of '%s'"),
4316 	      opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4317       return FALSE;
4318     }
4319 
4320   /* Next try the generic relocs.  */
4321   if (reloc == BFD_RELOC_NONE)
4322     reloc = encode_reloc (slot);
4323   if (reloc == BFD_RELOC_NONE)
4324     {
4325       as_bad (_("invalid relocation in instruction slot %i"), slot);
4326       return FALSE;
4327     }
4328 
4329   howto = bfd_reloc_type_lookup (stdoutput, reloc);
4330   if (!howto)
4331     {
4332       as_bad (_("undefined symbol for opcode \"%s\""),
4333 	      xtensa_opcode_name (xtensa_default_isa, opcode));
4334       return FALSE;
4335     }
4336 
4337   fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4338   the_fix = fix_new_exp (fragP, offset, fmt_length, exp,
4339 			 howto->pc_relative, reloc);
4340   the_fix->fx_no_overflow = 1;
4341   the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol;
4342   the_fix->tc_fix_data.X_add_number = exp->X_add_number;
4343   the_fix->tc_fix_data.slot = slot;
4344 
4345   return TRUE;
4346 }
4347 
4348 
4349 static bfd_boolean
xg_emit_insn_to_buf(TInsn * tinsn,char * buf,fragS * fragP,offsetT offset,bfd_boolean build_fix)4350 xg_emit_insn_to_buf (TInsn *tinsn,
4351 		     char *buf,
4352 		     fragS *fragP,
4353 		     offsetT offset,
4354 		     bfd_boolean build_fix)
4355 {
4356   static xtensa_insnbuf insnbuf = NULL;
4357   bfd_boolean has_symbolic_immed = FALSE;
4358   bfd_boolean ok = TRUE;
4359 
4360   if (!insnbuf)
4361     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4362 
4363   has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4364   if (has_symbolic_immed && build_fix)
4365     {
4366       /* Add a fixup.  */
4367       xtensa_format fmt = xg_get_single_format (tinsn->opcode);
4368       int slot = xg_get_single_slot (tinsn->opcode);
4369       int opnum = get_relaxable_immed (tinsn->opcode);
4370       expressionS *exp = &tinsn->tok[opnum];
4371 
4372       if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
4373 	ok = FALSE;
4374     }
4375   fragP->tc_frag_data.is_insn = TRUE;
4376   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4377 			   (unsigned char *) buf, 0);
4378   return ok;
4379 }
4380 
4381 
4382 static void
xg_resolve_literals(TInsn * insn,symbolS * lit_sym)4383 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4384 {
4385   symbolS *sym = get_special_literal_symbol ();
4386   int i;
4387   if (lit_sym == 0)
4388     return;
4389   gas_assert (insn->insn_type == ITYPE_INSN);
4390   for (i = 0; i < insn->ntok; i++)
4391     if (insn->tok[i].X_add_symbol == sym)
4392       insn->tok[i].X_add_symbol = lit_sym;
4393 
4394 }
4395 
4396 
4397 static void
xg_resolve_labels(TInsn * insn,symbolS * label_sym)4398 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4399 {
4400   symbolS *sym = get_special_label_symbol ();
4401   int i;
4402   for (i = 0; i < insn->ntok; i++)
4403     if (insn->tok[i].X_add_symbol == sym)
4404       insn->tok[i].X_add_symbol = label_sym;
4405 
4406 }
4407 
4408 
4409 /* Return TRUE if the instruction can write to the specified
4410    integer register.  */
4411 
4412 static bfd_boolean
is_register_writer(const TInsn * insn,const char * regset,int regnum)4413 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4414 {
4415   int i;
4416   int num_ops;
4417   xtensa_isa isa = xtensa_default_isa;
4418 
4419   num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4420 
4421   for (i = 0; i < num_ops; i++)
4422     {
4423       char inout;
4424       inout = xtensa_operand_inout (isa, insn->opcode, i);
4425       if ((inout == 'o' || inout == 'm')
4426 	  && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4427 	{
4428 	  xtensa_regfile opnd_rf =
4429 	    xtensa_operand_regfile (isa, insn->opcode, i);
4430 	  if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4431 	    {
4432 	      if ((insn->tok[i].X_op == O_register)
4433 		  && (insn->tok[i].X_add_number == regnum))
4434 		return TRUE;
4435 	    }
4436 	}
4437     }
4438   return FALSE;
4439 }
4440 
4441 
4442 static bfd_boolean
is_bad_loopend_opcode(const TInsn * tinsn)4443 is_bad_loopend_opcode (const TInsn *tinsn)
4444 {
4445   xtensa_opcode opcode = tinsn->opcode;
4446 
4447   if (opcode == XTENSA_UNDEFINED)
4448     return FALSE;
4449 
4450   if (opcode == xtensa_call0_opcode
4451       || opcode == xtensa_callx0_opcode
4452       || opcode == xtensa_call4_opcode
4453       || opcode == xtensa_callx4_opcode
4454       || opcode == xtensa_call8_opcode
4455       || opcode == xtensa_callx8_opcode
4456       || opcode == xtensa_call12_opcode
4457       || opcode == xtensa_callx12_opcode
4458       || opcode == xtensa_isync_opcode
4459       || opcode == xtensa_ret_opcode
4460       || opcode == xtensa_ret_n_opcode
4461       || opcode == xtensa_retw_opcode
4462       || opcode == xtensa_retw_n_opcode
4463       || opcode == xtensa_waiti_opcode
4464       || opcode == xtensa_rsr_lcount_opcode)
4465     return TRUE;
4466 
4467   return FALSE;
4468 }
4469 
4470 
4471 /* Labels that begin with ".Ln" or ".LM"  are unaligned.
4472    This allows the debugger to add unaligned labels.
4473    Also, the assembler generates stabs labels that need
4474    not be aligned:  FAKE_LABEL_NAME . {"F", "L", "endfunc"}.  */
4475 
4476 static bfd_boolean
is_unaligned_label(symbolS * sym)4477 is_unaligned_label (symbolS *sym)
4478 {
4479   const char *name = S_GET_NAME (sym);
4480   static size_t fake_size = 0;
4481 
4482   if (name
4483       && name[0] == '.'
4484       && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4485     return TRUE;
4486 
4487   /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4488   if (fake_size == 0)
4489     fake_size = strlen (FAKE_LABEL_NAME);
4490 
4491   if (name
4492       && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4493       && (name[fake_size] == 'F'
4494 	  || name[fake_size] == 'L'
4495 	  || (name[fake_size] == 'e'
4496 	      && strncmp ("endfunc", name+fake_size, 7) == 0)))
4497     return TRUE;
4498 
4499   return FALSE;
4500 }
4501 
4502 
4503 static fragS *
next_non_empty_frag(const fragS * fragP)4504 next_non_empty_frag (const fragS *fragP)
4505 {
4506   fragS *next_fragP = fragP->fr_next;
4507 
4508   /* Sometimes an empty will end up here due storage allocation issues.
4509      So we have to skip until we find something legit.  */
4510   while (next_fragP && next_fragP->fr_fix == 0)
4511     next_fragP = next_fragP->fr_next;
4512 
4513   if (next_fragP == NULL || next_fragP->fr_fix == 0)
4514     return NULL;
4515 
4516   return next_fragP;
4517 }
4518 
4519 
4520 static bfd_boolean
next_frag_opcode_is_loop(const fragS * fragP,xtensa_opcode * opcode)4521 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4522 {
4523   xtensa_opcode out_opcode;
4524   const fragS *next_fragP = next_non_empty_frag (fragP);
4525 
4526   if (next_fragP == NULL)
4527     return FALSE;
4528 
4529   out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4530   if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4531     {
4532       *opcode = out_opcode;
4533       return TRUE;
4534     }
4535   return FALSE;
4536 }
4537 
4538 
4539 static int
frag_format_size(const fragS * fragP)4540 frag_format_size (const fragS *fragP)
4541 {
4542   static xtensa_insnbuf insnbuf = NULL;
4543   xtensa_isa isa = xtensa_default_isa;
4544   xtensa_format fmt;
4545   int fmt_size;
4546 
4547   if (!insnbuf)
4548     insnbuf = xtensa_insnbuf_alloc (isa);
4549 
4550   if (fragP == NULL)
4551     return XTENSA_UNDEFINED;
4552 
4553   xtensa_insnbuf_from_chars (isa, insnbuf,
4554 			     (unsigned char *) fragP->fr_literal, 0);
4555 
4556   fmt = xtensa_format_decode (isa, insnbuf);
4557   if (fmt == XTENSA_UNDEFINED)
4558     return XTENSA_UNDEFINED;
4559   fmt_size = xtensa_format_length (isa, fmt);
4560 
4561   /* If the next format won't be changing due to relaxation, just
4562      return the length of the first format.  */
4563   if (fragP->fr_opcode != fragP->fr_literal)
4564     return fmt_size;
4565 
4566   /* If during relaxation we have to pull an instruction out of a
4567      multi-slot instruction, we will return the more conservative
4568      number.  This works because alignment on bigger instructions
4569      is more restrictive than alignment on smaller instructions.
4570      This is more conservative than we would like, but it happens
4571      infrequently.  */
4572 
4573   if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4574     return fmt_size;
4575 
4576   /* If we aren't doing one of our own relaxations or it isn't
4577      slot-based, then the insn size won't change.  */
4578   if (fragP->fr_type != rs_machine_dependent)
4579     return fmt_size;
4580   if (fragP->fr_subtype != RELAX_SLOTS)
4581     return fmt_size;
4582 
4583   /* If an instruction is about to grow, return the longer size.  */
4584   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4585       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
4586       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
4587     {
4588       /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4589 	 instruction in the relaxed version is of length 3.  (The case
4590 	 where we have to pull the instruction out of a FLIX bundle
4591 	 is handled conservatively above.)  However, frags with opcodes
4592 	 that are expanding to wide branches end up having formats that
4593 	 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4594 	 we can't tell directly what format the relaxer picked.  This
4595 	 is a wart in the design of the relaxer that should someday be
4596 	 fixed, but would require major changes, or at least should
4597 	 be accompanied by major changes to make use of that data.
4598 
4599 	 In any event, we can tell that we are expanding from a single-slot
4600 	 format to a wider one with the logic below.  */
4601 
4602       int i;
4603       int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0];
4604 
4605       for (i = 0; i < xtensa_isa_num_formats (isa); i++)
4606 	{
4607 	  if (relaxed_size == xtensa_format_length (isa, i))
4608 	    return relaxed_size;
4609 	}
4610 
4611       return 3;
4612     }
4613 
4614   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4615     return 2 + fragP->tc_frag_data.text_expansion[0];
4616 
4617   return fmt_size;
4618 }
4619 
4620 
4621 static int
next_frag_format_size(const fragS * fragP)4622 next_frag_format_size (const fragS *fragP)
4623 {
4624   const fragS *next_fragP = next_non_empty_frag (fragP);
4625   return frag_format_size (next_fragP);
4626 }
4627 
4628 
4629 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4630    required two-byte instructions to be treated as three-byte instructions
4631    for loop instruction alignment.  This restriction was removed beginning
4632    with Xtensa LX.  Now the only requirement on loop instruction alignment
4633    is that the first instruction of the loop must appear at an address that
4634    does not cross a fetch boundary.  */
4635 
4636 static int
get_loop_align_size(int insn_size)4637 get_loop_align_size (int insn_size)
4638 {
4639   if (insn_size == XTENSA_UNDEFINED)
4640     return xtensa_fetch_width;
4641 
4642   if (enforce_three_byte_loop_align && insn_size == 2)
4643     return 3;
4644 
4645   return insn_size;
4646 }
4647 
4648 
4649 /* If the next legit fragment is an end-of-loop marker,
4650    switch its state so it will instantiate a NOP.  */
4651 
4652 static void
update_next_frag_state(fragS * fragP)4653 update_next_frag_state (fragS *fragP)
4654 {
4655   fragS *next_fragP = fragP->fr_next;
4656   fragS *new_target = NULL;
4657 
4658   if (align_targets)
4659     {
4660       /* We are guaranteed there will be one of these...   */
4661       while (!(next_fragP->fr_type == rs_machine_dependent
4662 	       && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4663 		   || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4664 	next_fragP = next_fragP->fr_next;
4665 
4666       gas_assert (next_fragP->fr_type == rs_machine_dependent
4667 	      && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4668 		  || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4669 
4670       /* ...and one of these.  */
4671       new_target = next_fragP->fr_next;
4672       while (!(new_target->fr_type == rs_machine_dependent
4673 	       && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4674 		   || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4675 	new_target = new_target->fr_next;
4676 
4677       gas_assert (new_target->fr_type == rs_machine_dependent
4678 	      && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4679 		  || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4680     }
4681 
4682   while (next_fragP && next_fragP->fr_fix == 0)
4683     {
4684       if (next_fragP->fr_type == rs_machine_dependent
4685 	  && next_fragP->fr_subtype == RELAX_LOOP_END)
4686 	{
4687 	  next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4688 	  return;
4689 	}
4690 
4691       next_fragP = next_fragP->fr_next;
4692     }
4693 }
4694 
4695 
4696 static bfd_boolean
next_frag_is_branch_target(const fragS * fragP)4697 next_frag_is_branch_target (const fragS *fragP)
4698 {
4699   /* Sometimes an empty will end up here due to storage allocation issues,
4700      so we have to skip until we find something legit.  */
4701   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4702     {
4703       if (fragP->tc_frag_data.is_branch_target)
4704 	return TRUE;
4705       if (fragP->fr_fix != 0)
4706 	break;
4707     }
4708   return FALSE;
4709 }
4710 
4711 
4712 static bfd_boolean
next_frag_is_loop_target(const fragS * fragP)4713 next_frag_is_loop_target (const fragS *fragP)
4714 {
4715   /* Sometimes an empty will end up here due storage allocation issues.
4716      So we have to skip until we find something legit. */
4717   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4718     {
4719       if (fragP->tc_frag_data.is_loop_target)
4720 	return TRUE;
4721       if (fragP->fr_fix != 0)
4722 	break;
4723     }
4724   return FALSE;
4725 }
4726 
4727 
4728 /* As specified in the relaxation table, when a loop instruction is
4729    relaxed, there are 24 bytes between the loop instruction itself and
4730    the first instruction in the loop.  */
4731 
4732 #define RELAXED_LOOP_INSN_BYTES 24
4733 
4734 static addressT
next_frag_pre_opcode_bytes(const fragS * fragp)4735 next_frag_pre_opcode_bytes (const fragS *fragp)
4736 {
4737   const fragS *next_fragp = fragp->fr_next;
4738   xtensa_opcode next_opcode;
4739 
4740   if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4741     return 0;
4742 
4743   /* Sometimes an empty will end up here due to storage allocation issues,
4744      so we have to skip until we find something legit.  */
4745   while (next_fragp->fr_fix == 0)
4746     next_fragp = next_fragp->fr_next;
4747 
4748   if (next_fragp->fr_type != rs_machine_dependent)
4749     return 0;
4750 
4751   /* There is some implicit knowledge encoded in here.
4752      The LOOP instructions that are NOT RELAX_IMMED have
4753      been relaxed.  Note that we can assume that the LOOP
4754      instruction is in slot 0 because loops aren't bundleable.  */
4755   if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4756       return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES;
4757 
4758   return 0;
4759 }
4760 
4761 
4762 /* Mark a location where we can later insert literal frags.  Update
4763    the section's literal_pool_loc, so subsequent literals can be
4764    placed nearest to their use.  */
4765 
4766 static void
xtensa_mark_literal_pool_location(void)4767 xtensa_mark_literal_pool_location (void)
4768 {
4769   /* Any labels pointing to the current location need
4770      to be adjusted to after the literal pool.  */
4771   emit_state s;
4772   fragS *pool_location;
4773 
4774   if (use_literal_section)
4775     return;
4776 
4777   /* We stash info in these frags so we can later move the literal's
4778      fixes into this frchain's fix list.  */
4779   pool_location = frag_now;
4780   frag_now->tc_frag_data.lit_frchain = frchain_now;
4781   frag_now->tc_frag_data.literal_frag = frag_now;
4782   /* Just record this frag.  */
4783   xtensa_maybe_create_literal_pool_frag (FALSE, FALSE);
4784   frag_variant (rs_machine_dependent, 0, 0,
4785 		RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4786   xtensa_set_frag_assembly_state (frag_now);
4787   frag_now->tc_frag_data.lit_seg = now_seg;
4788   frag_variant (rs_machine_dependent, 0, 0,
4789 		RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4790   xtensa_set_frag_assembly_state (frag_now);
4791 
4792   /* Now put a frag into the literal pool that points to this location.  */
4793   set_literal_pool_location (now_seg, pool_location);
4794   xtensa_switch_to_non_abs_literal_fragment (&s);
4795   frag_align (2, 0, 0);
4796   record_alignment (now_seg, 2);
4797 
4798   /* Close whatever frag is there.  */
4799   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4800   xtensa_set_frag_assembly_state (frag_now);
4801   frag_now->tc_frag_data.literal_frag = pool_location;
4802   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4803   xtensa_restore_emit_state (&s);
4804   xtensa_set_frag_assembly_state (frag_now);
4805 }
4806 
4807 
4808 /* Build a nop of the correct size into tinsn.  */
4809 
4810 static void
build_nop(TInsn * tinsn,int size)4811 build_nop (TInsn *tinsn, int size)
4812 {
4813   tinsn_init (tinsn);
4814   switch (size)
4815     {
4816     case 2:
4817       tinsn->opcode = xtensa_nop_n_opcode;
4818       tinsn->ntok = 0;
4819       if (tinsn->opcode == XTENSA_UNDEFINED)
4820 	as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4821       break;
4822 
4823     case 3:
4824       if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4825 	{
4826 	  tinsn->opcode = xtensa_or_opcode;
4827 	  set_expr_const (&tinsn->tok[0], 1);
4828 	  set_expr_const (&tinsn->tok[1], 1);
4829 	  set_expr_const (&tinsn->tok[2], 1);
4830 	  tinsn->ntok = 3;
4831 	}
4832       else
4833 	tinsn->opcode = xtensa_nop_opcode;
4834 
4835       gas_assert (tinsn->opcode != XTENSA_UNDEFINED);
4836     }
4837 }
4838 
4839 
4840 /* Assemble a NOP of the requested size in the buffer.  User must have
4841    allocated "buf" with at least "size" bytes.  */
4842 
4843 static void
assemble_nop(int size,char * buf)4844 assemble_nop (int size, char *buf)
4845 {
4846   static xtensa_insnbuf insnbuf = NULL;
4847   TInsn tinsn;
4848 
4849   build_nop (&tinsn, size);
4850 
4851   if (!insnbuf)
4852     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4853 
4854   tinsn_to_insnbuf (&tinsn, insnbuf);
4855   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4856 			   (unsigned char *) buf, 0);
4857 }
4858 
4859 
4860 /* Return the number of bytes for the offset of the expanded loop
4861    instruction.  This should be incorporated into the relaxation
4862    specification but is hard-coded here.  This is used to auto-align
4863    the loop instruction.  It is invalid to call this function if the
4864    configuration does not have loops or if the opcode is not a loop
4865    opcode.  */
4866 
4867 static addressT
get_expanded_loop_offset(xtensa_opcode opcode)4868 get_expanded_loop_offset (xtensa_opcode opcode)
4869 {
4870   /* This is the OFFSET of the loop instruction in the expanded loop.
4871      This MUST correspond directly to the specification of the loop
4872      expansion.  It will be validated on fragment conversion.  */
4873   gas_assert (opcode != XTENSA_UNDEFINED);
4874   if (opcode == xtensa_loop_opcode)
4875     return 0;
4876   if (opcode == xtensa_loopnez_opcode)
4877     return 3;
4878   if (opcode == xtensa_loopgtz_opcode)
4879     return 6;
4880   as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4881   return 0;
4882 }
4883 
4884 
4885 static fragS *
get_literal_pool_location(segT seg)4886 get_literal_pool_location (segT seg)
4887 {
4888   struct litpool_seg *lps = litpool_seg_list.next;
4889   struct litpool_frag *lpf;
4890   for ( ; lps && lps->seg->id != seg->id; lps = lps->next)
4891     ;
4892   if (lps)
4893     {
4894       for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4895 	{ /* Skip "candidates" for now.  */
4896 	  if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
4897 	      lpf->priority == 1)
4898 	    return lpf->fragP;
4899 	}
4900       /* Must convert a lower-priority pool.  */
4901       for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4902 	{
4903 	  if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN)
4904 	    return lpf->fragP;
4905 	}
4906       /* Still no match -- try for a low priority pool.  */
4907       for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4908 	{
4909 	  if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
4910 	    return lpf->fragP;
4911 	}
4912     }
4913   return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4914 }
4915 
4916 
4917 static void
set_literal_pool_location(segT seg,fragS * literal_pool_loc)4918 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4919 {
4920   seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4921 }
4922 
4923 
4924 /* Set frag assembly state should be called when a new frag is
4925    opened and after a frag has been closed.  */
4926 
4927 static void
xtensa_set_frag_assembly_state(fragS * fragP)4928 xtensa_set_frag_assembly_state (fragS *fragP)
4929 {
4930   if (!density_supported)
4931     fragP->tc_frag_data.is_no_density = TRUE;
4932 
4933   /* This function is called from subsegs_finish, which is called
4934      after xtensa_end, so we can't use "use_transform" or
4935      "use_schedule" here.  */
4936   if (!directive_state[directive_transform])
4937     fragP->tc_frag_data.is_no_transform = TRUE;
4938   if (directive_state[directive_longcalls])
4939     fragP->tc_frag_data.use_longcalls = TRUE;
4940   fragP->tc_frag_data.use_absolute_literals =
4941     directive_state[directive_absolute_literals];
4942   fragP->tc_frag_data.is_assembly_state_set = TRUE;
4943 }
4944 
4945 
4946 static bfd_boolean
relaxable_section(asection * sec)4947 relaxable_section (asection *sec)
4948 {
4949   return ((sec->flags & SEC_DEBUGGING) == 0
4950 	  && strcmp (sec->name, ".eh_frame") != 0);
4951 }
4952 
4953 
4954 static void
xtensa_mark_frags_for_org(void)4955 xtensa_mark_frags_for_org (void)
4956 {
4957   segT *seclist;
4958 
4959   /* Walk over each fragment of all of the current segments.  If we find
4960      a .org frag in any of the segments, mark all frags prior to it as
4961      "no transform", which will prevent linker optimizations from messing
4962      up the .org distance.  This should be done after
4963      xtensa_find_unmarked_state_frags, because we don't want to worry here
4964      about that function trashing the data we save here.  */
4965 
4966   for (seclist = &stdoutput->sections;
4967        seclist && *seclist;
4968        seclist = &(*seclist)->next)
4969     {
4970       segT sec = *seclist;
4971       segment_info_type *seginfo;
4972       fragS *fragP;
4973       flagword flags;
4974       flags = bfd_get_section_flags (stdoutput, sec);
4975       if (flags & SEC_DEBUGGING)
4976 	continue;
4977       if (!(flags & SEC_ALLOC))
4978 	continue;
4979 
4980       seginfo = seg_info (sec);
4981       if (seginfo && seginfo->frchainP)
4982 	{
4983 	  fragS *last_fragP = seginfo->frchainP->frch_root;
4984 	  for (fragP = seginfo->frchainP->frch_root; fragP;
4985 	       fragP = fragP->fr_next)
4986 	    {
4987 	      /* cvt_frag_to_fill has changed the fr_type of org frags to
4988 		 rs_fill, so use the value as cached in rs_subtype here.  */
4989 	      if (fragP->fr_subtype == RELAX_ORG)
4990 		{
4991 		  while (last_fragP != fragP->fr_next)
4992 		    {
4993 		      last_fragP->tc_frag_data.is_no_transform = TRUE;
4994 		      last_fragP = last_fragP->fr_next;
4995 		    }
4996 		}
4997 	    }
4998 	}
4999     }
5000 }
5001 
5002 
5003 static void
xtensa_find_unmarked_state_frags(void)5004 xtensa_find_unmarked_state_frags (void)
5005 {
5006   segT *seclist;
5007 
5008   /* Walk over each fragment of all of the current segments.  For each
5009      unmarked fragment, mark it with the same info as the previous
5010      fragment.  */
5011   for (seclist = &stdoutput->sections;
5012        seclist && *seclist;
5013        seclist = &(*seclist)->next)
5014     {
5015       segT sec = *seclist;
5016       segment_info_type *seginfo;
5017       fragS *fragP;
5018       flagword flags;
5019       flags = bfd_get_section_flags (stdoutput, sec);
5020       if (flags & SEC_DEBUGGING)
5021 	continue;
5022       if (!(flags & SEC_ALLOC))
5023 	continue;
5024 
5025       seginfo = seg_info (sec);
5026       if (seginfo && seginfo->frchainP)
5027 	{
5028 	  fragS *last_fragP = 0;
5029 	  for (fragP = seginfo->frchainP->frch_root; fragP;
5030 	       fragP = fragP->fr_next)
5031 	    {
5032 	      if (fragP->fr_fix != 0
5033 		  && !fragP->tc_frag_data.is_assembly_state_set)
5034 		{
5035 		  if (last_fragP == 0)
5036 		    {
5037 		      as_warn_where (fragP->fr_file, fragP->fr_line,
5038 				     _("assembly state not set for first frag in section %s"),
5039 				     sec->name);
5040 		    }
5041 		  else
5042 		    {
5043 		      fragP->tc_frag_data.is_assembly_state_set = TRUE;
5044 		      fragP->tc_frag_data.is_no_density =
5045 			last_fragP->tc_frag_data.is_no_density;
5046 		      fragP->tc_frag_data.is_no_transform =
5047 			last_fragP->tc_frag_data.is_no_transform;
5048 		      fragP->tc_frag_data.use_longcalls =
5049 			last_fragP->tc_frag_data.use_longcalls;
5050 		      fragP->tc_frag_data.use_absolute_literals =
5051 			last_fragP->tc_frag_data.use_absolute_literals;
5052 		    }
5053 		}
5054 	      if (fragP->tc_frag_data.is_assembly_state_set)
5055 		last_fragP = fragP;
5056 	    }
5057 	}
5058     }
5059 }
5060 
5061 
5062 static void
xtensa_find_unaligned_branch_targets(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * unused ATTRIBUTE_UNUSED)5063 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
5064 				      asection *sec,
5065 				      void *unused ATTRIBUTE_UNUSED)
5066 {
5067   flagword flags = bfd_get_section_flags (abfd, sec);
5068   segment_info_type *seginfo = seg_info (sec);
5069   fragS *frag = seginfo->frchainP->frch_root;
5070 
5071   if (flags & SEC_CODE)
5072     {
5073       xtensa_isa isa = xtensa_default_isa;
5074       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5075       while (frag != NULL)
5076 	{
5077 	  if (frag->tc_frag_data.is_branch_target)
5078 	    {
5079 	      int op_size;
5080 	      addressT branch_align, frag_addr;
5081 	      xtensa_format fmt;
5082 
5083 	      xtensa_insnbuf_from_chars
5084 		(isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5085 	      fmt = xtensa_format_decode (isa, insnbuf);
5086 	      op_size = xtensa_format_length (isa, fmt);
5087 	      branch_align = 1 << branch_align_power (sec);
5088 	      frag_addr = frag->fr_address % branch_align;
5089 	      if (frag_addr + op_size > branch_align)
5090 		as_warn_where (frag->fr_file, frag->fr_line,
5091 			       _("unaligned branch target: %d bytes at 0x%lx"),
5092 			       op_size, (long) frag->fr_address);
5093 	    }
5094 	  frag = frag->fr_next;
5095 	}
5096       xtensa_insnbuf_free (isa, insnbuf);
5097     }
5098 }
5099 
5100 
5101 static void
xtensa_find_unaligned_loops(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * unused ATTRIBUTE_UNUSED)5102 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
5103 			     asection *sec,
5104 			     void *unused ATTRIBUTE_UNUSED)
5105 {
5106   flagword flags = bfd_get_section_flags (abfd, sec);
5107   segment_info_type *seginfo = seg_info (sec);
5108   fragS *frag = seginfo->frchainP->frch_root;
5109   xtensa_isa isa = xtensa_default_isa;
5110 
5111   if (flags & SEC_CODE)
5112     {
5113       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5114       while (frag != NULL)
5115 	{
5116 	  if (frag->tc_frag_data.is_first_loop_insn)
5117 	    {
5118 	      int op_size;
5119 	      addressT frag_addr;
5120 	      xtensa_format fmt;
5121 
5122 	      if (frag->fr_fix == 0)
5123 		frag = next_non_empty_frag (frag);
5124 
5125 	      if (frag)
5126 		{
5127 		  xtensa_insnbuf_from_chars
5128 		    (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5129 		  fmt = xtensa_format_decode (isa, insnbuf);
5130 		  op_size = xtensa_format_length (isa, fmt);
5131 		  frag_addr = frag->fr_address % xtensa_fetch_width;
5132 
5133 		  if (frag_addr + op_size > xtensa_fetch_width)
5134 		    as_warn_where (frag->fr_file, frag->fr_line,
5135 				   _("unaligned loop: %d bytes at 0x%lx"),
5136 				   op_size, (long) frag->fr_address);
5137 		}
5138 	    }
5139 	  frag = frag->fr_next;
5140 	}
5141       xtensa_insnbuf_free (isa, insnbuf);
5142     }
5143 }
5144 
5145 
5146 static int
xg_apply_fix_value(fixS * fixP,valueT val)5147 xg_apply_fix_value (fixS *fixP, valueT val)
5148 {
5149   xtensa_isa isa = xtensa_default_isa;
5150   static xtensa_insnbuf insnbuf = NULL;
5151   static xtensa_insnbuf slotbuf = NULL;
5152   xtensa_format fmt;
5153   int slot;
5154   bfd_boolean alt_reloc;
5155   xtensa_opcode opcode;
5156   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5157 
5158   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc)
5159       || alt_reloc)
5160     as_fatal (_("unexpected fix"));
5161 
5162   if (!insnbuf)
5163     {
5164       insnbuf = xtensa_insnbuf_alloc (isa);
5165       slotbuf = xtensa_insnbuf_alloc (isa);
5166     }
5167 
5168   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5169   fmt = xtensa_format_decode (isa, insnbuf);
5170   if (fmt == XTENSA_UNDEFINED)
5171     as_fatal (_("undecodable fix"));
5172   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5173   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5174   if (opcode == XTENSA_UNDEFINED)
5175     as_fatal (_("undecodable fix"));
5176 
5177   /* CONST16 immediates are not PC-relative, despite the fact that we
5178      reuse the normal PC-relative operand relocations for the low part
5179      of a CONST16 operand.  */
5180   if (opcode == xtensa_const16_opcode)
5181     return 0;
5182 
5183   xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5184 			      get_relaxable_immed (opcode), val,
5185 			      fixP->fx_file, fixP->fx_line);
5186 
5187   xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5188   xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5189 
5190   return 1;
5191 }
5192 
5193 
5194 /* External Functions and Other GAS Hooks.  */
5195 
5196 const char *
xtensa_target_format(void)5197 xtensa_target_format (void)
5198 {
5199   return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5200 }
5201 
5202 
5203 void
xtensa_file_arch_init(bfd * abfd)5204 xtensa_file_arch_init (bfd *abfd)
5205 {
5206   bfd_set_private_flags (abfd, 0x100 | 0x200);
5207 }
5208 
5209 
5210 void
md_number_to_chars(char * buf,valueT val,int n)5211 md_number_to_chars (char *buf, valueT val, int n)
5212 {
5213   if (target_big_endian)
5214     number_to_chars_bigendian (buf, val, n);
5215   else
5216     number_to_chars_littleendian (buf, val, n);
5217 }
5218 
5219 
5220 /* This function is called once, at assembler startup time.  It should
5221    set up all the tables, etc. that the MD part of the assembler will
5222    need.  */
5223 
5224 void
md_begin(void)5225 md_begin (void)
5226 {
5227   segT current_section = now_seg;
5228   int current_subsec = now_subseg;
5229   xtensa_isa isa;
5230   int i;
5231 
5232   xtensa_default_isa = xtensa_isa_init (0, 0);
5233   isa = xtensa_default_isa;
5234 
5235   linkrelax = 1;
5236 
5237   /* Set up the literal sections.  */
5238   memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5239 
5240   subseg_set (current_section, current_subsec);
5241 
5242   xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5243   xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5244   xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5245   xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5246   xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5247   xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5248   xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5249   xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5250   xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5251   xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5252   xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5253   xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5254   xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui");
5255   xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5256   xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5257   xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5258   xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
5259   xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5260   xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5261   xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5262   xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5263   xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5264   xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5265   xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5266   xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5267   xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5268   xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5269   xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5270   xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5271   xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5272   xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5273 
5274   for (i = 0; i < xtensa_isa_num_formats (isa); i++)
5275     {
5276       int format_slots = xtensa_format_num_slots (isa, i);
5277       if (format_slots > config_max_slots)
5278 	config_max_slots = format_slots;
5279     }
5280 
5281   xg_init_vinsn (&cur_vinsn);
5282 
5283   xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa);
5284 
5285   init_op_placement_info_table ();
5286 
5287   /* Set up the assembly state.  */
5288   if (!frag_now->tc_frag_data.is_assembly_state_set)
5289     xtensa_set_frag_assembly_state (frag_now);
5290 }
5291 
5292 
5293 /* TC_INIT_FIX_DATA hook */
5294 
5295 void
xtensa_init_fix_data(fixS * x)5296 xtensa_init_fix_data (fixS *x)
5297 {
5298   x->tc_fix_data.slot = 0;
5299   x->tc_fix_data.X_add_symbol = NULL;
5300   x->tc_fix_data.X_add_number = 0;
5301 }
5302 
5303 
5304 /* tc_frob_label hook */
5305 
5306 void
xtensa_frob_label(symbolS * sym)5307 xtensa_frob_label (symbolS *sym)
5308 {
5309   float freq;
5310 
5311   if (cur_vinsn.inside_bundle)
5312     {
5313       as_bad (_("labels are not valid inside bundles"));
5314       return;
5315     }
5316 
5317   freq = get_subseg_target_freq (now_seg, now_subseg);
5318 
5319   /* Since the label was already attached to a frag associated with the
5320      previous basic block, it now needs to be reset to the current frag.  */
5321   symbol_set_frag (sym, frag_now);
5322   S_SET_VALUE (sym, (valueT) frag_now_fix ());
5323 
5324   if (generating_literals)
5325     xtensa_add_literal_sym (sym);
5326   else
5327     xtensa_add_insn_label (sym);
5328 
5329   if (symbol_get_tc (sym)->is_loop_target)
5330     {
5331       if ((get_last_insn_flags (now_seg, now_subseg)
5332 	  & FLAG_IS_BAD_LOOPEND) != 0)
5333 	as_bad (_("invalid last instruction for a zero-overhead loop"));
5334 
5335       xtensa_set_frag_assembly_state (frag_now);
5336       frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5337 		frag_now->fr_symbol, frag_now->fr_offset, NULL);
5338 
5339       xtensa_set_frag_assembly_state (frag_now);
5340       xtensa_move_labels (frag_now, 0);
5341     }
5342 
5343   /* No target aligning in the absolute section.  */
5344   if (now_seg != absolute_section
5345       && !is_unaligned_label (sym)
5346       && !generating_literals)
5347     {
5348       xtensa_set_frag_assembly_state (frag_now);
5349 
5350       if (do_align_targets ())
5351 	frag_var (rs_machine_dependent, 0, (int) freq,
5352 		  RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol,
5353 		  frag_now->fr_offset, NULL);
5354       else
5355 	frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
5356 		  frag_now->fr_symbol, frag_now->fr_offset, NULL);
5357       xtensa_set_frag_assembly_state (frag_now);
5358       xtensa_move_labels (frag_now, 0);
5359     }
5360 
5361   /* We need to mark the following properties even if we aren't aligning.  */
5362 
5363   /* If the label is already known to be a branch target, i.e., a
5364      forward branch, mark the frag accordingly.  Backward branches
5365      are handled by xg_add_branch_and_loop_targets.  */
5366   if (symbol_get_tc (sym)->is_branch_target)
5367     symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5368 
5369   /* Loops only go forward, so they can be identified here.  */
5370   if (symbol_get_tc (sym)->is_loop_target)
5371     symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5372 
5373   dwarf2_emit_label (sym);
5374 }
5375 
5376 
5377 /* tc_unrecognized_line hook */
5378 
5379 int
xtensa_unrecognized_line(int ch)5380 xtensa_unrecognized_line (int ch)
5381 {
5382   switch (ch)
5383     {
5384     case '{' :
5385       if (cur_vinsn.inside_bundle == 0)
5386 	{
5387 	  /* PR8110: Cannot emit line number info inside a FLIX bundle
5388 	     when using --gstabs.  Temporarily disable debug info.  */
5389 	  generate_lineno_debug ();
5390 	  if (debug_type == DEBUG_STABS)
5391 	    {
5392 	      xt_saved_debug_type = debug_type;
5393 	      debug_type = DEBUG_NONE;
5394 	    }
5395 
5396 	  cur_vinsn.inside_bundle = 1;
5397 	}
5398       else
5399 	{
5400 	  as_bad (_("extra opening brace"));
5401 	  return 0;
5402 	}
5403       break;
5404 
5405     case '}' :
5406       if (cur_vinsn.inside_bundle)
5407 	finish_vinsn (&cur_vinsn);
5408       else
5409 	{
5410 	  as_bad (_("extra closing brace"));
5411 	  return 0;
5412 	}
5413       break;
5414     default:
5415       as_bad (_("syntax error"));
5416       return 0;
5417     }
5418   return 1;
5419 }
5420 
5421 
5422 /* md_flush_pending_output hook */
5423 
5424 void
xtensa_flush_pending_output(void)5425 xtensa_flush_pending_output (void)
5426 {
5427   /* This line fixes a bug where automatically generated gstabs info
5428      separates a function label from its entry instruction, ending up
5429      with the literal position between the function label and the entry
5430      instruction and crashing code.  It only happens with --gstabs and
5431      --text-section-literals, and when several other obscure relaxation
5432      conditions are met.  */
5433   if (outputting_stabs_line_debug)
5434     return;
5435 
5436   if (cur_vinsn.inside_bundle)
5437     as_bad (_("missing closing brace"));
5438 
5439   /* If there is a non-zero instruction fragment, close it.  */
5440   if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5441     {
5442       frag_wane (frag_now);
5443       frag_new (0);
5444       xtensa_set_frag_assembly_state (frag_now);
5445     }
5446   frag_now->tc_frag_data.is_insn = FALSE;
5447 
5448   xtensa_clear_insn_labels ();
5449 }
5450 
5451 
5452 /* We had an error while parsing an instruction.  The string might look
5453    like this: "insn arg1, arg2 }".  If so, we need to see the closing
5454    brace and reset some fields.  Otherwise, the vinsn never gets closed
5455    and the num_slots field will grow past the end of the array of slots,
5456    and bad things happen.  */
5457 
5458 static void
error_reset_cur_vinsn(void)5459 error_reset_cur_vinsn (void)
5460 {
5461   if (cur_vinsn.inside_bundle)
5462     {
5463       if (*input_line_pointer == '}'
5464 	  || *(input_line_pointer - 1) == '}'
5465 	  || *(input_line_pointer - 2) == '}')
5466 	xg_clear_vinsn (&cur_vinsn);
5467     }
5468 }
5469 
5470 
5471 void
md_assemble(char * str)5472 md_assemble (char *str)
5473 {
5474   xtensa_isa isa = xtensa_default_isa;
5475   char *opname;
5476   unsigned opnamelen;
5477   bfd_boolean has_underbar = FALSE;
5478   char *arg_strings[MAX_INSN_ARGS];
5479   int num_args;
5480   TInsn orig_insn;		/* Original instruction from the input.  */
5481 
5482   tinsn_init (&orig_insn);
5483 
5484   /* Split off the opcode.  */
5485   opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5486   opname = xstrndup (str, opnamelen);
5487 
5488   num_args = tokenize_arguments (arg_strings, str + opnamelen);
5489   if (num_args == -1)
5490     {
5491       as_bad (_("syntax error"));
5492       return;
5493     }
5494 
5495   if (xg_translate_idioms (&opname, &num_args, arg_strings))
5496     return;
5497 
5498   /* Check for an underbar prefix.  */
5499   if (*opname == '_')
5500     {
5501       has_underbar = TRUE;
5502       opname += 1;
5503     }
5504 
5505   orig_insn.insn_type = ITYPE_INSN;
5506   orig_insn.ntok = 0;
5507   orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5508   orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5509 
5510   /* Special case: Check for "CALLXn.TLS" psuedo op.  If found, grab its
5511      extra argument and set the opcode to "CALLXn".  */
5512   if (orig_insn.opcode == XTENSA_UNDEFINED
5513       && strncasecmp (opname, "callx", 5) == 0)
5514     {
5515       unsigned long window_size;
5516       char *suffix;
5517 
5518       window_size = strtoul (opname + 5, &suffix, 10);
5519       if (suffix != opname + 5
5520 	  && (window_size == 0
5521 	      || window_size == 4
5522 	      || window_size == 8
5523 	      || window_size == 12)
5524 	  && strcasecmp (suffix, ".tls") == 0)
5525 	{
5526 	  switch (window_size)
5527 	    {
5528 	    case 0: orig_insn.opcode = xtensa_callx0_opcode; break;
5529 	    case 4: orig_insn.opcode = xtensa_callx4_opcode; break;
5530 	    case 8: orig_insn.opcode = xtensa_callx8_opcode; break;
5531 	    case 12: orig_insn.opcode = xtensa_callx12_opcode; break;
5532 	    }
5533 
5534 	  if (num_args != 2)
5535 	    as_bad (_("wrong number of operands for '%s'"), opname);
5536 	  else
5537 	    {
5538 	      bfd_reloc_code_real_type reloc;
5539 	      char *old_input_line_pointer;
5540 	      expressionS *tok = &orig_insn.extra_arg;
5541 
5542 	      old_input_line_pointer = input_line_pointer;
5543 	      input_line_pointer = arg_strings[num_args - 1];
5544 
5545 	      expression (tok);
5546 	      if (tok->X_op == O_symbol
5547 		  && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
5548 		      == BFD_RELOC_XTENSA_TLS_CALL))
5549 		tok->X_op = map_suffix_reloc_to_operator (reloc);
5550 	      else
5551 		as_bad (_("bad relocation expression for '%s'"), opname);
5552 
5553 	      input_line_pointer = old_input_line_pointer;
5554 	      num_args -= 1;
5555 	    }
5556 	}
5557     }
5558 
5559   /* Special case: Check for "j.l" psuedo op.  */
5560   if (orig_insn.opcode == XTENSA_UNDEFINED
5561       && strncasecmp (opname, "j.l", 3) == 0)
5562     {
5563       if (num_args != 2)
5564 	as_bad (_("wrong number of operands for '%s'"), opname);
5565       else
5566 	{
5567 	  char *old_input_line_pointer;
5568 	  expressionS *tok = &orig_insn.extra_arg;
5569 
5570 	  old_input_line_pointer = input_line_pointer;
5571 	  input_line_pointer = arg_strings[num_args - 1];
5572 
5573 	  expression_maybe_register (xtensa_jx_opcode, 0, tok);
5574 	  input_line_pointer = old_input_line_pointer;
5575 
5576 	  num_args -= 1;
5577 	  orig_insn.opcode = xtensa_j_opcode;
5578 	}
5579     }
5580 
5581   if (orig_insn.opcode == XTENSA_UNDEFINED)
5582     {
5583       xtensa_format fmt = xtensa_format_lookup (isa, opname);
5584       if (fmt == XTENSA_UNDEFINED)
5585 	{
5586 	  as_bad (_("unknown opcode or format name '%s'"), opname);
5587 	  error_reset_cur_vinsn ();
5588 	  return;
5589 	}
5590       if (!cur_vinsn.inside_bundle)
5591 	{
5592 	  as_bad (_("format names only valid inside bundles"));
5593 	  error_reset_cur_vinsn ();
5594 	  return;
5595 	}
5596       if (cur_vinsn.format != XTENSA_UNDEFINED)
5597 	as_warn (_("multiple formats specified for one bundle; using '%s'"),
5598 		 opname);
5599       cur_vinsn.format = fmt;
5600       free (has_underbar ? opname - 1 : opname);
5601       error_reset_cur_vinsn ();
5602       return;
5603     }
5604 
5605   /* Parse the arguments.  */
5606   if (parse_arguments (&orig_insn, num_args, arg_strings))
5607     {
5608       as_bad (_("syntax error"));
5609       error_reset_cur_vinsn ();
5610       return;
5611     }
5612 
5613   /* Free the opcode and argument strings, now that they've been parsed.  */
5614   free (has_underbar ? opname - 1 : opname);
5615   opname = 0;
5616   while (num_args-- > 0)
5617     free (arg_strings[num_args]);
5618 
5619   /* Get expressions for invisible operands.  */
5620   if (get_invisible_operands (&orig_insn))
5621     {
5622       error_reset_cur_vinsn ();
5623       return;
5624     }
5625 
5626   /* Check for the right number and type of arguments.  */
5627   if (tinsn_check_arguments (&orig_insn))
5628     {
5629       error_reset_cur_vinsn ();
5630       return;
5631     }
5632 
5633   /* Record the line number for each TInsn, because a FLIX bundle may be
5634      spread across multiple input lines and individual instructions may be
5635      moved around in some cases.  */
5636   orig_insn.loc_directive_seen = dwarf2_loc_directive_seen;
5637   dwarf2_where (&orig_insn.debug_line);
5638   dwarf2_consume_line_info ();
5639 
5640   xg_add_branch_and_loop_targets (&orig_insn);
5641 
5642   /* Check that immediate value for ENTRY is >= 16.  */
5643   if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
5644     {
5645       expressionS *exp = &orig_insn.tok[2];
5646       if (exp->X_op == O_constant && exp->X_add_number < 16)
5647 	as_warn (_("entry instruction with stack decrement < 16"));
5648     }
5649 
5650   /* Finish it off:
5651      assemble_tokens (opcode, tok, ntok);
5652      expand the tokens from the orig_insn into the
5653      stack of instructions that will not expand
5654      unless required at relaxation time.  */
5655 
5656   if (!cur_vinsn.inside_bundle)
5657     emit_single_op (&orig_insn);
5658   else /* We are inside a bundle.  */
5659     {
5660       cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5661       cur_vinsn.num_slots++;
5662       if (*input_line_pointer == '}'
5663 	  || *(input_line_pointer - 1) == '}'
5664 	  || *(input_line_pointer - 2) == '}')
5665 	finish_vinsn (&cur_vinsn);
5666     }
5667 
5668   /* We've just emitted a new instruction so clear the list of labels.  */
5669   xtensa_clear_insn_labels ();
5670 
5671   xtensa_check_frag_count ();
5672 }
5673 
5674 
5675 /* HANDLE_ALIGN hook */
5676 
5677 /* For a .align directive, we mark the previous block with the alignment
5678    information.  This will be placed in the object file in the
5679    property section corresponding to this section.  */
5680 
5681 void
xtensa_handle_align(fragS * fragP)5682 xtensa_handle_align (fragS *fragP)
5683 {
5684   if (linkrelax
5685       && ! fragP->tc_frag_data.is_literal
5686       && (fragP->fr_type == rs_align
5687 	  || fragP->fr_type == rs_align_code)
5688       && fragP->fr_offset > 0
5689       && now_seg != bss_section)
5690     {
5691       fragP->tc_frag_data.is_align = TRUE;
5692       fragP->tc_frag_data.alignment = fragP->fr_offset;
5693     }
5694 
5695   if (fragP->fr_type == rs_align_test)
5696     {
5697       int count;
5698       count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5699       if (count != 0)
5700 	as_bad_where (fragP->fr_file, fragP->fr_line,
5701 		      _("unaligned entry instruction"));
5702     }
5703 
5704   if (linkrelax && fragP->fr_type == rs_org)
5705     fragP->fr_subtype = RELAX_ORG;
5706 }
5707 
5708 
5709 /* TC_FRAG_INIT hook */
5710 
5711 void
xtensa_frag_init(fragS * frag)5712 xtensa_frag_init (fragS *frag)
5713 {
5714   xtensa_set_frag_assembly_state (frag);
5715 }
5716 
5717 
5718 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)5719 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5720 {
5721   return NULL;
5722 }
5723 
5724 
5725 /* Round up a section size to the appropriate boundary.  */
5726 
5727 valueT
md_section_align(segT segment ATTRIBUTE_UNUSED,valueT size)5728 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5729 {
5730   return size;			/* Byte alignment is fine.  */
5731 }
5732 
5733 
5734 long
md_pcrel_from(fixS * fixP)5735 md_pcrel_from (fixS *fixP)
5736 {
5737   char *insn_p;
5738   static xtensa_insnbuf insnbuf = NULL;
5739   static xtensa_insnbuf slotbuf = NULL;
5740   int opnum;
5741   uint32 opnd_value;
5742   xtensa_opcode opcode;
5743   xtensa_format fmt;
5744   int slot;
5745   xtensa_isa isa = xtensa_default_isa;
5746   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5747   bfd_boolean alt_reloc;
5748 
5749   if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5750     return 0;
5751 
5752   if (fixP->fx_r_type == BFD_RELOC_32_PCREL)
5753     return addr;
5754 
5755   if (!insnbuf)
5756     {
5757       insnbuf = xtensa_insnbuf_alloc (isa);
5758       slotbuf = xtensa_insnbuf_alloc (isa);
5759     }
5760 
5761   insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5762   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
5763   fmt = xtensa_format_decode (isa, insnbuf);
5764 
5765   if (fmt == XTENSA_UNDEFINED)
5766     as_fatal (_("bad instruction format"));
5767 
5768   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5769     as_fatal (_("invalid relocation"));
5770 
5771   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5772   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5773 
5774   /* Check for "alternate" relocations (operand not specified).  None
5775      of the current uses for these are really PC-relative.  */
5776   if (alt_reloc || opcode == xtensa_const16_opcode)
5777     {
5778       if (opcode != xtensa_l32r_opcode
5779 	  && opcode != xtensa_const16_opcode)
5780 	as_fatal (_("invalid relocation for '%s' instruction"),
5781 		  xtensa_opcode_name (isa, opcode));
5782       return 0;
5783     }
5784 
5785   opnum = get_relaxable_immed (opcode);
5786   opnd_value = 0;
5787   if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5788       || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5789     {
5790       as_bad_where (fixP->fx_file,
5791 		    fixP->fx_line,
5792 		    _("invalid relocation for operand %d of '%s'"),
5793 		    opnum, xtensa_opcode_name (isa, opcode));
5794       return 0;
5795     }
5796   return 0 - opnd_value;
5797 }
5798 
5799 
5800 /* TC_FORCE_RELOCATION hook */
5801 
5802 int
xtensa_force_relocation(fixS * fix)5803 xtensa_force_relocation (fixS *fix)
5804 {
5805   switch (fix->fx_r_type)
5806     {
5807     case BFD_RELOC_XTENSA_ASM_EXPAND:
5808     case BFD_RELOC_XTENSA_SLOT0_ALT:
5809     case BFD_RELOC_XTENSA_SLOT1_ALT:
5810     case BFD_RELOC_XTENSA_SLOT2_ALT:
5811     case BFD_RELOC_XTENSA_SLOT3_ALT:
5812     case BFD_RELOC_XTENSA_SLOT4_ALT:
5813     case BFD_RELOC_XTENSA_SLOT5_ALT:
5814     case BFD_RELOC_XTENSA_SLOT6_ALT:
5815     case BFD_RELOC_XTENSA_SLOT7_ALT:
5816     case BFD_RELOC_XTENSA_SLOT8_ALT:
5817     case BFD_RELOC_XTENSA_SLOT9_ALT:
5818     case BFD_RELOC_XTENSA_SLOT10_ALT:
5819     case BFD_RELOC_XTENSA_SLOT11_ALT:
5820     case BFD_RELOC_XTENSA_SLOT12_ALT:
5821     case BFD_RELOC_XTENSA_SLOT13_ALT:
5822     case BFD_RELOC_XTENSA_SLOT14_ALT:
5823       return 1;
5824     default:
5825       break;
5826     }
5827 
5828   if (linkrelax && fix->fx_addsy
5829       && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5830     return 1;
5831 
5832   return generic_force_reloc (fix);
5833 }
5834 
5835 
5836 /* TC_VALIDATE_FIX_SUB hook */
5837 
5838 int
xtensa_validate_fix_sub(fixS * fix)5839 xtensa_validate_fix_sub (fixS *fix)
5840 {
5841   segT add_symbol_segment, sub_symbol_segment;
5842 
5843   /* The difference of two symbols should be resolved by the assembler when
5844      linkrelax is not set.  If the linker may relax the section containing
5845      the symbols, then an Xtensa DIFF relocation must be generated so that
5846      the linker knows to adjust the difference value.  */
5847   if (!linkrelax || fix->fx_addsy == NULL)
5848     return 0;
5849 
5850   /* Make sure both symbols are in the same segment, and that segment is
5851      "normal" and relaxable.  If the segment is not "normal", then the
5852      fix is not valid.  If the segment is not "relaxable", then the fix
5853      should have been handled earlier.  */
5854   add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5855   if (! SEG_NORMAL (add_symbol_segment) ||
5856       ! relaxable_section (add_symbol_segment))
5857     return 0;
5858   sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5859   return (sub_symbol_segment == add_symbol_segment);
5860 }
5861 
5862 
5863 /* NO_PSEUDO_DOT hook */
5864 
5865 /* This function has nothing to do with pseudo dots, but this is the
5866    nearest macro to where the check needs to take place.  FIXME: This
5867    seems wrong.  */
5868 
5869 bfd_boolean
xtensa_check_inside_bundle(void)5870 xtensa_check_inside_bundle (void)
5871 {
5872   if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5873     as_bad (_("directives are not valid inside bundles"));
5874 
5875   /* This function must always return FALSE because it is called via a
5876      macro that has nothing to do with bundling.  */
5877   return FALSE;
5878 }
5879 
5880 
5881 /* md_elf_section_change_hook */
5882 
5883 void
xtensa_elf_section_change_hook(void)5884 xtensa_elf_section_change_hook (void)
5885 {
5886   /* Set up the assembly state.  */
5887   if (!frag_now->tc_frag_data.is_assembly_state_set)
5888     xtensa_set_frag_assembly_state (frag_now);
5889 }
5890 
5891 
5892 /* tc_fix_adjustable hook */
5893 
5894 bfd_boolean
xtensa_fix_adjustable(fixS * fixP)5895 xtensa_fix_adjustable (fixS *fixP)
5896 {
5897   /* We need the symbol name for the VTABLE entries.  */
5898   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5899       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5900     return 0;
5901 
5902   return 1;
5903 }
5904 
5905 
5906 /* tc_symbol_new_hook */
5907 
5908 symbolS *expr_symbols = NULL;
5909 
5910 void
xtensa_symbol_new_hook(symbolS * sym)5911 xtensa_symbol_new_hook (symbolS *sym)
5912 {
5913   if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section)
5914     {
5915       symbol_get_tc (sym)->next_expr_symbol = expr_symbols;
5916       expr_symbols = sym;
5917     }
5918 }
5919 
5920 
5921 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg)5922 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
5923 {
5924   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5925   valueT val = 0;
5926 
5927   /* Subtracted symbols are only allowed for a few relocation types, and
5928      unless linkrelax is enabled, they should not make it to this point.  */
5929   if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
5930 					|| fixP->fx_r_type == BFD_RELOC_16
5931 					|| fixP->fx_r_type == BFD_RELOC_8)))
5932     as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
5933 
5934   switch (fixP->fx_r_type)
5935     {
5936     case BFD_RELOC_32_PCREL:
5937     case BFD_RELOC_32:
5938     case BFD_RELOC_16:
5939     case BFD_RELOC_8:
5940       if (fixP->fx_subsy)
5941 	{
5942 	  switch (fixP->fx_r_type)
5943 	    {
5944 	    case BFD_RELOC_8:
5945 	      fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5946 	      fixP->fx_signed = 0;
5947 	      break;
5948 	    case BFD_RELOC_16:
5949 	      fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5950 	      fixP->fx_signed = 0;
5951 	      break;
5952 	    case BFD_RELOC_32:
5953 	      fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5954 	      fixP->fx_signed = 0;
5955 	      break;
5956 	    default:
5957 	      break;
5958 	    }
5959 
5960 	  val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5961 		 - S_GET_VALUE (fixP->fx_subsy));
5962 
5963 	  /* The difference value gets written out, and the DIFF reloc
5964 	     identifies the address of the subtracted symbol (i.e., the one
5965 	     with the lowest address).  */
5966 	  *valP = val;
5967 	  fixP->fx_offset -= val;
5968 	  fixP->fx_subsy = NULL;
5969 	}
5970       else if (! fixP->fx_addsy)
5971 	{
5972 	  val = *valP;
5973 	  fixP->fx_done = 1;
5974 	}
5975       /* fall through */
5976 
5977     case BFD_RELOC_XTENSA_PLT:
5978       md_number_to_chars (fixpos, val, fixP->fx_size);
5979       fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
5980       break;
5981 
5982     case BFD_RELOC_XTENSA_TLSDESC_FN:
5983     case BFD_RELOC_XTENSA_TLSDESC_ARG:
5984     case BFD_RELOC_XTENSA_TLS_TPOFF:
5985     case BFD_RELOC_XTENSA_TLS_DTPOFF:
5986       S_SET_THREAD_LOCAL (fixP->fx_addsy);
5987       md_number_to_chars (fixpos, 0, fixP->fx_size);
5988       fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
5989       break;
5990 
5991     case BFD_RELOC_XTENSA_SLOT0_OP:
5992     case BFD_RELOC_XTENSA_SLOT1_OP:
5993     case BFD_RELOC_XTENSA_SLOT2_OP:
5994     case BFD_RELOC_XTENSA_SLOT3_OP:
5995     case BFD_RELOC_XTENSA_SLOT4_OP:
5996     case BFD_RELOC_XTENSA_SLOT5_OP:
5997     case BFD_RELOC_XTENSA_SLOT6_OP:
5998     case BFD_RELOC_XTENSA_SLOT7_OP:
5999     case BFD_RELOC_XTENSA_SLOT8_OP:
6000     case BFD_RELOC_XTENSA_SLOT9_OP:
6001     case BFD_RELOC_XTENSA_SLOT10_OP:
6002     case BFD_RELOC_XTENSA_SLOT11_OP:
6003     case BFD_RELOC_XTENSA_SLOT12_OP:
6004     case BFD_RELOC_XTENSA_SLOT13_OP:
6005     case BFD_RELOC_XTENSA_SLOT14_OP:
6006       if (linkrelax)
6007 	{
6008 	  /* Write the tentative value of a PC-relative relocation to a
6009 	     local symbol into the instruction.  The value will be ignored
6010 	     by the linker, and it makes the object file disassembly
6011 	     readable when all branch targets are encoded in relocations.  */
6012 
6013 	  gas_assert (fixP->fx_addsy);
6014 	  if (S_GET_SEGMENT (fixP->fx_addsy) == seg
6015 	      && !S_FORCE_RELOC (fixP->fx_addsy, 1))
6016 	    {
6017 	      val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6018 		     - md_pcrel_from (fixP));
6019 	      (void) xg_apply_fix_value (fixP, val);
6020 	    }
6021 	}
6022       else if (! fixP->fx_addsy)
6023 	{
6024 	  val = *valP;
6025 	  if (xg_apply_fix_value (fixP, val))
6026 	    fixP->fx_done = 1;
6027 	}
6028       break;
6029 
6030     case BFD_RELOC_XTENSA_ASM_EXPAND:
6031     case BFD_RELOC_XTENSA_TLS_FUNC:
6032     case BFD_RELOC_XTENSA_TLS_ARG:
6033     case BFD_RELOC_XTENSA_TLS_CALL:
6034     case BFD_RELOC_XTENSA_SLOT0_ALT:
6035     case BFD_RELOC_XTENSA_SLOT1_ALT:
6036     case BFD_RELOC_XTENSA_SLOT2_ALT:
6037     case BFD_RELOC_XTENSA_SLOT3_ALT:
6038     case BFD_RELOC_XTENSA_SLOT4_ALT:
6039     case BFD_RELOC_XTENSA_SLOT5_ALT:
6040     case BFD_RELOC_XTENSA_SLOT6_ALT:
6041     case BFD_RELOC_XTENSA_SLOT7_ALT:
6042     case BFD_RELOC_XTENSA_SLOT8_ALT:
6043     case BFD_RELOC_XTENSA_SLOT9_ALT:
6044     case BFD_RELOC_XTENSA_SLOT10_ALT:
6045     case BFD_RELOC_XTENSA_SLOT11_ALT:
6046     case BFD_RELOC_XTENSA_SLOT12_ALT:
6047     case BFD_RELOC_XTENSA_SLOT13_ALT:
6048     case BFD_RELOC_XTENSA_SLOT14_ALT:
6049       /* These all need to be resolved at link-time.  Do nothing now.  */
6050       break;
6051 
6052     case BFD_RELOC_VTABLE_INHERIT:
6053     case BFD_RELOC_VTABLE_ENTRY:
6054       fixP->fx_done = 0;
6055       break;
6056 
6057     default:
6058       as_bad (_("unhandled local relocation fix %s"),
6059 	      bfd_get_reloc_code_name (fixP->fx_r_type));
6060     }
6061 }
6062 
6063 
6064 const char *
md_atof(int type,char * litP,int * sizeP)6065 md_atof (int type, char *litP, int *sizeP)
6066 {
6067   return ieee_md_atof (type, litP, sizeP, target_big_endian);
6068 }
6069 
6070 
6071 int
md_estimate_size_before_relax(fragS * fragP,segT seg ATTRIBUTE_UNUSED)6072 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
6073 {
6074   return total_frag_text_expansion (fragP);
6075 }
6076 
6077 
6078 /* Translate internal representation of relocation info to BFD target
6079    format.  */
6080 
6081 arelent *
tc_gen_reloc(asection * section ATTRIBUTE_UNUSED,fixS * fixp)6082 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
6083 {
6084   arelent *reloc;
6085 
6086   reloc = XNEW (arelent);
6087   reloc->sym_ptr_ptr = XNEW (asymbol *);
6088   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6089   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6090 
6091   /* Make sure none of our internal relocations make it this far.
6092      They'd better have been fully resolved by this point.  */
6093   gas_assert ((int) fixp->fx_r_type > 0);
6094 
6095   reloc->addend = fixp->fx_offset;
6096 
6097   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
6098   if (reloc->howto == NULL)
6099     {
6100       as_bad_where (fixp->fx_file, fixp->fx_line,
6101 		    _("cannot represent `%s' relocation in object file"),
6102 		    bfd_get_reloc_code_name (fixp->fx_r_type));
6103       free (reloc->sym_ptr_ptr);
6104       free (reloc);
6105       return NULL;
6106     }
6107 
6108   if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
6109     as_fatal (_("internal error; cannot generate `%s' relocation"),
6110 	      bfd_get_reloc_code_name (fixp->fx_r_type));
6111 
6112   return reloc;
6113 }
6114 
6115 
6116 /* Checks for resource conflicts between instructions.  */
6117 
6118 /* The func unit stuff could be implemented as bit-vectors rather
6119    than the iterative approach here.  If it ends up being too
6120    slow, we will switch it.  */
6121 
6122 resource_table *
new_resource_table(void * data,int cycles,int nu,unit_num_copies_func uncf,opcode_num_units_func onuf,opcode_funcUnit_use_unit_func ouuf,opcode_funcUnit_use_stage_func ousf)6123 new_resource_table (void *data,
6124 		    int cycles,
6125 		    int nu,
6126 		    unit_num_copies_func uncf,
6127 		    opcode_num_units_func onuf,
6128 		    opcode_funcUnit_use_unit_func ouuf,
6129 		    opcode_funcUnit_use_stage_func ousf)
6130 {
6131   int i;
6132   resource_table *rt = XNEW (resource_table);
6133   rt->data = data;
6134   rt->cycles = cycles;
6135   rt->allocated_cycles = cycles;
6136   rt->num_units = nu;
6137   rt->unit_num_copies = uncf;
6138   rt->opcode_num_units = onuf;
6139   rt->opcode_unit_use = ouuf;
6140   rt->opcode_unit_stage = ousf;
6141 
6142   rt->units = XCNEWVEC (unsigned char *, cycles);
6143   for (i = 0; i < cycles; i++)
6144     rt->units[i] = XCNEWVEC (unsigned char, nu);
6145 
6146   return rt;
6147 }
6148 
6149 
6150 void
clear_resource_table(resource_table * rt)6151 clear_resource_table (resource_table *rt)
6152 {
6153   int i, j;
6154   for (i = 0; i < rt->allocated_cycles; i++)
6155     for (j = 0; j < rt->num_units; j++)
6156       rt->units[i][j] = 0;
6157 }
6158 
6159 
6160 /* We never shrink it, just fake it into thinking so.  */
6161 
6162 void
resize_resource_table(resource_table * rt,int cycles)6163 resize_resource_table (resource_table *rt, int cycles)
6164 {
6165   int i, old_cycles;
6166 
6167   rt->cycles = cycles;
6168   if (cycles <= rt->allocated_cycles)
6169     return;
6170 
6171   old_cycles = rt->allocated_cycles;
6172   rt->allocated_cycles = cycles;
6173 
6174   rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles);
6175   for (i = 0; i < old_cycles; i++)
6176     rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units);
6177   for (i = old_cycles; i < cycles; i++)
6178     rt->units[i] = XCNEWVEC (unsigned char, rt->num_units);
6179 }
6180 
6181 
6182 bfd_boolean
resources_available(resource_table * rt,xtensa_opcode opcode,int cycle)6183 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
6184 {
6185   int i;
6186   int uses = (rt->opcode_num_units) (rt->data, opcode);
6187 
6188   for (i = 0; i < uses; i++)
6189     {
6190       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6191       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6192       int copies_in_use = rt->units[stage + cycle][unit];
6193       int copies = (rt->unit_num_copies) (rt->data, unit);
6194       if (copies_in_use >= copies)
6195 	return FALSE;
6196     }
6197   return TRUE;
6198 }
6199 
6200 
6201 void
reserve_resources(resource_table * rt,xtensa_opcode opcode,int cycle)6202 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6203 {
6204   int i;
6205   int uses = (rt->opcode_num_units) (rt->data, opcode);
6206 
6207   for (i = 0; i < uses; i++)
6208     {
6209       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6210       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6211       /* Note that this allows resources to be oversubscribed.  That's
6212 	 essential to the way the optional scheduler works.
6213 	 resources_available reports when a resource is over-subscribed,
6214 	 so it's easy to tell.  */
6215       rt->units[stage + cycle][unit]++;
6216     }
6217 }
6218 
6219 
6220 void
release_resources(resource_table * rt,xtensa_opcode opcode,int cycle)6221 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6222 {
6223   int i;
6224   int uses = (rt->opcode_num_units) (rt->data, opcode);
6225 
6226   for (i = 0; i < uses; i++)
6227     {
6228       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6229       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6230       gas_assert (rt->units[stage + cycle][unit] > 0);
6231       rt->units[stage + cycle][unit]--;
6232     }
6233 }
6234 
6235 
6236 /* Wrapper functions make parameterized resource reservation
6237    more convenient.  */
6238 
6239 int
opcode_funcUnit_use_unit(void * data,xtensa_opcode opcode,int idx)6240 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6241 {
6242   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6243   return use->unit;
6244 }
6245 
6246 
6247 int
opcode_funcUnit_use_stage(void * data,xtensa_opcode opcode,int idx)6248 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6249 {
6250   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6251   return use->stage;
6252 }
6253 
6254 
6255 /* Note that this function does not check issue constraints, but
6256    solely whether the hardware is available to execute the given
6257    instructions together.  It also doesn't check if the tinsns
6258    write the same state, or access the same tieports.  That is
6259    checked by check_t1_t2_reads_and_writes.  */
6260 
6261 static bfd_boolean
resources_conflict(vliw_insn * vinsn)6262 resources_conflict (vliw_insn *vinsn)
6263 {
6264   int i;
6265   static resource_table *rt = NULL;
6266 
6267   /* This is the most common case by far.  Optimize it.  */
6268   if (vinsn->num_slots == 1)
6269     return FALSE;
6270 
6271   if (rt == NULL)
6272     {
6273       xtensa_isa isa = xtensa_default_isa;
6274       rt = new_resource_table
6275 	(isa, xtensa_num_pipe_stages,
6276 	 xtensa_isa_num_funcUnits (isa),
6277 	 (unit_num_copies_func) xtensa_funcUnit_num_copies,
6278 	 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6279 	 opcode_funcUnit_use_unit,
6280 	 opcode_funcUnit_use_stage);
6281     }
6282 
6283   clear_resource_table (rt);
6284 
6285   for (i = 0; i < vinsn->num_slots; i++)
6286     {
6287       if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6288 	return TRUE;
6289       reserve_resources (rt, vinsn->slots[i].opcode, 0);
6290     }
6291 
6292   return FALSE;
6293 }
6294 
6295 
6296 /* finish_vinsn, emit_single_op and helper functions.  */
6297 
6298 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6299 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6300 static void xg_assemble_vliw_tokens (vliw_insn *);
6301 
6302 
6303 /* We have reached the end of a bundle; emit into the frag.  */
6304 
6305 static void
finish_vinsn(vliw_insn * vinsn)6306 finish_vinsn (vliw_insn *vinsn)
6307 {
6308   IStack slotstack;
6309   int i;
6310 
6311   if (find_vinsn_conflicts (vinsn))
6312     {
6313       xg_clear_vinsn (vinsn);
6314       return;
6315     }
6316 
6317   /* First, find a format that works.  */
6318   if (vinsn->format == XTENSA_UNDEFINED)
6319     vinsn->format = xg_find_narrowest_format (vinsn);
6320 
6321   if (xtensa_format_num_slots (xtensa_default_isa, vinsn->format) > 1
6322       && produce_flix == FLIX_NONE)
6323     {
6324       as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6325       xg_clear_vinsn (vinsn);
6326       return;
6327     }
6328 
6329   if (vinsn->format == XTENSA_UNDEFINED)
6330     {
6331       as_bad (_("couldn't find a valid instruction format"));
6332       fprintf (stderr, _("    ops were: "));
6333       for (i = 0; i < vinsn->num_slots; i++)
6334 	fprintf (stderr, _(" %s;"),
6335 		 xtensa_opcode_name (xtensa_default_isa,
6336 				     vinsn->slots[i].opcode));
6337       fprintf (stderr, _("\n"));
6338       xg_clear_vinsn (vinsn);
6339       return;
6340     }
6341 
6342   if (vinsn->num_slots
6343       != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
6344     {
6345       as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6346 	      xtensa_format_name (xtensa_default_isa, vinsn->format),
6347 	      xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6348 	      vinsn->num_slots);
6349       xg_clear_vinsn (vinsn);
6350       return;
6351     }
6352 
6353   if (resources_conflict (vinsn))
6354     {
6355       as_bad (_("illegal resource usage in bundle"));
6356       fprintf (stderr, "    ops were: ");
6357       for (i = 0; i < vinsn->num_slots; i++)
6358 	fprintf (stderr, " %s;",
6359 		 xtensa_opcode_name (xtensa_default_isa,
6360 				     vinsn->slots[i].opcode));
6361       fprintf (stderr, "\n");
6362       xg_clear_vinsn (vinsn);
6363       return;
6364     }
6365 
6366   for (i = 0; i < vinsn->num_slots; i++)
6367     {
6368       if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6369 	{
6370 	  symbolS *lit_sym = NULL;
6371 	  int j;
6372 	  bfd_boolean e = FALSE;
6373 	  bfd_boolean saved_density = density_supported;
6374 
6375 	  /* We don't want to narrow ops inside multi-slot bundles.  */
6376 	  if (vinsn->num_slots > 1)
6377 	    density_supported = FALSE;
6378 
6379 	  istack_init (&slotstack);
6380 	  if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6381 	    {
6382 	      vinsn->slots[i].opcode =
6383 		xtensa_format_slot_nop_opcode (xtensa_default_isa,
6384 					       vinsn->format, i);
6385 	      vinsn->slots[i].ntok = 0;
6386 	    }
6387 
6388 	  if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6389 	    {
6390 	      e = TRUE;
6391 	      continue;
6392 	    }
6393 
6394 	  density_supported = saved_density;
6395 
6396 	  if (e)
6397 	    {
6398 	      xg_clear_vinsn (vinsn);
6399 	      return;
6400 	    }
6401 
6402 	  for (j = 0; j < slotstack.ninsn; j++)
6403 	    {
6404 	      TInsn *insn = &slotstack.insn[j];
6405 	      if (insn->insn_type == ITYPE_LITERAL)
6406 		{
6407 		  gas_assert (lit_sym == NULL);
6408 		  lit_sym = xg_assemble_literal (insn);
6409 		}
6410 	      else
6411 		{
6412 		  gas_assert (insn->insn_type == ITYPE_INSN);
6413 		  if (lit_sym)
6414 		    xg_resolve_literals (insn, lit_sym);
6415 		  if (j != slotstack.ninsn - 1)
6416 		    emit_single_op (insn);
6417 		}
6418 	    }
6419 
6420 	  if (vinsn->num_slots > 1)
6421 	    {
6422 	      if (opcode_fits_format_slot
6423 		  (slotstack.insn[slotstack.ninsn - 1].opcode,
6424 		   vinsn->format, i))
6425 		{
6426 		  vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6427 		}
6428 	      else
6429 		{
6430 		  emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6431 		  if (vinsn->format == XTENSA_UNDEFINED)
6432 		    vinsn->slots[i].opcode = xtensa_nop_opcode;
6433 		  else
6434 		    vinsn->slots[i].opcode
6435 		      = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6436 						       vinsn->format, i);
6437 
6438 		  vinsn->slots[i].ntok = 0;
6439 		}
6440 	    }
6441 	  else
6442 	    {
6443 	      vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6444 	      vinsn->format = XTENSA_UNDEFINED;
6445 	    }
6446 	}
6447     }
6448 
6449   /* Now check resource conflicts on the modified bundle.  */
6450   if (resources_conflict (vinsn))
6451     {
6452       as_bad (_("illegal resource usage in bundle"));
6453       fprintf (stderr, "    ops were: ");
6454       for (i = 0; i < vinsn->num_slots; i++)
6455 	fprintf (stderr, " %s;",
6456 		 xtensa_opcode_name (xtensa_default_isa,
6457 				     vinsn->slots[i].opcode));
6458       fprintf (stderr, "\n");
6459       xg_clear_vinsn (vinsn);
6460       return;
6461     }
6462 
6463   /* First, find a format that works.  */
6464   if (vinsn->format == XTENSA_UNDEFINED)
6465       vinsn->format = xg_find_narrowest_format (vinsn);
6466 
6467   xg_assemble_vliw_tokens (vinsn);
6468 
6469   xg_clear_vinsn (vinsn);
6470 
6471   xtensa_check_frag_count ();
6472 }
6473 
6474 
6475 /* Given an vliw instruction, what conflicts are there in register
6476    usage and in writes to states and queues?
6477 
6478    This function does two things:
6479    1. Reports an error when a vinsn contains illegal combinations
6480       of writes to registers states or queues.
6481    2. Marks individual tinsns as not relaxable if the combination
6482       contains antidependencies.
6483 
6484    Job 2 handles things like swap semantics in instructions that need
6485    to be relaxed.  For example,
6486 
6487 	addi a0, a1, 100000
6488 
6489    normally would be relaxed to
6490 
6491 	l32r a0, some_label
6492 	add a0, a1, a0
6493 
6494    _but_, if the above instruction is bundled with an a0 reader, e.g.,
6495 
6496 	{ addi a0, a1, 10000 ; add a2, a0, a4 ; }
6497 
6498    then we can't relax it into
6499 
6500 	l32r a0, some_label
6501 	{ add a0, a1, a0 ; add a2, a0, a4 ; }
6502 
6503    because the value of a0 is trashed before the second add can read it.  */
6504 
6505 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6506 
6507 static bfd_boolean
find_vinsn_conflicts(vliw_insn * vinsn)6508 find_vinsn_conflicts (vliw_insn *vinsn)
6509 {
6510   int i, j;
6511   int branches = 0;
6512   xtensa_isa isa = xtensa_default_isa;
6513 
6514   gas_assert (!past_xtensa_end);
6515 
6516   for (i = 0 ; i < vinsn->num_slots; i++)
6517     {
6518       TInsn *op1 = &vinsn->slots[i];
6519       if (op1->is_specific_opcode)
6520 	op1->keep_wide = TRUE;
6521       else
6522 	op1->keep_wide = FALSE;
6523     }
6524 
6525   for (i = 0 ; i < vinsn->num_slots; i++)
6526     {
6527       TInsn *op1 = &vinsn->slots[i];
6528 
6529       if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6530 	branches++;
6531 
6532       for (j = 0; j < vinsn->num_slots; j++)
6533 	{
6534 	  if (i != j)
6535 	    {
6536 	      TInsn *op2 = &vinsn->slots[j];
6537 	      char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6538 	      switch (conflict_type)
6539 		{
6540 		case 'c':
6541 		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6542 			  xtensa_opcode_name (isa, op1->opcode), i,
6543 			  xtensa_opcode_name (isa, op2->opcode), j);
6544 		  return TRUE;
6545 		case 'd':
6546 		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6547 			  xtensa_opcode_name (isa, op1->opcode), i,
6548 			  xtensa_opcode_name (isa, op2->opcode), j);
6549 		  return TRUE;
6550 		case 'e':
6551 		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6552 			  xtensa_opcode_name (isa, op1->opcode), i,
6553 			  xtensa_opcode_name (isa, op2->opcode), j);
6554 		  return TRUE;
6555 		case 'f':
6556 		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6557 			  xtensa_opcode_name (isa, op1->opcode), i,
6558 			  xtensa_opcode_name (isa, op2->opcode), j);
6559 		  return TRUE;
6560 		default:
6561 		  /* Everything is OK.  */
6562 		  break;
6563 		}
6564 	      op2->is_specific_opcode = (op2->is_specific_opcode
6565 					 || conflict_type == 'a');
6566 	    }
6567 	}
6568     }
6569 
6570   if (branches > 1)
6571     {
6572       as_bad (_("multiple branches or jumps in the same bundle"));
6573       return TRUE;
6574     }
6575 
6576   return FALSE;
6577 }
6578 
6579 
6580 /* Check how the state used by t1 and t2 relate.
6581    Cases found are:
6582 
6583    case A: t1 reads a register t2 writes (an antidependency within a bundle)
6584    case B: no relationship between what is read and written (both could
6585            read the same reg though)
6586    case C: t1 writes a register t2 writes (a register conflict within a
6587            bundle)
6588    case D: t1 writes a state that t2 also writes
6589    case E: t1 writes a tie queue that t2 also writes
6590    case F: two volatile queue accesses
6591 */
6592 
6593 static char
check_t1_t2_reads_and_writes(TInsn * t1,TInsn * t2)6594 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6595 {
6596   xtensa_isa isa = xtensa_default_isa;
6597   xtensa_regfile t1_regfile, t2_regfile;
6598   int t1_reg, t2_reg;
6599   int t1_base_reg, t1_last_reg;
6600   int t2_base_reg, t2_last_reg;
6601   char t1_inout, t2_inout;
6602   int i, j;
6603   char conflict = 'b';
6604   int t1_states;
6605   int t2_states;
6606   int t1_interfaces;
6607   int t2_interfaces;
6608   bfd_boolean t1_volatile = FALSE;
6609   bfd_boolean t2_volatile = FALSE;
6610 
6611   /* Check registers.  */
6612   for (j = 0; j < t2->ntok; j++)
6613     {
6614       if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6615 	continue;
6616 
6617       t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6618       t2_base_reg = t2->tok[j].X_add_number;
6619       t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6620 
6621       for (i = 0; i < t1->ntok; i++)
6622 	{
6623 	  if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6624 	    continue;
6625 
6626 	  t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6627 
6628 	  if (t1_regfile != t2_regfile)
6629 	    continue;
6630 
6631 	  t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6632 	  t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6633 
6634 	  if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6635 	      || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6636 	    {
6637 	      if (t1_inout == 'm' || t1_inout == 'o'
6638 		  || t2_inout == 'm' || t2_inout == 'o')
6639 		{
6640 		  conflict = 'a';
6641 		  continue;
6642 		}
6643 	    }
6644 
6645 	  t1_base_reg = t1->tok[i].X_add_number;
6646 	  t1_last_reg = (t1_base_reg
6647 			 + xtensa_operand_num_regs (isa, t1->opcode, i));
6648 
6649 	  for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6650 	    {
6651 	      for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6652 		{
6653 		  if (t1_reg != t2_reg)
6654 		    continue;
6655 
6656 		  if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6657 		    {
6658 		      conflict = 'a';
6659 		      continue;
6660 		    }
6661 
6662 		  if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6663 		    {
6664 		      conflict = 'a';
6665 		      continue;
6666 		    }
6667 
6668 		  if (t1_inout != 'i' && t2_inout != 'i')
6669 		    return 'c';
6670 		}
6671 	    }
6672 	}
6673     }
6674 
6675   /* Check states.  */
6676   t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6677   t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6678   for (j = 0; j < t2_states; j++)
6679     {
6680       xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6681       t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6682       for (i = 0; i < t1_states; i++)
6683 	{
6684 	  xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6685 	  t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6686 	  if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1)
6687 	    continue;
6688 
6689 	  if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6690 	    {
6691 	      conflict = 'a';
6692 	      continue;
6693 	    }
6694 
6695 	  if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6696 	    {
6697 	      conflict = 'a';
6698 	      continue;
6699 	    }
6700 
6701 	  if (t1_inout != 'i' && t2_inout != 'i')
6702 	    return 'd';
6703 	}
6704     }
6705 
6706   /* Check tieports.  */
6707   t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6708   t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6709   for (j = 0; j < t2_interfaces; j++)
6710     {
6711       xtensa_interface t2_int
6712 	= xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6713       int t2_class = xtensa_interface_class_id (isa, t2_int);
6714 
6715       t2_inout = xtensa_interface_inout (isa, t2_int);
6716       if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6717 	t2_volatile = TRUE;
6718 
6719       for (i = 0; i < t1_interfaces; i++)
6720 	{
6721 	  xtensa_interface t1_int
6722 	    = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6723 	  int t1_class = xtensa_interface_class_id (isa, t1_int);
6724 
6725 	  t1_inout = xtensa_interface_inout (isa, t1_int);
6726 	  if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6727 	    t1_volatile = TRUE;
6728 
6729 	  if (t1_volatile && t2_volatile && (t1_class == t2_class))
6730 	    return 'f';
6731 
6732 	  if (t1_int != t2_int)
6733 	    continue;
6734 
6735 	  if (t2_inout == 'i' && t1_inout == 'o')
6736 	    {
6737 	      conflict = 'a';
6738 	      continue;
6739 	    }
6740 
6741 	  if (t1_inout == 'i' && t2_inout == 'o')
6742 	    {
6743 	      conflict = 'a';
6744 	      continue;
6745 	    }
6746 
6747 	  if (t1_inout != 'i' && t2_inout != 'i')
6748 	    return 'e';
6749 	}
6750     }
6751 
6752   return conflict;
6753 }
6754 
6755 
6756 static xtensa_format
xg_find_narrowest_format(vliw_insn * vinsn)6757 xg_find_narrowest_format (vliw_insn *vinsn)
6758 {
6759   /* Right now we assume that the ops within the vinsn are properly
6760      ordered for the slots that the programmer wanted them in.  In
6761      other words, we don't rearrange the ops in hopes of finding a
6762      better format.  The scheduler handles that.  */
6763 
6764   xtensa_isa isa = xtensa_default_isa;
6765   xtensa_format format;
6766   xtensa_opcode nop_opcode = xtensa_nop_opcode;
6767 
6768   if (vinsn->num_slots == 1)
6769     return xg_get_single_format (vinsn->slots[0].opcode);
6770 
6771   for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6772     {
6773       vliw_insn v_copy;
6774       xg_copy_vinsn (&v_copy, vinsn);
6775       if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6776 	{
6777 	  int slot;
6778 	  int fit = 0;
6779 	  for (slot = 0; slot < v_copy.num_slots; slot++)
6780 	    {
6781 	      if (v_copy.slots[slot].opcode == nop_opcode)
6782 		{
6783 		  v_copy.slots[slot].opcode =
6784 		    xtensa_format_slot_nop_opcode (isa, format, slot);
6785 		  v_copy.slots[slot].ntok = 0;
6786 		}
6787 
6788 	      if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6789 					   format, slot))
6790 		fit++;
6791 	      else if (v_copy.num_slots > 1)
6792 		{
6793 		  TInsn widened;
6794 		  /* Try the widened version.  */
6795 		  if (!v_copy.slots[slot].keep_wide
6796 		      && !v_copy.slots[slot].is_specific_opcode
6797 		      && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6798 						      &widened, TRUE)
6799 		      && opcode_fits_format_slot (widened.opcode,
6800 						  format, slot))
6801 		    {
6802 		      v_copy.slots[slot] = widened;
6803 		      fit++;
6804 		    }
6805 		}
6806 	    }
6807 	  if (fit == v_copy.num_slots)
6808 	    {
6809 	      xg_copy_vinsn (vinsn, &v_copy);
6810 	      xtensa_format_encode (isa, format, vinsn->insnbuf);
6811 	      vinsn->format = format;
6812 	      break;
6813 	    }
6814 	}
6815     }
6816 
6817   if (format == xtensa_isa_num_formats (isa))
6818     return XTENSA_UNDEFINED;
6819 
6820   return format;
6821 }
6822 
6823 
6824 /* Return the additional space needed in a frag
6825    for possible relaxations of any ops in a VLIW insn.
6826    Also fill out the relaxations that might be required of
6827    each tinsn in the vinsn.  */
6828 
6829 static int
relaxation_requirements(vliw_insn * vinsn,bfd_boolean * pfinish_frag)6830 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
6831 {
6832   bfd_boolean finish_frag = FALSE;
6833   int extra_space = 0;
6834   int slot;
6835 
6836   for (slot = 0; slot < vinsn->num_slots; slot++)
6837     {
6838       TInsn *tinsn = &vinsn->slots[slot];
6839       if (!tinsn_has_symbolic_operands (tinsn))
6840 	{
6841 	  /* A narrow instruction could be widened later to help
6842 	     alignment issues.  */
6843 	  if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
6844 	      && !tinsn->is_specific_opcode
6845 	      && vinsn->num_slots == 1)
6846 	    {
6847 	      /* Difference in bytes between narrow and wide insns...  */
6848 	      extra_space += 1;
6849 	      tinsn->subtype = RELAX_NARROW;
6850 	    }
6851 	}
6852       else
6853 	{
6854 	  if (workaround_b_j_loop_end
6855 	      && tinsn->opcode == xtensa_jx_opcode
6856 	      && use_transform ())
6857 	    {
6858 	      /* Add 2 of these.  */
6859 	      extra_space += 3; /* for the nop size */
6860 	      tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6861 	    }
6862 
6863 	  /* Need to assemble it with space for the relocation.  */
6864 	  if (xg_is_relaxable_insn (tinsn, 0)
6865 	      && !tinsn->is_specific_opcode)
6866 	    {
6867 	      int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6868 	      int max_literal_size =
6869 		xg_get_max_insn_widen_literal_size (tinsn->opcode);
6870 
6871 	      tinsn->literal_space = max_literal_size;
6872 
6873 	      tinsn->subtype = RELAX_IMMED;
6874 	      extra_space += max_size;
6875 	    }
6876 	  else
6877 	    {
6878 	      /* A fix record will be added for this instruction prior
6879 		 to relaxation, so make it end the frag.  */
6880 	      finish_frag = TRUE;
6881 	    }
6882 	}
6883     }
6884   *pfinish_frag = finish_frag;
6885   return extra_space;
6886 }
6887 
6888 
6889 static void
bundle_tinsn(TInsn * tinsn,vliw_insn * vinsn)6890 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
6891 {
6892   xtensa_isa isa = xtensa_default_isa;
6893   int slot, chosen_slot;
6894 
6895   vinsn->format = xg_get_single_format (tinsn->opcode);
6896   gas_assert (vinsn->format != XTENSA_UNDEFINED);
6897   vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
6898 
6899   chosen_slot = xg_get_single_slot (tinsn->opcode);
6900   for (slot = 0; slot < vinsn->num_slots; slot++)
6901     {
6902       if (slot == chosen_slot)
6903 	vinsn->slots[slot] = *tinsn;
6904       else
6905 	{
6906 	  vinsn->slots[slot].opcode =
6907 	    xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
6908 	  vinsn->slots[slot].ntok = 0;
6909 	  vinsn->slots[slot].insn_type = ITYPE_INSN;
6910 	}
6911     }
6912 }
6913 
6914 
6915 static bfd_boolean
emit_single_op(TInsn * orig_insn)6916 emit_single_op (TInsn *orig_insn)
6917 {
6918   int i;
6919   IStack istack;		/* put instructions into here */
6920   symbolS *lit_sym = NULL;
6921   symbolS *label_sym = NULL;
6922 
6923   istack_init (&istack);
6924 
6925   /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6926      Because the scheduling and bundling characteristics of movi and
6927      l32r or const16 are so different, we can do much better if we relax
6928      it prior to scheduling and bundling, rather than after.  */
6929   if ((orig_insn->opcode == xtensa_movi_opcode
6930        || orig_insn->opcode == xtensa_movi_n_opcode)
6931       && !cur_vinsn.inside_bundle
6932       && (orig_insn->tok[1].X_op == O_symbol
6933 	  || orig_insn->tok[1].X_op == O_pltrel
6934 	  || orig_insn->tok[1].X_op == O_tlsfunc
6935 	  || orig_insn->tok[1].X_op == O_tlsarg
6936 	  || orig_insn->tok[1].X_op == O_tpoff
6937 	  || orig_insn->tok[1].X_op == O_dtpoff)
6938       && !orig_insn->is_specific_opcode && use_transform ())
6939     xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6940   else
6941     if (xg_expand_assembly_insn (&istack, orig_insn))
6942       return TRUE;
6943 
6944   for (i = 0; i < istack.ninsn; i++)
6945     {
6946       TInsn *insn = &istack.insn[i];
6947       switch (insn->insn_type)
6948 	{
6949 	case ITYPE_LITERAL:
6950 	  gas_assert (lit_sym == NULL);
6951 	  lit_sym = xg_assemble_literal (insn);
6952 	  break;
6953 	case ITYPE_LABEL:
6954 	  {
6955 	    static int relaxed_sym_idx = 0;
6956 	    char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12);
6957 	    sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6958 	    colon (label);
6959 	    gas_assert (label_sym == NULL);
6960 	    label_sym = symbol_find_or_make (label);
6961 	    gas_assert (label_sym);
6962 	    free (label);
6963 	  }
6964 	  break;
6965 	case ITYPE_INSN:
6966 	  {
6967 	    vliw_insn v;
6968 	    if (lit_sym)
6969 	      xg_resolve_literals (insn, lit_sym);
6970 	    if (label_sym)
6971 	      xg_resolve_labels (insn, label_sym);
6972 	    xg_init_vinsn (&v);
6973 	    bundle_tinsn (insn, &v);
6974 	    finish_vinsn (&v);
6975 	    xg_free_vinsn (&v);
6976 	  }
6977 	  break;
6978 	default:
6979 	  gas_assert (0);
6980 	  break;
6981 	}
6982     }
6983   return FALSE;
6984 }
6985 
6986 
6987 static int
total_frag_text_expansion(fragS * fragP)6988 total_frag_text_expansion (fragS *fragP)
6989 {
6990   int slot;
6991   int total_expansion = 0;
6992 
6993   for (slot = 0; slot < config_max_slots; slot++)
6994     total_expansion += fragP->tc_frag_data.text_expansion[slot];
6995 
6996   return total_expansion;
6997 }
6998 
6999 
7000 /* Emit a vliw instruction to the current fragment.  */
7001 
7002 static void
xg_assemble_vliw_tokens(vliw_insn * vinsn)7003 xg_assemble_vliw_tokens (vliw_insn *vinsn)
7004 {
7005   bfd_boolean finish_frag;
7006   bfd_boolean is_jump = FALSE;
7007   bfd_boolean is_branch = FALSE;
7008   xtensa_isa isa = xtensa_default_isa;
7009   int insn_size;
7010   int extra_space;
7011   char *f = NULL;
7012   int slot;
7013   struct dwarf2_line_info debug_line;
7014   bfd_boolean loc_directive_seen = FALSE;
7015   TInsn *tinsn;
7016 
7017   memset (&debug_line, 0, sizeof (struct dwarf2_line_info));
7018 
7019   if (generating_literals)
7020     {
7021       static int reported = 0;
7022       if (reported < 4)
7023 	as_bad_where (frag_now->fr_file, frag_now->fr_line,
7024 		      _("cannot assemble into a literal fragment"));
7025       if (reported == 3)
7026 	as_bad (_("..."));
7027       reported++;
7028       return;
7029     }
7030 
7031   if (frag_now_fix () != 0
7032       && (! frag_now->tc_frag_data.is_insn
7033  	  || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7034  	  || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform
7035  	  || (directive_state[directive_longcalls]
7036 	      != frag_now->tc_frag_data.use_longcalls)
7037  	  || (directive_state[directive_absolute_literals]
7038 	      != frag_now->tc_frag_data.use_absolute_literals)))
7039     {
7040       frag_wane (frag_now);
7041       frag_new (0);
7042       xtensa_set_frag_assembly_state (frag_now);
7043     }
7044 
7045   if (workaround_a0_b_retw
7046       && vinsn->num_slots == 1
7047       && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
7048       && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
7049       && use_transform ())
7050     {
7051       has_a0_b_retw = TRUE;
7052 
7053       /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7054 	 After the first assembly pass we will check all of them and
7055 	 add a nop if needed.  */
7056       frag_now->tc_frag_data.is_insn = TRUE;
7057       frag_var (rs_machine_dependent, 4, 4,
7058 		RELAX_ADD_NOP_IF_A0_B_RETW,
7059 		frag_now->fr_symbol,
7060 		frag_now->fr_offset,
7061 		NULL);
7062       xtensa_set_frag_assembly_state (frag_now);
7063       frag_now->tc_frag_data.is_insn = TRUE;
7064       frag_var (rs_machine_dependent, 4, 4,
7065 		RELAX_ADD_NOP_IF_A0_B_RETW,
7066 		frag_now->fr_symbol,
7067 		frag_now->fr_offset,
7068 		NULL);
7069       xtensa_set_frag_assembly_state (frag_now);
7070     }
7071 
7072   for (slot = 0; slot < vinsn->num_slots; slot++)
7073     {
7074       tinsn = &vinsn->slots[slot];
7075 
7076       /* See if the instruction implies an aligned section.  */
7077       if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1)
7078 	record_alignment (now_seg, 2);
7079 
7080       /* Determine the best line number for debug info.  */
7081       if ((tinsn->loc_directive_seen || !loc_directive_seen)
7082 	  && (tinsn->debug_line.filenum != debug_line.filenum
7083 	      || tinsn->debug_line.line < debug_line.line
7084 	      || tinsn->debug_line.column < debug_line.column))
7085 	debug_line = tinsn->debug_line;
7086       if (tinsn->loc_directive_seen)
7087 	loc_directive_seen = TRUE;
7088     }
7089 
7090   /* Special cases for instructions that force an alignment... */
7091   /* None of these opcodes are bundle-able.  */
7092   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
7093     {
7094       int max_fill;
7095 
7096       /* Remember the symbol that marks the end of the loop in the frag
7097 	 that marks the start of the loop.  This way we can easily find
7098 	 the end of the loop at the beginning, without adding special code
7099 	 to mark the loop instructions themselves.  */
7100       symbolS *target_sym = NULL;
7101       if (vinsn->slots[0].tok[1].X_op == O_symbol)
7102 	target_sym = vinsn->slots[0].tok[1].X_add_symbol;
7103 
7104       xtensa_set_frag_assembly_state (frag_now);
7105       frag_now->tc_frag_data.is_insn = TRUE;
7106 
7107       max_fill = get_text_align_max_fill_size
7108 	(get_text_align_power (xtensa_fetch_width),
7109 	 TRUE, frag_now->tc_frag_data.is_no_density);
7110 
7111       if (use_transform ())
7112 	frag_var (rs_machine_dependent, max_fill, max_fill,
7113 		  RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7114       else
7115 	frag_var (rs_machine_dependent, 0, 0,
7116 		  RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7117       xtensa_set_frag_assembly_state (frag_now);
7118     }
7119 
7120   if (vinsn->slots[0].opcode == xtensa_entry_opcode
7121       && !vinsn->slots[0].is_specific_opcode)
7122     {
7123       xtensa_mark_literal_pool_location ();
7124       xtensa_move_labels (frag_now, 0);
7125       frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
7126     }
7127 
7128   if (vinsn->num_slots == 1)
7129     {
7130       if (workaround_a0_b_retw && use_transform ())
7131 	set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
7132 			     is_register_writer (&vinsn->slots[0], "a", 0));
7133 
7134       set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
7135 			   is_bad_loopend_opcode (&vinsn->slots[0]));
7136     }
7137   else
7138     set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
7139 
7140   insn_size = xtensa_format_length (isa, vinsn->format);
7141 
7142   extra_space = relaxation_requirements (vinsn, &finish_frag);
7143 
7144   /* vinsn_to_insnbuf will produce the error.  */
7145   if (vinsn->format != XTENSA_UNDEFINED)
7146     {
7147       f = frag_more (insn_size + extra_space);
7148       xtensa_set_frag_assembly_state (frag_now);
7149       frag_now->tc_frag_data.is_insn = TRUE;
7150     }
7151 
7152   vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
7153   if (vinsn->format == XTENSA_UNDEFINED)
7154     return;
7155 
7156   xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
7157 
7158   if (debug_type == DEBUG_DWARF2 || loc_directive_seen)
7159     dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space),
7160 			  &debug_line);
7161 
7162   for (slot = 0; slot < vinsn->num_slots; slot++)
7163     {
7164       tinsn = &vinsn->slots[slot];
7165       frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7166       frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7167       frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
7168       frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7169       if (tinsn->opcode == xtensa_l32r_opcode)
7170 	{
7171 	  frag_now->tc_frag_data.literal_frags[slot] =
7172 		  tinsn->tok[1].X_add_symbol->sy_frag;
7173 	}
7174       if (tinsn->literal_space != 0)
7175 	xg_assemble_literal_space (tinsn->literal_space, slot);
7176       frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg;
7177 
7178       if (tinsn->subtype == RELAX_NARROW)
7179 	gas_assert (vinsn->num_slots == 1);
7180       if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7181 	is_jump = TRUE;
7182       if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7183 	is_branch = TRUE;
7184 
7185       if (tinsn->subtype || tinsn->symbol || tinsn->offset
7186 	  || tinsn->literal_frag || is_jump || is_branch)
7187 	finish_frag = TRUE;
7188     }
7189 
7190   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7191     frag_now->tc_frag_data.is_specific_opcode = TRUE;
7192 
7193   if (finish_frag)
7194     {
7195       frag_variant (rs_machine_dependent,
7196 		    extra_space, extra_space, RELAX_SLOTS,
7197 		    frag_now->fr_symbol, frag_now->fr_offset, f);
7198       xtensa_set_frag_assembly_state (frag_now);
7199     }
7200 
7201   /* Special cases for loops:
7202      close_loop_end should be inserted AFTER short_loop.
7203      Make sure that CLOSE loops are processed BEFORE short_loops
7204      when converting them.  */
7205 
7206   /* "short_loop": Add a NOP if the loop is < 4 bytes.  */
7207   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
7208       && !vinsn->slots[0].is_specific_opcode)
7209     {
7210       if (workaround_short_loop && use_transform ())
7211 	{
7212 	  maybe_has_short_loop = TRUE;
7213 	  frag_now->tc_frag_data.is_insn = TRUE;
7214 	  frag_var (rs_machine_dependent, 4, 4,
7215 		    RELAX_ADD_NOP_IF_SHORT_LOOP,
7216 		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
7217 	  frag_now->tc_frag_data.is_insn = TRUE;
7218 	  frag_var (rs_machine_dependent, 4, 4,
7219 		    RELAX_ADD_NOP_IF_SHORT_LOOP,
7220 		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
7221 	}
7222 
7223       /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7224 	 loop at least 12 bytes away from another loop's end.  */
7225       if (workaround_close_loop_end && use_transform ())
7226 	{
7227 	  maybe_has_close_loop_end = TRUE;
7228 	  frag_now->tc_frag_data.is_insn = TRUE;
7229 	  frag_var (rs_machine_dependent, 12, 12,
7230 		    RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7231 		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
7232 	}
7233     }
7234 
7235   if (use_transform ())
7236     {
7237       if (is_jump)
7238 	{
7239 	  gas_assert (finish_frag);
7240 	  frag_var (rs_machine_dependent,
7241 		    xtensa_fetch_width, xtensa_fetch_width,
7242 		    RELAX_UNREACHABLE,
7243 		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
7244 	  xtensa_set_frag_assembly_state (frag_now);
7245 	  xtensa_maybe_create_trampoline_frag ();
7246 	  /* Always create one here.  */
7247 	  xtensa_maybe_create_literal_pool_frag (TRUE, FALSE);
7248 	}
7249       else if (is_branch && do_align_targets ())
7250 	{
7251 	  gas_assert (finish_frag);
7252 	  frag_var (rs_machine_dependent,
7253 		    xtensa_fetch_width, xtensa_fetch_width,
7254 		    RELAX_MAYBE_UNREACHABLE,
7255 		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
7256 	  xtensa_set_frag_assembly_state (frag_now);
7257 	  frag_var (rs_machine_dependent,
7258 		    0, 0,
7259 		    RELAX_MAYBE_DESIRE_ALIGN,
7260 		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
7261 	  xtensa_set_frag_assembly_state (frag_now);
7262 	}
7263     }
7264 
7265   /* Now, if the original opcode was a call...  */
7266   if (do_align_targets ()
7267       && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7268     {
7269       float freq = get_subseg_total_freq (now_seg, now_subseg);
7270       frag_now->tc_frag_data.is_insn = TRUE;
7271       frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7272 		frag_now->fr_symbol, frag_now->fr_offset, NULL);
7273       xtensa_set_frag_assembly_state (frag_now);
7274     }
7275 
7276   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7277     {
7278       frag_wane (frag_now);
7279       frag_new (0);
7280       xtensa_set_frag_assembly_state (frag_now);
7281     }
7282 }
7283 
7284 
7285 /* xtensa_end and helper functions.  */
7286 
7287 static void xtensa_cleanup_align_frags (void);
7288 static void xtensa_fix_target_frags (void);
7289 static void xtensa_mark_narrow_branches (void);
7290 static void xtensa_mark_zcl_first_insns (void);
7291 static void xtensa_mark_difference_of_two_symbols (void);
7292 static void xtensa_fix_a0_b_retw_frags (void);
7293 static void xtensa_fix_b_j_loop_end_frags (void);
7294 static void xtensa_fix_close_loop_end_frags (void);
7295 static void xtensa_fix_short_loop_frags (void);
7296 static void xtensa_sanity_check (void);
7297 static void xtensa_add_config_info (void);
7298 
7299 void
xtensa_end(void)7300 xtensa_end (void)
7301 {
7302   directive_balance ();
7303   xtensa_flush_pending_output ();
7304 
7305   past_xtensa_end = TRUE;
7306 
7307   xtensa_move_literals ();
7308 
7309   xtensa_reorder_segments ();
7310   xtensa_cleanup_align_frags ();
7311   xtensa_fix_target_frags ();
7312   if (workaround_a0_b_retw && has_a0_b_retw)
7313     xtensa_fix_a0_b_retw_frags ();
7314   if (workaround_b_j_loop_end)
7315     xtensa_fix_b_j_loop_end_frags ();
7316 
7317   /* "close_loop_end" should be processed BEFORE "short_loop".  */
7318   if (workaround_close_loop_end && maybe_has_close_loop_end)
7319     xtensa_fix_close_loop_end_frags ();
7320 
7321   if (workaround_short_loop && maybe_has_short_loop)
7322     xtensa_fix_short_loop_frags ();
7323   if (align_targets)
7324     xtensa_mark_narrow_branches ();
7325   xtensa_mark_zcl_first_insns ();
7326 
7327   xtensa_sanity_check ();
7328 
7329   xtensa_add_config_info ();
7330 
7331   xtensa_check_frag_count ();
7332 }
7333 
7334 
7335 struct trampoline_frag
7336 {
7337   struct trampoline_frag *next;
7338   bfd_boolean needs_jump_around;
7339   fragS *fragP;
7340   fixS *fixP;
7341 };
7342 
7343 struct trampoline_seg
7344 {
7345   struct trampoline_seg *next;
7346   asection *seg;
7347   struct trampoline_frag trampoline_list;
7348 };
7349 
7350 static struct trampoline_seg trampoline_seg_list;
7351 #define J_RANGE (128 * 1024)
7352 
7353 static int unreachable_count = 0;
7354 
7355 
7356 static void
xtensa_maybe_create_trampoline_frag(void)7357 xtensa_maybe_create_trampoline_frag (void)
7358 {
7359   if (!use_trampolines)
7360     return;
7361 
7362   /* We create an area for possible trampolines every 10 unreachable frags.
7363      These are preferred over the ones not preceded by an unreachable frag,
7364      because we don't have to jump around them. This function is called after
7365      each RELAX_UNREACHABLE frag is created.  */
7366 
7367   if (++unreachable_count > 10)
7368     {
7369       xtensa_create_trampoline_frag (FALSE);
7370       clear_frag_count ();
7371       unreachable_count = 0;
7372     }
7373 }
7374 
7375 static void
xtensa_check_frag_count(void)7376 xtensa_check_frag_count (void)
7377 {
7378   if (!use_trampolines || frag_now->tc_frag_data.is_no_transform)
7379     return;
7380 
7381   /* We create an area for possible trampolines every 8000 frags or so. This
7382      is an estimate based on the max range of a "j" insn (+/-128K) divided
7383      by a typical frag byte count (16), minus a few for safety. This function
7384      is called after each source line is processed.  */
7385 
7386   if (get_frag_count () > 8000)
7387     {
7388       xtensa_create_trampoline_frag (TRUE);
7389       clear_frag_count ();
7390       unreachable_count = 0;
7391     }
7392 
7393   /* We create an area for a possible literal pool every N (default 5000)
7394      frags or so.  */
7395   xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
7396 }
7397 
7398 static xtensa_insnbuf trampoline_buf = NULL;
7399 static xtensa_insnbuf trampoline_slotbuf = NULL;
7400 
7401 static xtensa_insnbuf litpool_buf = NULL;
7402 static xtensa_insnbuf litpool_slotbuf = NULL;
7403 
7404 #define TRAMPOLINE_FRAG_SIZE 3000
7405 
7406 static void
xtensa_create_trampoline_frag(bfd_boolean needs_jump_around)7407 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around)
7408 {
7409   /* Emit a frag where we can place intermediate jump instructions,
7410      in case we need to jump farther than 128K bytes.
7411      Each jump instruction takes three bytes.
7412      We allocate enough for 1000 trampolines in each frag.
7413      If that's not enough, oh well.  */
7414 
7415   struct trampoline_seg *ts = trampoline_seg_list.next;
7416   struct trampoline_frag *tf;
7417   char *varP;
7418   fragS *fragP;
7419   int size = TRAMPOLINE_FRAG_SIZE;
7420 
7421   for ( ; ts; ts = ts->next)
7422     {
7423       if (ts->seg == now_seg)
7424 	break;
7425     }
7426 
7427   if (ts == NULL)
7428     {
7429       ts = XCNEW(struct trampoline_seg);
7430       ts->next = trampoline_seg_list.next;
7431       trampoline_seg_list.next = ts;
7432       ts->seg = now_seg;
7433     }
7434 
7435   frag_wane (frag_now);
7436   frag_new (0);
7437   xtensa_set_frag_assembly_state (frag_now);
7438   varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL);
7439   fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG);
7440   if (trampoline_buf == NULL)
7441     {
7442       trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa);
7443       trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7444     }
7445   tf = XNEW (struct trampoline_frag);
7446   tf->next = ts->trampoline_list.next;
7447   ts->trampoline_list.next = tf;
7448   tf->needs_jump_around = needs_jump_around;
7449   tf->fragP = fragP;
7450   tf->fixP = NULL;
7451 }
7452 
7453 
7454 static struct trampoline_seg *
find_trampoline_seg(asection * seg)7455 find_trampoline_seg (asection *seg)
7456 {
7457   struct trampoline_seg *ts = trampoline_seg_list.next;
7458 
7459   for ( ; ts; ts = ts->next)
7460     {
7461       if (ts->seg == seg)
7462 	return ts;
7463     }
7464 
7465   return NULL;
7466 }
7467 
7468 
7469 void dump_trampolines (void);
7470 
7471 void
dump_trampolines(void)7472 dump_trampolines (void)
7473 {
7474   struct trampoline_seg *ts = trampoline_seg_list.next;
7475 
7476   for ( ; ts; ts = ts->next)
7477     {
7478       asection *seg = ts->seg;
7479 
7480       if (seg == NULL)
7481 	continue;
7482       fprintf(stderr, "SECTION %s\n", seg->name);
7483       struct trampoline_frag *tf = ts->trampoline_list.next;
7484       for ( ; tf; tf = tf->next)
7485 	{
7486 	  if (tf->fragP == NULL)
7487 	    continue;
7488 	  fprintf(stderr, "   0x%08x: fix=%d, jump_around=%s\n",
7489 		  (int)tf->fragP->fr_address, (int)tf->fragP->fr_fix,
7490 		  tf->needs_jump_around ? "T" : "F");
7491 	}
7492     }
7493 }
7494 
7495 static void dump_litpools (void) __attribute__ ((unused));
7496 
7497 static void
dump_litpools(void)7498 dump_litpools (void)
7499 {
7500   struct litpool_seg *lps = litpool_seg_list.next;
7501   struct litpool_frag *lpf;
7502 
7503   for ( ; lps ; lps = lps->next )
7504     {
7505       printf("litpool seg %s\n", lps->seg->name);
7506       for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next )
7507 	{
7508 	  fragS *litfrag = lpf->fragP->fr_next;
7509 	  int count = 0;
7510 	  while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END)
7511 	    {
7512 	      if (litfrag->fr_fix == 4)
7513 		count++;
7514 	      litfrag = litfrag->fr_next;
7515 	    }
7516 	  printf("   %ld <%d:%d> (%d) [%d]: ",
7517 		 lpf->addr, lpf->priority, lpf->original_priority,
7518 		 lpf->fragP->fr_line, count);
7519 	  //dump_frag(lpf->fragP);
7520 	}
7521     }
7522 }
7523 
7524 static void
xtensa_maybe_create_literal_pool_frag(bfd_boolean create,bfd_boolean only_if_needed)7525 xtensa_maybe_create_literal_pool_frag (bfd_boolean create,
7526 				       bfd_boolean only_if_needed)
7527 {
7528   struct litpool_seg *lps = litpool_seg_list.next;
7529   fragS *fragP;
7530   struct litpool_frag *lpf;
7531   bfd_boolean needed = FALSE;
7532 
7533   if (use_literal_section || !auto_litpools)
7534     return;
7535 
7536   for ( ; lps ; lps = lps->next )
7537     {
7538       if (lps->seg == now_seg)
7539 	break;
7540     }
7541 
7542   if (lps == NULL)
7543     {
7544       lps = XCNEW (struct litpool_seg);
7545       lps->next = litpool_seg_list.next;
7546       litpool_seg_list.next = lps;
7547       lps->seg = now_seg;
7548       lps->frag_list.next = &lps->frag_list;
7549       lps->frag_list.prev = &lps->frag_list;
7550     }
7551 
7552   lps->frag_count++;
7553 
7554   if (create)
7555     {
7556       if (only_if_needed)
7557 	{
7558 	  if (past_xtensa_end || !use_transform() ||
7559 	      frag_now->tc_frag_data.is_no_transform)
7560 	    {
7561 	      return;
7562 	    }
7563 	  if (auto_litpool_limit <= 0)
7564 	    {
7565 	      /* Don't create a litpool based only on frag count.  */
7566 	      return;
7567 	    }
7568 	  else if (lps->frag_count > auto_litpool_limit)
7569 	    {
7570 	      needed = TRUE;
7571 	    }
7572 	  else
7573 	    {
7574 	      return;
7575 	    }
7576 	}
7577       else
7578 	{
7579 	  needed = TRUE;
7580 	}
7581     }
7582 
7583   if (needed)
7584     {
7585       int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn.  */
7586       /* Create a potential site for a literal pool.  */
7587       frag_wane (frag_now);
7588       frag_new (0);
7589       xtensa_set_frag_assembly_state (frag_now);
7590       fragP = frag_now;
7591       fragP->tc_frag_data.lit_frchain = frchain_now;
7592       fragP->tc_frag_data.literal_frag = fragP;
7593       frag_var (rs_machine_dependent, size, size,
7594 		    (only_if_needed) ?
7595 		        RELAX_LITERAL_POOL_CANDIDATE_BEGIN :
7596 		        RELAX_LITERAL_POOL_BEGIN,
7597 		    NULL, 0, NULL);
7598       frag_now->tc_frag_data.lit_seg = now_seg;
7599       frag_variant (rs_machine_dependent, 0, 0,
7600 		    RELAX_LITERAL_POOL_END, NULL, 0, NULL);
7601       xtensa_set_frag_assembly_state (frag_now);
7602     }
7603   else
7604     {
7605       /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7606 	 just record it here.  */
7607       fragP = frag_now;
7608     }
7609 
7610   lpf = XNEW (struct litpool_frag);
7611   /* Insert at tail of circular list.  */
7612   lpf->addr = 0;
7613   lps->frag_list.prev->next = lpf;
7614   lpf->next = &lps->frag_list;
7615   lpf->prev = lps->frag_list.prev;
7616   lps->frag_list.prev = lpf;
7617   lpf->fragP = fragP;
7618   lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1;
7619   lpf->original_priority = lpf->priority;
7620 
7621   lps->frag_count = 0;
7622 }
7623 
7624 static void
xtensa_cleanup_align_frags(void)7625 xtensa_cleanup_align_frags (void)
7626 {
7627   frchainS *frchP;
7628   asection *s;
7629 
7630   for (s = stdoutput->sections; s; s = s->next)
7631     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7632       {
7633 	fragS *fragP;
7634 	/* Walk over all of the fragments in a subsection.  */
7635 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7636 	  {
7637 	    if ((fragP->fr_type == rs_align
7638 		 || fragP->fr_type == rs_align_code
7639 		 || (fragP->fr_type == rs_machine_dependent
7640 		     && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7641 			 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7642 		&& fragP->fr_fix == 0)
7643 	      {
7644 		fragS *next = fragP->fr_next;
7645 
7646 		while (next
7647 		       && next->fr_fix == 0
7648 		       && next->fr_type == rs_machine_dependent
7649 		       && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7650 		  {
7651 		    frag_wane (next);
7652 		    next = next->fr_next;
7653 		  }
7654 	      }
7655 	    /* If we don't widen branch targets, then they
7656 	       will be easier to align.  */
7657 	    if (fragP->tc_frag_data.is_branch_target
7658 		&& fragP->fr_opcode == fragP->fr_literal
7659 		&& fragP->fr_type == rs_machine_dependent
7660 		&& fragP->fr_subtype == RELAX_SLOTS
7661 		&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7662 	      frag_wane (fragP);
7663 	    if (fragP->fr_type == rs_machine_dependent
7664 		&& fragP->fr_subtype == RELAX_UNREACHABLE)
7665 	      fragP->tc_frag_data.is_unreachable = TRUE;
7666 	  }
7667       }
7668 }
7669 
7670 
7671 /* Re-process all of the fragments looking to convert all of the
7672    RELAX_DESIRE_ALIGN_IF_TARGET fragments.  If there is a branch
7673    target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7674    Otherwise, convert to a .fill 0.  */
7675 
7676 static void
xtensa_fix_target_frags(void)7677 xtensa_fix_target_frags (void)
7678 {
7679   frchainS *frchP;
7680   asection *s;
7681 
7682   /* When this routine is called, all of the subsections are still intact
7683      so we walk over subsections instead of sections.  */
7684   for (s = stdoutput->sections; s; s = s->next)
7685     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7686       {
7687 	fragS *fragP;
7688 
7689 	/* Walk over all of the fragments in a subsection.  */
7690 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7691 	  {
7692 	    if (fragP->fr_type == rs_machine_dependent
7693 		&& fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7694 	      {
7695 		if (next_frag_is_branch_target (fragP))
7696 		  fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7697 		else
7698 		  frag_wane (fragP);
7699 	      }
7700 	  }
7701       }
7702 }
7703 
7704 
7705 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7706 
7707 static void
xtensa_mark_narrow_branches(void)7708 xtensa_mark_narrow_branches (void)
7709 {
7710   frchainS *frchP;
7711   asection *s;
7712 
7713   for (s = stdoutput->sections; s; s = s->next)
7714     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7715       {
7716 	fragS *fragP;
7717 	/* Walk over all of the fragments in a subsection.  */
7718 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7719 	  {
7720 	    if (fragP->fr_type == rs_machine_dependent
7721 		&& fragP->fr_subtype == RELAX_SLOTS
7722 		&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7723 	      {
7724 		vliw_insn vinsn;
7725 
7726 		vinsn_from_chars (&vinsn, fragP->fr_opcode);
7727 		tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7728 
7729 		if (vinsn.num_slots == 1
7730 		    && xtensa_opcode_is_branch (xtensa_default_isa,
7731 						vinsn.slots[0].opcode) == 1
7732 		    && xg_get_single_size (vinsn.slots[0].opcode) == 2
7733 		    && is_narrow_branch_guaranteed_in_range (fragP,
7734 							     &vinsn.slots[0]))
7735 		  {
7736 		    fragP->fr_subtype = RELAX_SLOTS;
7737 		    fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7738 		    fragP->tc_frag_data.is_aligning_branch = 1;
7739 		  }
7740 	      }
7741 	  }
7742       }
7743 }
7744 
7745 
7746 /* A branch is typically widened only when its target is out of
7747    range.  However, we would like to widen them to align a subsequent
7748    branch target when possible.
7749 
7750    Because the branch relaxation code is so convoluted, the optimal solution
7751    (combining the two cases) is difficult to get right in all circumstances.
7752    We therefore go with an "almost as good" solution, where we only
7753    use for alignment narrow branches that definitely will not expand to a
7754    jump and a branch.  These functions find and mark these cases.  */
7755 
7756 /* The range in bytes of BNEZ.N and BEQZ.N.  The target operand is encoded
7757    as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7758    We start counting beginning with the frag after the 2-byte branch, so the
7759    maximum offset is (4 - 2) + 63 = 65.  */
7760 #define MAX_IMMED6 65
7761 
7762 static offsetT unrelaxed_frag_max_size (fragS *);
7763 
7764 static bfd_boolean
is_narrow_branch_guaranteed_in_range(fragS * fragP,TInsn * tinsn)7765 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
7766 {
7767   const expressionS *exp = &tinsn->tok[1];
7768   symbolS *symbolP = exp->X_add_symbol;
7769   offsetT max_distance = exp->X_add_number;
7770   fragS *target_frag;
7771 
7772   if (exp->X_op != O_symbol)
7773     return FALSE;
7774 
7775   target_frag = symbol_get_frag (symbolP);
7776 
7777   max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7778   if (is_branch_jmp_to_next (tinsn, fragP))
7779     return FALSE;
7780 
7781   /* The branch doesn't branch over it's own frag,
7782      but over the subsequent ones.  */
7783   fragP = fragP->fr_next;
7784   while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7785     {
7786       max_distance += unrelaxed_frag_max_size (fragP);
7787       fragP = fragP->fr_next;
7788     }
7789   if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7790     return TRUE;
7791   return FALSE;
7792 }
7793 
7794 
7795 static void
xtensa_mark_zcl_first_insns(void)7796 xtensa_mark_zcl_first_insns (void)
7797 {
7798   frchainS *frchP;
7799   asection *s;
7800 
7801   for (s = stdoutput->sections; s; s = s->next)
7802     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7803       {
7804 	fragS *fragP;
7805 	/* Walk over all of the fragments in a subsection.  */
7806 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7807 	  {
7808 	    if (fragP->fr_type == rs_machine_dependent
7809 		&& (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7810 		    || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7811 	      {
7812 		/* Find the loop frag.  */
7813 		fragS *loop_frag = next_non_empty_frag (fragP);
7814 		/* Find the first insn frag.  */
7815 		fragS *targ_frag = next_non_empty_frag (loop_frag);
7816 
7817 	      /* Handle a corner case that comes up in hardware
7818 		 diagnostics.  The original assembly looks like this:
7819 
7820 		 loop aX, LabelA
7821 		 <empty_frag>--not found by next_non_empty_frag
7822 		 loop aY, LabelB
7823 
7824 		 Depending on the start address, the assembler may or
7825 		 may not change it to look something like this:
7826 
7827 		 loop aX, LabelA
7828 		 nop--frag isn't empty anymore
7829 		 loop aY, LabelB
7830 
7831 		 So set up to check the alignment of the nop if it
7832 		 exists  */
7833 		while (loop_frag != targ_frag)
7834 		  {
7835 		    if (loop_frag->fr_type == rs_machine_dependent
7836 			&& (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7837 			    || loop_frag->fr_subtype
7838 			    == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7839 		      targ_frag = loop_frag;
7840 		    else
7841 		      loop_frag = loop_frag->fr_next;
7842 		  }
7843 
7844 		/* Of course, sometimes (mostly for toy test cases) a
7845 		   zero-cost loop instruction is the last in a section.  */
7846 		if (targ_frag)
7847 		  {
7848 		    targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7849 		    /* Do not widen a frag that is the first instruction of a
7850 		       zero-cost loop.  It makes that loop harder to align.  */
7851 		    if (targ_frag->fr_type == rs_machine_dependent
7852 			&& targ_frag->fr_subtype == RELAX_SLOTS
7853 			&& (targ_frag->tc_frag_data.slot_subtypes[0]
7854 			    == RELAX_NARROW))
7855 		      {
7856 			if (targ_frag->tc_frag_data.is_aligning_branch)
7857 			  targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
7858 			else
7859 			  {
7860 			    frag_wane (targ_frag);
7861 			    targ_frag->tc_frag_data.slot_subtypes[0] = 0;
7862 			  }
7863 		      }
7864 		  }
7865 		if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7866 		  frag_wane (fragP);
7867 	      }
7868 	  }
7869       }
7870 }
7871 
7872 
7873 /* When a difference-of-symbols expression is encoded as a uleb128 or
7874    sleb128 value, the linker is unable to adjust that value to account for
7875    link-time relaxation.  Mark all the code between such symbols so that
7876    its size cannot be changed by linker relaxation.  */
7877 
7878 static void
xtensa_mark_difference_of_two_symbols(void)7879 xtensa_mark_difference_of_two_symbols (void)
7880 {
7881   symbolS *expr_sym;
7882 
7883   for (expr_sym = expr_symbols; expr_sym;
7884        expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
7885     {
7886       expressionS *exp = symbol_get_value_expression (expr_sym);
7887 
7888       if (exp->X_op == O_subtract)
7889 	{
7890 	  symbolS *left = exp->X_add_symbol;
7891 	  symbolS *right = exp->X_op_symbol;
7892 
7893 	  /* Difference of two symbols not in the same section
7894 	     are handled with relocations in the linker.  */
7895 	  if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
7896 	    {
7897 	      fragS *start;
7898 	      fragS *end;
7899 	      fragS *walk;
7900 
7901 	      if (symbol_get_frag (left)->fr_address
7902 		  <= symbol_get_frag (right)->fr_address)
7903 		{
7904 		  start = symbol_get_frag (left);
7905 		  end = symbol_get_frag (right);
7906 		}
7907 	      else
7908 		{
7909 		  start = symbol_get_frag (right);
7910 		  end = symbol_get_frag (left);
7911 		}
7912 
7913 	      if (start->tc_frag_data.no_transform_end != NULL)
7914 		walk = start->tc_frag_data.no_transform_end;
7915 	      else
7916 		walk = start;
7917 	      do
7918 		{
7919 		  walk->tc_frag_data.is_no_transform = 1;
7920 		  walk = walk->fr_next;
7921 		}
7922 	      while (walk && walk->fr_address < end->fr_address);
7923 
7924 	      start->tc_frag_data.no_transform_end = walk;
7925 	    }
7926 	}
7927     }
7928 }
7929 
7930 
7931 /* Re-process all of the fragments looking to convert all of the
7932    RELAX_ADD_NOP_IF_A0_B_RETW.  If the next instruction is a
7933    conditional branch or a retw/retw.n, convert this frag to one that
7934    will generate a NOP.  In any case close it off with a .fill 0.  */
7935 
7936 static bfd_boolean next_instrs_are_b_retw (fragS *);
7937 
7938 static void
xtensa_fix_a0_b_retw_frags(void)7939 xtensa_fix_a0_b_retw_frags (void)
7940 {
7941   frchainS *frchP;
7942   asection *s;
7943 
7944   /* When this routine is called, all of the subsections are still intact
7945      so we walk over subsections instead of sections.  */
7946   for (s = stdoutput->sections; s; s = s->next)
7947     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7948       {
7949 	fragS *fragP;
7950 
7951 	/* Walk over all of the fragments in a subsection.  */
7952 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7953 	  {
7954 	    if (fragP->fr_type == rs_machine_dependent
7955 		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7956 	      {
7957 		if (next_instrs_are_b_retw (fragP))
7958 		  {
7959 		    if (fragP->tc_frag_data.is_no_transform)
7960 		      as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7961 		    else
7962 		      relax_frag_add_nop (fragP);
7963 		  }
7964 		frag_wane (fragP);
7965 	      }
7966 	  }
7967       }
7968 }
7969 
7970 
7971 static bfd_boolean
next_instrs_are_b_retw(fragS * fragP)7972 next_instrs_are_b_retw (fragS *fragP)
7973 {
7974   xtensa_opcode opcode;
7975   xtensa_format fmt;
7976   const fragS *next_fragP = next_non_empty_frag (fragP);
7977   static xtensa_insnbuf insnbuf = NULL;
7978   static xtensa_insnbuf slotbuf = NULL;
7979   xtensa_isa isa = xtensa_default_isa;
7980   int offset = 0;
7981   int slot;
7982   bfd_boolean branch_seen = FALSE;
7983 
7984   if (!insnbuf)
7985     {
7986       insnbuf = xtensa_insnbuf_alloc (isa);
7987       slotbuf = xtensa_insnbuf_alloc (isa);
7988     }
7989 
7990   if (next_fragP == NULL)
7991     return FALSE;
7992 
7993   /* Check for the conditional branch.  */
7994   xtensa_insnbuf_from_chars
7995     (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
7996   fmt = xtensa_format_decode (isa, insnbuf);
7997   if (fmt == XTENSA_UNDEFINED)
7998     return FALSE;
7999 
8000   for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8001     {
8002       xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
8003       opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
8004 
8005       branch_seen = (branch_seen
8006 		     || xtensa_opcode_is_branch (isa, opcode) == 1);
8007     }
8008 
8009   if (!branch_seen)
8010     return FALSE;
8011 
8012   offset += xtensa_format_length (isa, fmt);
8013   if (offset == next_fragP->fr_fix)
8014     {
8015       next_fragP = next_non_empty_frag (next_fragP);
8016       offset = 0;
8017     }
8018 
8019   if (next_fragP == NULL)
8020     return FALSE;
8021 
8022   /* Check for the retw/retw.n.  */
8023   xtensa_insnbuf_from_chars
8024     (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8025   fmt = xtensa_format_decode (isa, insnbuf);
8026 
8027   /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8028      have no problems.  */
8029   if (fmt == XTENSA_UNDEFINED
8030       || xtensa_format_num_slots (isa, fmt) != 1)
8031     return FALSE;
8032 
8033   xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
8034   opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
8035 
8036   if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
8037     return TRUE;
8038 
8039   return FALSE;
8040 }
8041 
8042 
8043 /* Re-process all of the fragments looking to convert all of the
8044    RELAX_ADD_NOP_IF_PRE_LOOP_END.  If there is one instruction and a
8045    loop end label, convert this frag to one that will generate a NOP.
8046    In any case close it off with a .fill 0.  */
8047 
8048 static bfd_boolean next_instr_is_loop_end (fragS *);
8049 
8050 static void
xtensa_fix_b_j_loop_end_frags(void)8051 xtensa_fix_b_j_loop_end_frags (void)
8052 {
8053   frchainS *frchP;
8054   asection *s;
8055 
8056   /* When this routine is called, all of the subsections are still intact
8057      so we walk over subsections instead of sections.  */
8058   for (s = stdoutput->sections; s; s = s->next)
8059     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8060       {
8061 	fragS *fragP;
8062 
8063 	/* Walk over all of the fragments in a subsection.  */
8064 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8065 	  {
8066 	    if (fragP->fr_type == rs_machine_dependent
8067 		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
8068 	      {
8069 		if (next_instr_is_loop_end (fragP))
8070 		  {
8071 		    if (fragP->tc_frag_data.is_no_transform)
8072 		      as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8073 		    else
8074 		      relax_frag_add_nop (fragP);
8075 		  }
8076 		frag_wane (fragP);
8077 	      }
8078 	  }
8079       }
8080 }
8081 
8082 
8083 static bfd_boolean
next_instr_is_loop_end(fragS * fragP)8084 next_instr_is_loop_end (fragS *fragP)
8085 {
8086   const fragS *next_fragP;
8087 
8088   if (next_frag_is_loop_target (fragP))
8089     return FALSE;
8090 
8091   next_fragP = next_non_empty_frag (fragP);
8092   if (next_fragP == NULL)
8093     return FALSE;
8094 
8095   if (!next_frag_is_loop_target (next_fragP))
8096     return FALSE;
8097 
8098   /* If the size is >= 3 then there is more than one instruction here.
8099      The hardware bug will not fire.  */
8100   if (next_fragP->fr_fix > 3)
8101     return FALSE;
8102 
8103   return TRUE;
8104 }
8105 
8106 
8107 /* Re-process all of the fragments looking to convert all of the
8108    RELAX_ADD_NOP_IF_CLOSE_LOOP_END.  If there is an loop end that is
8109    not MY loop's loop end within 12 bytes, add enough nops here to
8110    make it at least 12 bytes away.  In any case close it off with a
8111    .fill 0.  */
8112 
8113 static offsetT min_bytes_to_other_loop_end
8114   (fragS *, fragS *, offsetT);
8115 
8116 static void
xtensa_fix_close_loop_end_frags(void)8117 xtensa_fix_close_loop_end_frags (void)
8118 {
8119   frchainS *frchP;
8120   asection *s;
8121 
8122   /* When this routine is called, all of the subsections are still intact
8123      so we walk over subsections instead of sections.  */
8124   for (s = stdoutput->sections; s; s = s->next)
8125     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8126       {
8127 	fragS *fragP;
8128 
8129 	fragS *current_target = NULL;
8130 
8131 	/* Walk over all of the fragments in a subsection.  */
8132 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8133 	  {
8134 	    if (fragP->fr_type == rs_machine_dependent
8135 		&& ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8136 		    || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8137 	      current_target = symbol_get_frag (fragP->fr_symbol);
8138 
8139 	    if (current_target
8140 		&& fragP->fr_type == rs_machine_dependent
8141 		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
8142 	      {
8143 		offsetT min_bytes;
8144 		int bytes_added = 0;
8145 
8146 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8147 		/* Max out at 12.  */
8148 		min_bytes = min_bytes_to_other_loop_end
8149 		  (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
8150 
8151 		if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
8152 		  {
8153 		    if (fragP->tc_frag_data.is_no_transform)
8154 		      as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8155 		    else
8156 		      {
8157 			while (min_bytes + bytes_added
8158 			       < REQUIRED_LOOP_DIVIDING_BYTES)
8159 			  {
8160 			    int length = 3;
8161 
8162 			    if (fragP->fr_var < length)
8163 			      as_fatal (_("fr_var %lu < length %d"),
8164 					(long) fragP->fr_var, length);
8165 			    else
8166 			      {
8167 				assemble_nop (length,
8168 					      fragP->fr_literal + fragP->fr_fix);
8169 				fragP->fr_fix += length;
8170 				fragP->fr_var -= length;
8171 			      }
8172 			    bytes_added += length;
8173 			  }
8174 		      }
8175 		  }
8176 		frag_wane (fragP);
8177 	      }
8178 	    gas_assert (fragP->fr_type != rs_machine_dependent
8179 		    || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
8180 	  }
8181       }
8182 }
8183 
8184 
8185 static offsetT unrelaxed_frag_min_size (fragS *);
8186 
8187 static offsetT
min_bytes_to_other_loop_end(fragS * fragP,fragS * current_target,offsetT max_size)8188 min_bytes_to_other_loop_end (fragS *fragP,
8189 			     fragS *current_target,
8190 			     offsetT max_size)
8191 {
8192   offsetT offset = 0;
8193   fragS *current_fragP;
8194 
8195   for (current_fragP = fragP;
8196        current_fragP;
8197        current_fragP = current_fragP->fr_next)
8198     {
8199       if (current_fragP->tc_frag_data.is_loop_target
8200 	  && current_fragP != current_target)
8201 	return offset;
8202 
8203       offset += unrelaxed_frag_min_size (current_fragP);
8204 
8205       if (offset >= max_size)
8206 	return max_size;
8207     }
8208   return max_size;
8209 }
8210 
8211 
8212 static offsetT
unrelaxed_frag_min_size(fragS * fragP)8213 unrelaxed_frag_min_size (fragS *fragP)
8214 {
8215   offsetT size = fragP->fr_fix;
8216 
8217   /* Add fill size.  */
8218   if (fragP->fr_type == rs_fill)
8219     size += fragP->fr_offset;
8220 
8221   return size;
8222 }
8223 
8224 
8225 static offsetT
unrelaxed_frag_max_size(fragS * fragP)8226 unrelaxed_frag_max_size (fragS *fragP)
8227 {
8228   offsetT size = fragP->fr_fix;
8229   switch (fragP->fr_type)
8230     {
8231     case 0:
8232       /* Empty frags created by the obstack allocation scheme
8233 	 end up with type 0.  */
8234       break;
8235     case rs_fill:
8236     case rs_org:
8237     case rs_space:
8238       size += fragP->fr_offset;
8239       break;
8240     case rs_align:
8241     case rs_align_code:
8242     case rs_align_test:
8243     case rs_leb128:
8244     case rs_cfa:
8245     case rs_dwarf2dbg:
8246       /* No further adjustments needed.  */
8247       break;
8248     case rs_machine_dependent:
8249       if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
8250 	size += fragP->fr_var;
8251       break;
8252     default:
8253       /* We had darn well better know how big it is.  */
8254       gas_assert (0);
8255       break;
8256     }
8257 
8258   return size;
8259 }
8260 
8261 
8262 /* Re-process all of the fragments looking to convert all
8263    of the RELAX_ADD_NOP_IF_SHORT_LOOP.  If:
8264 
8265    A)
8266      1) the instruction size count to the loop end label
8267         is too short (<= 2 instructions),
8268      2) loop has a jump or branch in it
8269 
8270    or B)
8271      1) workaround_all_short_loops is TRUE
8272      2) The generating loop was a  'loopgtz' or 'loopnez'
8273      3) the instruction size count to the loop end label is too short
8274         (<= 2 instructions)
8275    then convert this frag (and maybe the next one) to generate a NOP.
8276    In any case close it off with a .fill 0.  */
8277 
8278 static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
8279 static bfd_boolean branch_before_loop_end (fragS *);
8280 
8281 static void
xtensa_fix_short_loop_frags(void)8282 xtensa_fix_short_loop_frags (void)
8283 {
8284   frchainS *frchP;
8285   asection *s;
8286 
8287   /* When this routine is called, all of the subsections are still intact
8288      so we walk over subsections instead of sections.  */
8289   for (s = stdoutput->sections; s; s = s->next)
8290     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8291       {
8292 	fragS *fragP;
8293 	xtensa_opcode current_opcode = XTENSA_UNDEFINED;
8294 
8295 	/* Walk over all of the fragments in a subsection.  */
8296 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8297 	  {
8298 	    if (fragP->fr_type == rs_machine_dependent
8299 		&& ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8300 		    || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8301 	      {
8302 		TInsn t_insn;
8303 		fragS *loop_frag = next_non_empty_frag (fragP);
8304 		tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
8305 		current_opcode = t_insn.opcode;
8306 		gas_assert (xtensa_opcode_is_loop (xtensa_default_isa,
8307 					       current_opcode) == 1);
8308 	      }
8309 
8310 	    if (fragP->fr_type == rs_machine_dependent
8311 		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8312 	      {
8313 		if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
8314 		    && (branch_before_loop_end (fragP->fr_next)
8315 			|| (workaround_all_short_loops
8316 			    && current_opcode != XTENSA_UNDEFINED
8317 			    && current_opcode != xtensa_loop_opcode)))
8318 		  {
8319 		    if (fragP->tc_frag_data.is_no_transform)
8320 		      as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8321 		    else
8322 		      relax_frag_add_nop (fragP);
8323 		  }
8324 		frag_wane (fragP);
8325 	      }
8326 	  }
8327       }
8328 }
8329 
8330 
8331 static int unrelaxed_frag_min_insn_count (fragS *);
8332 
8333 static int
count_insns_to_loop_end(fragS * base_fragP,bfd_boolean count_relax_add,int max_count)8334 count_insns_to_loop_end (fragS *base_fragP,
8335 			 bfd_boolean count_relax_add,
8336 			 int max_count)
8337 {
8338   fragS *fragP = NULL;
8339   int insn_count = 0;
8340 
8341   fragP = base_fragP;
8342 
8343   for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
8344     {
8345       insn_count += unrelaxed_frag_min_insn_count (fragP);
8346       if (insn_count >= max_count)
8347 	return max_count;
8348 
8349       if (count_relax_add)
8350 	{
8351 	  if (fragP->fr_type == rs_machine_dependent
8352 	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8353 	    {
8354 	      /* In order to add the appropriate number of
8355 	         NOPs, we count an instruction for downstream
8356 	         occurrences.  */
8357 	      insn_count++;
8358 	      if (insn_count >= max_count)
8359 		return max_count;
8360 	    }
8361 	}
8362     }
8363   return insn_count;
8364 }
8365 
8366 
8367 static int
unrelaxed_frag_min_insn_count(fragS * fragP)8368 unrelaxed_frag_min_insn_count (fragS *fragP)
8369 {
8370   xtensa_isa isa = xtensa_default_isa;
8371   static xtensa_insnbuf insnbuf = NULL;
8372   int insn_count = 0;
8373   int offset = 0;
8374 
8375   if (!fragP->tc_frag_data.is_insn)
8376     return insn_count;
8377 
8378   if (!insnbuf)
8379     insnbuf = xtensa_insnbuf_alloc (isa);
8380 
8381   /* Decode the fixed instructions.  */
8382   while (offset < fragP->fr_fix)
8383     {
8384       xtensa_format fmt;
8385 
8386       xtensa_insnbuf_from_chars
8387 	(isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8388       fmt = xtensa_format_decode (isa, insnbuf);
8389 
8390       if (fmt == XTENSA_UNDEFINED)
8391 	{
8392 	  as_fatal (_("undecodable instruction in instruction frag"));
8393 	  return insn_count;
8394 	}
8395       offset += xtensa_format_length (isa, fmt);
8396       insn_count++;
8397     }
8398 
8399   return insn_count;
8400 }
8401 
8402 
8403 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
8404 
8405 static bfd_boolean
branch_before_loop_end(fragS * base_fragP)8406 branch_before_loop_end (fragS *base_fragP)
8407 {
8408   fragS *fragP;
8409 
8410   for (fragP = base_fragP;
8411        fragP && !fragP->tc_frag_data.is_loop_target;
8412        fragP = fragP->fr_next)
8413     {
8414       if (unrelaxed_frag_has_b_j (fragP))
8415 	return TRUE;
8416     }
8417   return FALSE;
8418 }
8419 
8420 
8421 static bfd_boolean
unrelaxed_frag_has_b_j(fragS * fragP)8422 unrelaxed_frag_has_b_j (fragS *fragP)
8423 {
8424   static xtensa_insnbuf insnbuf = NULL;
8425   xtensa_isa isa = xtensa_default_isa;
8426   int offset = 0;
8427 
8428   if (!fragP->tc_frag_data.is_insn)
8429     return FALSE;
8430 
8431   if (!insnbuf)
8432     insnbuf = xtensa_insnbuf_alloc (isa);
8433 
8434   /* Decode the fixed instructions.  */
8435   while (offset < fragP->fr_fix)
8436     {
8437       xtensa_format fmt;
8438       int slot;
8439 
8440       xtensa_insnbuf_from_chars
8441 	(isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8442       fmt = xtensa_format_decode (isa, insnbuf);
8443       if (fmt == XTENSA_UNDEFINED)
8444 	return FALSE;
8445 
8446       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8447 	{
8448 	  xtensa_opcode opcode =
8449 	    get_opcode_from_buf (fragP->fr_literal + offset, slot);
8450 	  if (xtensa_opcode_is_branch (isa, opcode) == 1
8451 	      || xtensa_opcode_is_jump (isa, opcode) == 1)
8452 	    return TRUE;
8453 	}
8454       offset += xtensa_format_length (isa, fmt);
8455     }
8456   return FALSE;
8457 }
8458 
8459 
8460 /* Checks to be made after initial assembly but before relaxation.  */
8461 
8462 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
8463 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
8464 
8465 static void
xtensa_sanity_check(void)8466 xtensa_sanity_check (void)
8467 {
8468   const char *file_name;
8469   unsigned line;
8470   frchainS *frchP;
8471   asection *s;
8472 
8473   file_name = as_where (&line);
8474   for (s = stdoutput->sections; s; s = s->next)
8475     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8476       {
8477 	fragS *fragP;
8478 
8479 	/* Walk over all of the fragments in a subsection.  */
8480 	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8481 	  {
8482 	    if (fragP->fr_type == rs_machine_dependent
8483 		&& fragP->fr_subtype == RELAX_SLOTS
8484 		&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8485 	      {
8486 		static xtensa_insnbuf insnbuf = NULL;
8487 		TInsn t_insn;
8488 
8489 		if (fragP->fr_opcode != NULL)
8490 		  {
8491 		    if (!insnbuf)
8492 		      insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
8493 		    tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8494 		    tinsn_immed_from_frag (&t_insn, fragP, 0);
8495 
8496 		    if (xtensa_opcode_is_loop (xtensa_default_isa,
8497 					       t_insn.opcode) == 1)
8498 		      {
8499 			if (is_empty_loop (&t_insn, fragP))
8500 			  {
8501 			    new_logical_line (fragP->fr_file, fragP->fr_line);
8502 			    as_bad (_("invalid empty loop"));
8503 			  }
8504 			if (!is_local_forward_loop (&t_insn, fragP))
8505 			  {
8506 			    new_logical_line (fragP->fr_file, fragP->fr_line);
8507 			    as_bad (_("loop target does not follow "
8508 				      "loop instruction in section"));
8509 			  }
8510 		      }
8511 		  }
8512 	      }
8513 	  }
8514       }
8515   new_logical_line (file_name, line);
8516 }
8517 
8518 
8519 #define LOOP_IMMED_OPN 1
8520 
8521 /* Return TRUE if the loop target is the next non-zero fragment.  */
8522 
8523 static bfd_boolean
is_empty_loop(const TInsn * insn,fragS * fragP)8524 is_empty_loop (const TInsn *insn, fragS *fragP)
8525 {
8526   const expressionS *exp;
8527   symbolS *symbolP;
8528   fragS *next_fragP;
8529 
8530   if (insn->insn_type != ITYPE_INSN)
8531     return FALSE;
8532 
8533   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8534     return FALSE;
8535 
8536   if (insn->ntok <= LOOP_IMMED_OPN)
8537     return FALSE;
8538 
8539   exp = &insn->tok[LOOP_IMMED_OPN];
8540 
8541   if (exp->X_op != O_symbol)
8542     return FALSE;
8543 
8544   symbolP = exp->X_add_symbol;
8545   if (!symbolP)
8546     return FALSE;
8547 
8548   if (symbol_get_frag (symbolP) == NULL)
8549     return FALSE;
8550 
8551   if (S_GET_VALUE (symbolP) != 0)
8552     return FALSE;
8553 
8554   /* Walk through the zero-size fragments from this one.  If we find
8555      the target fragment, then this is a zero-size loop.  */
8556 
8557   for (next_fragP = fragP->fr_next;
8558        next_fragP != NULL;
8559        next_fragP = next_fragP->fr_next)
8560     {
8561       if (next_fragP == symbol_get_frag (symbolP))
8562 	return TRUE;
8563       if (next_fragP->fr_fix != 0)
8564 	return FALSE;
8565     }
8566   return FALSE;
8567 }
8568 
8569 
8570 static bfd_boolean
is_local_forward_loop(const TInsn * insn,fragS * fragP)8571 is_local_forward_loop (const TInsn *insn, fragS *fragP)
8572 {
8573   const expressionS *exp;
8574   symbolS *symbolP;
8575   fragS *next_fragP;
8576 
8577   if (insn->insn_type != ITYPE_INSN)
8578     return FALSE;
8579 
8580   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8581     return FALSE;
8582 
8583   if (insn->ntok <= LOOP_IMMED_OPN)
8584     return FALSE;
8585 
8586   exp = &insn->tok[LOOP_IMMED_OPN];
8587 
8588   if (exp->X_op != O_symbol)
8589     return FALSE;
8590 
8591   symbolP = exp->X_add_symbol;
8592   if (!symbolP)
8593     return FALSE;
8594 
8595   if (symbol_get_frag (symbolP) == NULL)
8596     return FALSE;
8597 
8598   /* Walk through fragments until we find the target.
8599      If we do not find the target, then this is an invalid loop.  */
8600 
8601   for (next_fragP = fragP->fr_next;
8602        next_fragP != NULL;
8603        next_fragP = next_fragP->fr_next)
8604     {
8605       if (next_fragP == symbol_get_frag (symbolP))
8606 	return TRUE;
8607     }
8608 
8609   return FALSE;
8610 }
8611 
8612 
8613 #define XTINFO_NAME "Xtensa_Info"
8614 #define XTINFO_NAMESZ 12
8615 #define XTINFO_TYPE 1
8616 
8617 static void
xtensa_add_config_info(void)8618 xtensa_add_config_info (void)
8619 {
8620   asection *info_sec;
8621   char *data, *p;
8622   int sz;
8623 
8624   info_sec = subseg_new (".xtensa.info", 0);
8625   bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
8626 
8627   data = XNEWVEC (char, 100);
8628   sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8629 	   XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI);
8630   sz = strlen (data) + 1;
8631 
8632   /* Add enough null terminators to pad to a word boundary.  */
8633   do
8634     data[sz++] = 0;
8635   while ((sz & 3) != 0);
8636 
8637   /* Follow the standard note section layout:
8638      First write the length of the name string.  */
8639   p = frag_more (4);
8640   md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
8641 
8642   /* Next comes the length of the "descriptor", i.e., the actual data.  */
8643   p = frag_more (4);
8644   md_number_to_chars (p, (valueT) sz, 4);
8645 
8646   /* Write the note type.  */
8647   p = frag_more (4);
8648   md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
8649 
8650   /* Write the name field.  */
8651   p = frag_more (XTINFO_NAMESZ);
8652   memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
8653 
8654   /* Finally, write the descriptor.  */
8655   p = frag_more (sz);
8656   memcpy (p, data, sz);
8657 
8658   free (data);
8659 }
8660 
8661 
8662 /* Alignment Functions.  */
8663 
8664 static int
get_text_align_power(unsigned target_size)8665 get_text_align_power (unsigned target_size)
8666 {
8667   if (target_size <= 4)
8668     return 2;
8669 
8670   if (target_size <= 8)
8671     return 3;
8672 
8673   if (target_size <= 16)
8674     return 4;
8675 
8676   if (target_size <= 32)
8677     return 5;
8678 
8679   if (target_size <= 64)
8680     return 6;
8681 
8682   if (target_size <= 128)
8683     return 7;
8684 
8685   if (target_size <= 256)
8686     return 8;
8687 
8688   if (target_size <= 512)
8689     return 9;
8690 
8691   if (target_size <= 1024)
8692     return 10;
8693 
8694   gas_assert (0);
8695   return 0;
8696 }
8697 
8698 
8699 static int
get_text_align_max_fill_size(int align_pow,bfd_boolean use_nops,bfd_boolean use_no_density)8700 get_text_align_max_fill_size (int align_pow,
8701 			      bfd_boolean use_nops,
8702 			      bfd_boolean use_no_density)
8703 {
8704   if (!use_nops)
8705     return (1 << align_pow);
8706   if (use_no_density)
8707     return 3 * (1 << align_pow);
8708 
8709   return 1 + (1 << align_pow);
8710 }
8711 
8712 
8713 /* Calculate the minimum bytes of fill needed at "address" to align a
8714    target instruction of size "target_size" so that it does not cross a
8715    power-of-two boundary specified by "align_pow".  If "use_nops" is FALSE,
8716    the fill can be an arbitrary number of bytes.  Otherwise, the space must
8717    be filled by NOP instructions.  */
8718 
8719 static int
get_text_align_fill_size(addressT address,int align_pow,int target_size,bfd_boolean use_nops,bfd_boolean use_no_density)8720 get_text_align_fill_size (addressT address,
8721 			  int align_pow,
8722 			  int target_size,
8723 			  bfd_boolean use_nops,
8724 			  bfd_boolean use_no_density)
8725 {
8726   addressT alignment, fill, fill_limit, fill_step;
8727   bfd_boolean skip_one = FALSE;
8728 
8729   alignment = (1 << align_pow);
8730   gas_assert (target_size > 0 && alignment >= (addressT) target_size);
8731 
8732   if (!use_nops)
8733     {
8734       fill_limit = alignment;
8735       fill_step = 1;
8736     }
8737   else if (!use_no_density)
8738     {
8739       /* Combine 2- and 3-byte NOPs to fill anything larger than one.  */
8740       fill_limit = alignment * 2;
8741       fill_step = 1;
8742       skip_one = TRUE;
8743     }
8744   else
8745     {
8746       /* Fill with 3-byte NOPs -- can only fill multiples of 3.  */
8747       fill_limit = alignment * 3;
8748       fill_step = 3;
8749     }
8750 
8751   /* Try all fill sizes until finding one that works.  */
8752   for (fill = 0; fill < fill_limit; fill += fill_step)
8753     {
8754       if (skip_one && fill == 1)
8755 	continue;
8756       if ((address + fill) >> align_pow
8757 	  == (address + fill + target_size - 1) >> align_pow)
8758 	return fill;
8759     }
8760   gas_assert (0);
8761   return 0;
8762 }
8763 
8764 
8765 static int
branch_align_power(segT sec)8766 branch_align_power (segT sec)
8767 {
8768   /* If the Xtensa processor has a fetch width of X, and
8769      the section is aligned to at least that boundary, then a branch
8770      target need only fit within that aligned block of memory to avoid
8771      a stall.  Otherwise, try to fit branch targets within 4-byte
8772      aligned blocks (which may be insufficient, e.g., if the section
8773      has no alignment, but it's good enough).  */
8774   int fetch_align = get_text_align_power(xtensa_fetch_width);
8775   int sec_align = get_recorded_alignment (sec);
8776 
8777   if (sec_align >= fetch_align)
8778     return fetch_align;
8779 
8780   return 2;
8781 }
8782 
8783 
8784 /* This will assert if it is not possible.  */
8785 
8786 static int
get_text_align_nop_count(offsetT fill_size,bfd_boolean use_no_density)8787 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
8788 {
8789   int count = 0;
8790 
8791   if (use_no_density)
8792     {
8793       gas_assert (fill_size % 3 == 0);
8794       return (fill_size / 3);
8795     }
8796 
8797   gas_assert (fill_size != 1);	/* Bad argument.  */
8798 
8799   while (fill_size > 1)
8800     {
8801       int insn_size = 3;
8802       if (fill_size == 2 || fill_size == 4)
8803 	insn_size = 2;
8804       fill_size -= insn_size;
8805       count++;
8806     }
8807   gas_assert (fill_size != 1);	/* Bad algorithm.  */
8808   return count;
8809 }
8810 
8811 
8812 static int
get_text_align_nth_nop_size(offsetT fill_size,int n,bfd_boolean use_no_density)8813 get_text_align_nth_nop_size (offsetT fill_size,
8814 			     int n,
8815 			     bfd_boolean use_no_density)
8816 {
8817   int count = 0;
8818 
8819   if (use_no_density)
8820     return 3;
8821 
8822   gas_assert (fill_size != 1);	/* Bad argument.  */
8823 
8824   while (fill_size > 1)
8825     {
8826       int insn_size = 3;
8827       if (fill_size == 2 || fill_size == 4)
8828 	insn_size = 2;
8829       fill_size -= insn_size;
8830       count++;
8831       if (n + 1 == count)
8832 	return insn_size;
8833     }
8834   gas_assert (0);
8835   return 0;
8836 }
8837 
8838 
8839 /* For the given fragment, find the appropriate address
8840    for it to begin at if we are using NOPs to align it.  */
8841 
8842 static addressT
get_noop_aligned_address(fragS * fragP,addressT address)8843 get_noop_aligned_address (fragS *fragP, addressT address)
8844 {
8845   /* The rule is: get next fragment's FIRST instruction.  Find
8846      the smallest number of bytes that need to be added to
8847      ensure that the next fragment's FIRST instruction will fit
8848      in a single word.
8849 
8850      E.G.,   2 bytes : 0, 1, 2 mod 4
8851 	     3 bytes: 0, 1 mod 4
8852 
8853      If the FIRST instruction MIGHT be relaxed,
8854      assume that it will become a 3-byte instruction.
8855 
8856      Note again here that LOOP instructions are not bundleable,
8857      and this relaxation only applies to LOOP opcodes.  */
8858 
8859   int fill_size = 0;
8860   int first_insn_size;
8861   int loop_insn_size;
8862   addressT pre_opcode_bytes;
8863   int align_power;
8864   fragS *first_insn;
8865   xtensa_opcode opcode;
8866   bfd_boolean is_loop;
8867 
8868   gas_assert (fragP->fr_type == rs_machine_dependent);
8869   gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
8870 
8871   /* Find the loop frag.  */
8872   first_insn = next_non_empty_frag (fragP);
8873   /* Now find the first insn frag.  */
8874   first_insn = next_non_empty_frag (first_insn);
8875 
8876   is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8877   gas_assert (is_loop);
8878   loop_insn_size = xg_get_single_size (opcode);
8879 
8880   pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8881   pre_opcode_bytes += loop_insn_size;
8882 
8883   /* For loops, the alignment depends on the size of the
8884      instruction following the loop, not the LOOP instruction.  */
8885 
8886   if (first_insn == NULL)
8887     first_insn_size = xtensa_fetch_width;
8888   else
8889     first_insn_size = get_loop_align_size (frag_format_size (first_insn));
8890 
8891   /* If it was 8, then we'll need a larger alignment for the section.  */
8892   align_power = get_text_align_power (first_insn_size);
8893   record_alignment (now_seg, align_power);
8894 
8895   fill_size = get_text_align_fill_size
8896     (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
8897      fragP->tc_frag_data.is_no_density);
8898 
8899   return address + fill_size;
8900 }
8901 
8902 
8903 /* 3 mechanisms for relaxing an alignment:
8904 
8905    Align to a power of 2.
8906    Align so the next fragment's instruction does not cross a word boundary.
8907    Align the current instruction so that if the next instruction
8908        were 3 bytes, it would not cross a word boundary.
8909 
8910    We can align with:
8911 
8912    zeros    - This is easy; always insert zeros.
8913    nops     - 3-byte and 2-byte instructions
8914               2 - 2-byte nop
8915               3 - 3-byte nop
8916               4 - 2 2-byte nops
8917               >=5 : 3-byte instruction + fn (n-3)
8918    widening - widen previous instructions.  */
8919 
8920 static offsetT
get_aligned_diff(fragS * fragP,addressT address,offsetT * max_diff)8921 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
8922 {
8923   addressT target_address, loop_insn_offset;
8924   int target_size;
8925   xtensa_opcode loop_opcode;
8926   bfd_boolean is_loop;
8927   int align_power;
8928   offsetT opt_diff;
8929   offsetT branch_align;
8930   fragS *loop_frag;
8931 
8932   gas_assert (fragP->fr_type == rs_machine_dependent);
8933   switch (fragP->fr_subtype)
8934     {
8935     case RELAX_DESIRE_ALIGN:
8936       target_size = next_frag_format_size (fragP);
8937       if (target_size == XTENSA_UNDEFINED)
8938 	target_size = 3;
8939       align_power = branch_align_power (now_seg);
8940       branch_align = 1 << align_power;
8941       /* Don't count on the section alignment being as large as the target.  */
8942       if (target_size > branch_align)
8943 	target_size = branch_align;
8944       opt_diff = get_text_align_fill_size (address, align_power,
8945 					   target_size, FALSE, FALSE);
8946 
8947       *max_diff = (opt_diff + branch_align
8948 		   - (target_size + ((address + opt_diff) % branch_align)));
8949       gas_assert (*max_diff >= opt_diff);
8950       return opt_diff;
8951 
8952     case RELAX_ALIGN_NEXT_OPCODE:
8953       /* The next non-empty frag after this one holds the LOOP instruction
8954 	 that needs to be aligned.  The required alignment depends on the
8955 	 size of the next non-empty frag after the loop frag, i.e., the
8956 	 first instruction in the loop.  */
8957       loop_frag = next_non_empty_frag (fragP);
8958       target_size = get_loop_align_size (next_frag_format_size (loop_frag));
8959       loop_insn_offset = 0;
8960       is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8961       gas_assert (is_loop);
8962 
8963       /* If the loop has been expanded then the LOOP instruction
8964 	 could be at an offset from this fragment.  */
8965       if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED)
8966 	loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8967 
8968       /* In an ideal world, which is what we are shooting for here,
8969 	 we wouldn't need to use any NOPs immediately prior to the
8970 	 LOOP instruction.  If this approach fails, relax_frag_loop_align
8971 	 will call get_noop_aligned_address.  */
8972       target_address =
8973 	address + loop_insn_offset + xg_get_single_size (loop_opcode);
8974       align_power = get_text_align_power (target_size);
8975       opt_diff = get_text_align_fill_size (target_address, align_power,
8976 					   target_size, FALSE, FALSE);
8977 
8978       *max_diff = xtensa_fetch_width
8979 	- ((target_address + opt_diff) % xtensa_fetch_width)
8980 	- target_size + opt_diff;
8981       gas_assert (*max_diff >= opt_diff);
8982       return opt_diff;
8983 
8984     default:
8985       break;
8986     }
8987   gas_assert (0);
8988   return 0;
8989 }
8990 
8991 
8992 /* md_relax_frag Hook and Helper Functions.  */
8993 
8994 static long relax_frag_loop_align (fragS *, long);
8995 static long relax_frag_for_align (fragS *, long);
8996 static long relax_frag_immed
8997   (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8998 
8999 typedef struct cached_fixup cached_fixupS;
9000 struct cached_fixup
9001 {
9002   int addr;
9003   int target;
9004   int delta;
9005   fixS *fixP;
9006 };
9007 
9008 typedef struct fixup_cache fixup_cacheS;
9009 struct fixup_cache
9010 {
9011   cached_fixupS *fixups;
9012   unsigned n_fixups;
9013   unsigned n_max;
9014 
9015   segT seg;
9016   fragS *first_frag;
9017 };
9018 
fixup_order(const void * a,const void * b)9019 static int fixup_order (const void *a, const void *b)
9020 {
9021   const cached_fixupS *pa = a;
9022   const cached_fixupS *pb = b;
9023 
9024   if (pa->addr == pb->addr)
9025     {
9026       if (pa->target == pb->target)
9027 	{
9028 	  if (pa->fixP->fx_r_type == pb->fixP->fx_r_type)
9029 	    return 0;
9030 	  return pa->fixP->fx_r_type < pb->fixP->fx_r_type ?  -1 : 1;
9031 	}
9032       return pa->target - pb->target;
9033     }
9034   return pa->addr - pb->addr;
9035 }
9036 
xtensa_make_cached_fixup(cached_fixupS * o,fixS * fixP)9037 static bfd_boolean xtensa_make_cached_fixup (cached_fixupS *o, fixS *fixP)
9038 {
9039   xtensa_isa isa = xtensa_default_isa;
9040   int addr = fixP->fx_frag->fr_address;
9041   int target;
9042   int delta;
9043   symbolS *s = fixP->fx_addsy;
9044   int slot;
9045   xtensa_format fmt;
9046   xtensa_opcode opcode;
9047 
9048   if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP ||
9049       fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP)
9050     return FALSE;
9051   target = S_GET_VALUE (s);
9052   delta = target - addr;
9053 
9054   if (abs(delta) < J_RANGE / 2)
9055     return FALSE;
9056 
9057   xtensa_insnbuf_from_chars (isa, trampoline_buf,
9058 			     (unsigned char *) fixP->fx_frag->fr_literal +
9059 			     fixP->fx_where, 0);
9060   fmt = xtensa_format_decode (isa, trampoline_buf);
9061   gas_assert (fmt != XTENSA_UNDEFINED);
9062   slot = fixP->tc_fix_data.slot;
9063   xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf);
9064   opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf);
9065   if (opcode != xtensa_j_opcode)
9066     return FALSE;
9067 
9068   o->addr = addr;
9069   o->target = target;
9070   o->delta = delta;
9071   o->fixP = fixP;
9072 
9073   return TRUE;
9074 }
9075 
xtensa_realloc_fixup_cache(fixup_cacheS * cache,unsigned add)9076 static void xtensa_realloc_fixup_cache (fixup_cacheS *cache, unsigned add)
9077 {
9078   if (cache->n_fixups + add > cache->n_max)
9079     {
9080       cache->n_max = (cache->n_fixups + add) * 2;
9081       cache->fixups = XRESIZEVEC (cached_fixupS, cache->fixups, cache->n_max);
9082     }
9083 }
9084 
xtensa_cache_relaxable_fixups(fixup_cacheS * cache,segment_info_type * seginfo)9085 static void xtensa_cache_relaxable_fixups (fixup_cacheS *cache,
9086 					   segment_info_type *seginfo)
9087 {
9088   fixS *fixP;
9089 
9090   cache->n_fixups = 0;
9091 
9092   for (fixP = seginfo->fix_root; fixP ; fixP = fixP->fx_next)
9093     {
9094       xtensa_realloc_fixup_cache (cache, 1);
9095 
9096       if (xtensa_make_cached_fixup (cache->fixups + cache->n_fixups, fixP))
9097 	++cache->n_fixups;
9098     }
9099   qsort (cache->fixups, cache->n_fixups, sizeof (*cache->fixups), fixup_order);
9100 }
9101 
xtensa_find_first_cached_fixup(const fixup_cacheS * cache,int addr)9102 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS *cache,
9103 						int addr)
9104 {
9105   unsigned a = 0;
9106   unsigned b = cache->n_fixups;
9107 
9108   while (b - a > 1)
9109     {
9110       unsigned c = (a + b) / 2;
9111 
9112       if (cache->fixups[c].addr < addr)
9113 	a = c;
9114       else
9115 	b = c;
9116     }
9117   return a;
9118 }
9119 
xtensa_delete_cached_fixup(fixup_cacheS * cache,unsigned i)9120 static void xtensa_delete_cached_fixup (fixup_cacheS *cache, unsigned i)
9121 {
9122   memmove (cache->fixups + i, cache->fixups + i + 1,
9123 	   (cache->n_fixups - i - 1) * sizeof (*cache->fixups));
9124   --cache->n_fixups;
9125 }
9126 
xtensa_add_cached_fixup(fixup_cacheS * cache,fixS * fixP)9127 static bfd_boolean xtensa_add_cached_fixup (fixup_cacheS *cache, fixS *fixP)
9128 {
9129   cached_fixupS o;
9130   unsigned i;
9131 
9132   if (!xtensa_make_cached_fixup (&o, fixP))
9133     return FALSE;
9134   xtensa_realloc_fixup_cache (cache, 1);
9135   i = xtensa_find_first_cached_fixup (cache, o.addr);
9136   if (i < cache->n_fixups)
9137     {
9138       ++i;
9139       memmove (cache->fixups + i + 1, cache->fixups + i,
9140 	       (cache->n_fixups - i) * sizeof (*cache->fixups));
9141     }
9142   cache->fixups[i] = o;
9143   ++cache->n_fixups;
9144   return TRUE;
9145 }
9146 
9147 /* Return the number of bytes added to this fragment, given that the
9148    input has been stretched already by "stretch".  */
9149 
9150 long
xtensa_relax_frag(fragS * fragP,long stretch,int * stretched_p)9151 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
9152 {
9153   xtensa_isa isa = xtensa_default_isa;
9154   int unreported = fragP->tc_frag_data.unreported_expansion;
9155   long new_stretch = 0;
9156   const char *file_name;
9157   unsigned line;
9158   int lit_size;
9159   static xtensa_insnbuf vbuf = NULL;
9160   int slot, num_slots;
9161   xtensa_format fmt;
9162 
9163   file_name = as_where (&line);
9164   new_logical_line (fragP->fr_file, fragP->fr_line);
9165 
9166   fragP->tc_frag_data.unreported_expansion = 0;
9167 
9168   switch (fragP->fr_subtype)
9169     {
9170     case RELAX_ALIGN_NEXT_OPCODE:
9171       /* Always convert.  */
9172       if (fragP->tc_frag_data.relax_seen)
9173 	new_stretch = relax_frag_loop_align (fragP, stretch);
9174       break;
9175 
9176     case RELAX_LOOP_END:
9177       /* Do nothing.  */
9178       break;
9179 
9180     case RELAX_LOOP_END_ADD_NOP:
9181       /* Add a NOP and switch to .fill 0.  */
9182       new_stretch = relax_frag_add_nop (fragP);
9183       frag_wane (fragP);
9184       break;
9185 
9186     case RELAX_DESIRE_ALIGN:
9187       /* Do nothing. The narrowing before this frag will either align
9188          it or not.  */
9189       break;
9190 
9191     case RELAX_LITERAL:
9192     case RELAX_LITERAL_FINAL:
9193       return 0;
9194 
9195     case RELAX_LITERAL_NR:
9196       lit_size = 4;
9197       fragP->fr_subtype = RELAX_LITERAL_FINAL;
9198       gas_assert (unreported == lit_size);
9199       memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
9200       fragP->fr_var -= lit_size;
9201       fragP->fr_fix += lit_size;
9202       new_stretch = 4;
9203       break;
9204 
9205     case RELAX_SLOTS:
9206       if (vbuf == NULL)
9207 	vbuf = xtensa_insnbuf_alloc (isa);
9208 
9209       xtensa_insnbuf_from_chars
9210 	(isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
9211       fmt = xtensa_format_decode (isa, vbuf);
9212       num_slots = xtensa_format_num_slots (isa, fmt);
9213 
9214       for (slot = 0; slot < num_slots; slot++)
9215 	{
9216 	  switch (fragP->tc_frag_data.slot_subtypes[slot])
9217 	    {
9218 	    case RELAX_NARROW:
9219 	      if (fragP->tc_frag_data.relax_seen)
9220 		new_stretch += relax_frag_for_align (fragP, stretch);
9221 	      break;
9222 
9223 	    case RELAX_IMMED:
9224 	    case RELAX_IMMED_STEP1:
9225 	    case RELAX_IMMED_STEP2:
9226 	    case RELAX_IMMED_STEP3:
9227 	      /* Place the immediate.  */
9228 	      new_stretch += relax_frag_immed
9229 		(now_seg, fragP, stretch,
9230 		 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9231 		 fmt, slot, stretched_p, FALSE);
9232 	      break;
9233 
9234 	    default:
9235 	      /* This is OK; see the note in xg_assemble_vliw_tokens.  */
9236 	      break;
9237 	    }
9238 	}
9239       break;
9240 
9241     case RELAX_LITERAL_POOL_BEGIN:
9242       if (fragP->fr_var != 0)
9243 	{
9244 	  /* We have a converted "candidate" literal pool;
9245 	     assemble a jump around it.  */
9246 	  TInsn insn;
9247 	  if (!litpool_slotbuf)
9248 	    {
9249 	      litpool_buf = xtensa_insnbuf_alloc (isa);
9250 	      litpool_slotbuf = xtensa_insnbuf_alloc (isa);
9251 	    }
9252 	  new_stretch += 3;
9253 	  fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass.  */
9254 	  fragP->tc_frag_data.is_insn = TRUE;
9255 	  tinsn_init (&insn);
9256 	  insn.insn_type = ITYPE_INSN;
9257 	  insn.opcode = xtensa_j_opcode;
9258 	  insn.ntok = 1;
9259 	  set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol,
9260 				  fragP->fr_fix);
9261 	  fmt = xg_get_single_format (xtensa_j_opcode);
9262 	  tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf);
9263 	  xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf);
9264 	  xtensa_insnbuf_to_chars (isa, litpool_buf,
9265 				   (unsigned char *)fragP->fr_literal +
9266 				   fragP->fr_fix, 3);
9267 	  fragP->fr_fix += 3;
9268 	  fragP->fr_var -= 3;
9269 	  /* Add a fix-up.  */
9270 	  fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE,
9271 		   BFD_RELOC_XTENSA_SLOT0_OP);
9272 	}
9273       break;
9274 
9275     case RELAX_LITERAL_POOL_END:
9276     case RELAX_LITERAL_POOL_CANDIDATE_BEGIN:
9277     case RELAX_MAYBE_UNREACHABLE:
9278     case RELAX_MAYBE_DESIRE_ALIGN:
9279       /* No relaxation required.  */
9280       break;
9281 
9282     case RELAX_FILL_NOP:
9283     case RELAX_UNREACHABLE:
9284       if (fragP->tc_frag_data.relax_seen)
9285 	new_stretch += relax_frag_for_align (fragP, stretch);
9286       break;
9287 
9288     case RELAX_TRAMPOLINE:
9289       if (fragP->tc_frag_data.relax_seen)
9290         {
9291 	  static fixup_cacheS fixup_cache;
9292 	  segment_info_type *seginfo = seg_info (now_seg);
9293 	  int trampaddr = fragP->fr_address + fragP->fr_fix;
9294 	  int searchaddr = trampaddr < J_RANGE ? 0 : trampaddr - J_RANGE;
9295 	  unsigned i;
9296 
9297 	  if (now_seg != fixup_cache.seg ||
9298 	      fragP == fixup_cache.first_frag ||
9299 	      fixup_cache.first_frag == NULL)
9300 	    {
9301 	      xtensa_cache_relaxable_fixups (&fixup_cache, seginfo);
9302 	      fixup_cache.seg = now_seg;
9303 	      fixup_cache.first_frag = fragP;
9304 	    }
9305 
9306           /* Scan for jumps that will not reach.  */
9307           for (i = xtensa_find_first_cached_fixup (&fixup_cache, searchaddr);
9308 	       i < fixup_cache.n_fixups; ++i)
9309 
9310             {
9311 	      fixS *fixP = fixup_cache.fixups[i].fixP;
9312 	      int target = fixup_cache.fixups[i].target;
9313 	      int addr = fixup_cache.fixups[i].addr;
9314 	      int delta = fixup_cache.fixups[i].delta + stretch;
9315 
9316 	      trampaddr = fragP->fr_address + fragP->fr_fix;
9317 
9318 	      if (addr + J_RANGE < trampaddr)
9319 		continue;
9320 	      if (addr > trampaddr + J_RANGE)
9321 		break;
9322 	      if (abs (delta) < J_RANGE)
9323 		continue;
9324 
9325 	      slot = fixP->tc_fix_data.slot;
9326 
9327               if (delta > J_RANGE  || delta < -1 * J_RANGE)
9328                 { /* Found an out-of-range jump; scan the list of trampolines for the best match.  */
9329 		  struct trampoline_seg *ts = find_trampoline_seg (now_seg);
9330 		  struct trampoline_frag *tf = ts->trampoline_list.next;
9331 		  struct trampoline_frag *prev = &ts->trampoline_list;
9332 		  int lower = (target < addr) ? target : addr;
9333 		  int upper = (target > addr) ? target : addr;
9334 		  int midpoint = lower + (upper - lower) / 2;
9335 
9336 		  if ((upper - lower) > 2 * J_RANGE)
9337 		    {
9338 		      /* One trampoline won't suffice; we need multiple jumps.
9339 			 Jump to the trampoline that's farthest, but still in
9340 			 range relative to the original "j" instruction.  */
9341 		      for ( ; tf; prev = tf, tf = tf->next )
9342 			{
9343 			  int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix;
9344 			  int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0 ;
9345 
9346 			  if (addr == lower)
9347 			    {
9348 			      /* Forward jump.  */
9349 			      if (this_addr - addr < J_RANGE)
9350 				break;
9351 			    }
9352 			  else
9353 			    {
9354 			      /* Backward jump.  */
9355 			      if (next_addr == 0 || addr - next_addr > J_RANGE)
9356 				break;
9357 			    }
9358 			}
9359 		    }
9360 		  else
9361 		    {
9362 		      struct trampoline_frag *best_tf = NULL;
9363 		      int best_delta = 0;
9364 
9365 		      for ( ; tf; prev = tf, tf = tf->next )
9366 			{
9367 			  int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix;
9368 			  int this_delta = abs (this_addr - midpoint);
9369 
9370 			  if (!best_tf || this_delta < best_delta)
9371 			    {
9372 			       best_tf = tf;
9373 			       best_delta = this_delta;
9374 			    }
9375 			}
9376 		      tf = best_tf;
9377 		    }
9378 		  if (tf->fragP == fragP)
9379 		    {
9380 		      if (abs (addr - trampaddr) < J_RANGE)
9381 			{ /* The trampoline is in range of original; fix it!  */
9382 			  fixS *newfixP;
9383 			  int offset;
9384 			  TInsn insn;
9385 			  symbolS *lsym;
9386 			  fragS *fP; /* The out-of-range jump.  */
9387 
9388 			  new_stretch += init_trampoline_frag (tf);
9389 			  offset = fragP->fr_fix; /* Where to assemble the j insn.  */
9390 			  lsym = fragP->fr_symbol;
9391 			  fP = fixP->fx_frag;
9392 			  /* Assemble a jump to the target label here.  */
9393 			  tinsn_init (&insn);
9394 			  insn.insn_type = ITYPE_INSN;
9395 			  insn.opcode = xtensa_j_opcode;
9396 			  insn.ntok = 1;
9397 			  set_expr_symbol_offset (&insn.tok[0], lsym, offset);
9398 			  fmt = xg_get_single_format (xtensa_j_opcode);
9399 			  tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf);
9400 			  xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
9401 			  xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)fragP->fr_literal + offset, 3);
9402 			  fragP->fr_fix += 3;
9403 			  fragP->fr_var -= 3;
9404 			  /* Add a fix-up for the original j insn.  */
9405 			  newfixP = fix_new (fP, fixP->fx_where, fixP->fx_size, lsym, fragP->fr_fix - 3, TRUE, fixP->fx_r_type);
9406 			  newfixP->fx_no_overflow = 1;
9407 			  newfixP->tc_fix_data.X_add_symbol = lsym;
9408 			  newfixP->tc_fix_data.X_add_number = offset;
9409 			  newfixP->tc_fix_data.slot = slot;
9410 
9411 			  xtensa_delete_cached_fixup (&fixup_cache, i);
9412 			  xtensa_add_cached_fixup (&fixup_cache, newfixP);
9413 
9414 			  /* Move the fix-up from the original j insn to this one.  */
9415 			  fixP->fx_frag = fragP;
9416 			  fixP->fx_where = fragP->fr_fix - 3;
9417 			  fixP->tc_fix_data.slot = 0;
9418 
9419 			  xtensa_add_cached_fixup (&fixup_cache, fixP);
9420 
9421 			  /* re-do current fixup */
9422 			  --i;
9423 
9424 			  /* Adjust the jump around this trampoline (if present).  */
9425 			  if (tf->fixP != NULL)
9426 			    {
9427 			      tf->fixP->fx_offset += 3;
9428 			    }
9429 			  new_stretch += 3;
9430 			  fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass.  */
9431 			  /* Do we have room for more?  */
9432 			  if (fragP->fr_var < 3)
9433 			    { /* No, convert to fill.  */
9434 			      frag_wane (fragP);
9435 			      fragP->fr_subtype = 0;
9436 			      /* Remove from the trampoline_list.  */
9437 			      prev->next = tf->next;
9438 			      if (fragP == fixup_cache.first_frag)
9439 				fixup_cache.first_frag = NULL;
9440 			      break;
9441 			    }
9442 			}
9443 		    }
9444                 }
9445             }
9446         }
9447       break;
9448 
9449     default:
9450       as_bad (_("bad relaxation state"));
9451     }
9452 
9453   /* Tell gas we need another relaxation pass.  */
9454   if (! fragP->tc_frag_data.relax_seen)
9455     {
9456       fragP->tc_frag_data.relax_seen = TRUE;
9457       *stretched_p = 1;
9458     }
9459 
9460   new_logical_line (file_name, line);
9461   return new_stretch;
9462 }
9463 
9464 
9465 static long
relax_frag_loop_align(fragS * fragP,long stretch)9466 relax_frag_loop_align (fragS *fragP, long stretch)
9467 {
9468   addressT old_address, old_next_address, old_size;
9469   addressT new_address, new_next_address, new_size;
9470   addressT growth;
9471 
9472   /* All the frags with relax_frag_for_alignment prior to this one in the
9473      section have been done, hopefully eliminating the need for a NOP here.
9474      But, this will put it in if necessary.  */
9475 
9476   /* Calculate the old address of this fragment and the next fragment.  */
9477   old_address = fragP->fr_address - stretch;
9478   old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
9479 		      fragP->tc_frag_data.text_expansion[0]);
9480   old_size = old_next_address - old_address;
9481 
9482   /* Calculate the new address of this fragment and the next fragment.  */
9483   new_address = fragP->fr_address;
9484   new_next_address =
9485     get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
9486   new_size = new_next_address - new_address;
9487 
9488   growth = new_size - old_size;
9489 
9490   /* Fix up the text_expansion field and return the new growth.  */
9491   fragP->tc_frag_data.text_expansion[0] += growth;
9492   return growth;
9493 }
9494 
9495 
9496 /* Add a NOP instruction.  */
9497 
9498 static long
relax_frag_add_nop(fragS * fragP)9499 relax_frag_add_nop (fragS *fragP)
9500 {
9501   char *nop_buf = fragP->fr_literal + fragP->fr_fix;
9502   int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
9503   assemble_nop (length, nop_buf);
9504   fragP->tc_frag_data.is_insn = TRUE;
9505 
9506   if (fragP->fr_var < length)
9507     {
9508       as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
9509       return 0;
9510     }
9511 
9512   fragP->fr_fix += length;
9513   fragP->fr_var -= length;
9514   return length;
9515 }
9516 
9517 
9518 static long future_alignment_required (fragS *, long);
9519 
9520 static long
relax_frag_for_align(fragS * fragP,long stretch)9521 relax_frag_for_align (fragS *fragP, long stretch)
9522 {
9523   /* Overview of the relaxation procedure for alignment:
9524      We can widen with NOPs or by widening instructions or by filling
9525      bytes after jump instructions.  Find the opportune places and widen
9526      them if necessary.  */
9527 
9528   long stretch_me;
9529   long diff;
9530 
9531   gas_assert (fragP->fr_subtype == RELAX_FILL_NOP
9532 	  || fragP->fr_subtype == RELAX_UNREACHABLE
9533 	  || (fragP->fr_subtype == RELAX_SLOTS
9534 	      && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
9535 
9536   stretch_me = future_alignment_required (fragP, stretch);
9537   diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
9538   if (diff == 0)
9539     return 0;
9540 
9541   if (diff < 0)
9542     {
9543       /* We expanded on a previous pass.  Can we shrink now?  */
9544       long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
9545       if (shrink <= stretch && stretch > 0)
9546 	{
9547 	  fragP->tc_frag_data.text_expansion[0] = stretch_me;
9548 	  return -shrink;
9549 	}
9550       return 0;
9551     }
9552 
9553   /* Below here, diff > 0.  */
9554   fragP->tc_frag_data.text_expansion[0] = stretch_me;
9555 
9556   return diff;
9557 }
9558 
9559 
9560 /* Return the address of the next frag that should be aligned.
9561 
9562    By "address" we mean the address it _would_ be at if there
9563    is no action taken to align it between here and the target frag.
9564    In other words, if no narrows and no fill nops are used between
9565    here and the frag to align, _even_if_ some of the frags we use
9566    to align targets have already expanded on a previous relaxation
9567    pass.
9568 
9569    Also, count each frag that may be used to help align the target.
9570 
9571    Return 0 if there are no frags left in the chain that need to be
9572    aligned.  */
9573 
9574 static addressT
find_address_of_next_align_frag(fragS ** fragPP,int * wide_nops,int * narrow_nops,int * widens,bfd_boolean * paddable)9575 find_address_of_next_align_frag (fragS **fragPP,
9576 				 int *wide_nops,
9577 				 int *narrow_nops,
9578 				 int *widens,
9579 				 bfd_boolean *paddable)
9580 {
9581   fragS *fragP = *fragPP;
9582   addressT address = fragP->fr_address;
9583 
9584   /* Do not reset the counts to 0.  */
9585 
9586   while (fragP)
9587     {
9588       /* Limit this to a small search.  */
9589       if (*widens >= (int) xtensa_fetch_width)
9590 	{
9591 	  *fragPP = fragP;
9592 	  return 0;
9593 	}
9594       address += fragP->fr_fix;
9595 
9596       if (fragP->fr_type == rs_fill)
9597 	address += fragP->fr_offset * fragP->fr_var;
9598       else if (fragP->fr_type == rs_machine_dependent)
9599 	{
9600 	  switch (fragP->fr_subtype)
9601 	    {
9602 	    case RELAX_UNREACHABLE:
9603 	      *paddable = TRUE;
9604 	      break;
9605 
9606 	    case RELAX_FILL_NOP:
9607 	      (*wide_nops)++;
9608 	      if (!fragP->tc_frag_data.is_no_density)
9609 		(*narrow_nops)++;
9610 	      break;
9611 
9612 	    case RELAX_SLOTS:
9613 	      if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9614 		{
9615 		  (*widens)++;
9616 		  break;
9617 		}
9618 	      address += total_frag_text_expansion (fragP);
9619 	      break;
9620 
9621 	    case RELAX_IMMED:
9622 	      address += fragP->tc_frag_data.text_expansion[0];
9623 	      break;
9624 
9625 	    case RELAX_ALIGN_NEXT_OPCODE:
9626 	    case RELAX_DESIRE_ALIGN:
9627 	      *fragPP = fragP;
9628 	      return address;
9629 
9630 	    case RELAX_MAYBE_UNREACHABLE:
9631 	    case RELAX_MAYBE_DESIRE_ALIGN:
9632 	      /* Do nothing.  */
9633 	      break;
9634 
9635 	    default:
9636 	      /* Just punt if we don't know the type.  */
9637 	      *fragPP = fragP;
9638 	      return 0;
9639 	    }
9640 	}
9641       else
9642 	{
9643 	  /* Just punt if we don't know the type.  */
9644 	  *fragPP = fragP;
9645 	  return 0;
9646 	}
9647       fragP = fragP->fr_next;
9648     }
9649 
9650   *fragPP = fragP;
9651   return 0;
9652 }
9653 
9654 
9655 static long bytes_to_stretch (fragS *, int, int, int, int);
9656 
9657 static long
future_alignment_required(fragS * fragP,long stretch ATTRIBUTE_UNUSED)9658 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
9659 {
9660   fragS *this_frag = fragP;
9661   long address;
9662   int num_widens = 0;
9663   int wide_nops = 0;
9664   int narrow_nops = 0;
9665   bfd_boolean paddable = FALSE;
9666   offsetT local_opt_diff;
9667   offsetT opt_diff;
9668   offsetT max_diff;
9669   int stretch_amount = 0;
9670   int local_stretch_amount;
9671   int global_stretch_amount;
9672 
9673   address = find_address_of_next_align_frag
9674     (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
9675 
9676   if (!address)
9677     {
9678       if (this_frag->tc_frag_data.is_aligning_branch)
9679 	this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
9680       else
9681 	frag_wane (this_frag);
9682     }
9683   else
9684     {
9685       local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
9686       opt_diff = local_opt_diff;
9687       gas_assert (opt_diff >= 0);
9688       gas_assert (max_diff >= opt_diff);
9689       if (max_diff == 0)
9690 	return 0;
9691 
9692       if (fragP)
9693 	fragP = fragP->fr_next;
9694 
9695       while (fragP && opt_diff < max_diff && address)
9696 	{
9697 	  /* We only use these to determine if we can exit early
9698 	     because there will be plenty of ways to align future
9699 	     align frags.  */
9700 	  int glob_widens = 0;
9701 	  int dnn = 0;
9702 	  int dw = 0;
9703 	  bfd_boolean glob_pad = 0;
9704 	  address = find_address_of_next_align_frag
9705 	    (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
9706 	  /* If there is a padable portion, then skip.  */
9707 	  if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
9708 	    address = 0;
9709 
9710 	  if (address)
9711 	    {
9712 	      offsetT next_m_diff;
9713 	      offsetT next_o_diff;
9714 
9715 	      /* Downrange frags haven't had stretch added to them yet.  */
9716 	      address += stretch;
9717 
9718 	      /* The address also includes any text expansion from this
9719 		 frag in a previous pass, but we don't want that.  */
9720 	      address -= this_frag->tc_frag_data.text_expansion[0];
9721 
9722 	      /* Assume we are going to move at least opt_diff.  In
9723 		 reality, we might not be able to, but assuming that
9724 		 we will helps catch cases where moving opt_diff pushes
9725 		 the next target from aligned to unaligned.  */
9726 	      address += opt_diff;
9727 
9728 	      next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
9729 
9730 	      /* Now cleanup for the adjustments to address.  */
9731 	      next_o_diff += opt_diff;
9732 	      next_m_diff += opt_diff;
9733 	      if (next_o_diff <= max_diff && next_o_diff > opt_diff)
9734 		opt_diff = next_o_diff;
9735 	      if (next_m_diff < max_diff)
9736 		max_diff = next_m_diff;
9737 	      fragP = fragP->fr_next;
9738 	    }
9739 	}
9740 
9741       /* If there are enough wideners in between, do it.  */
9742       if (paddable)
9743 	{
9744 	  if (this_frag->fr_subtype == RELAX_UNREACHABLE)
9745 	    {
9746 	      gas_assert (opt_diff <= (signed) xtensa_fetch_width);
9747 	      return opt_diff;
9748 	    }
9749 	  return 0;
9750 	}
9751       local_stretch_amount
9752 	= bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9753 			    num_widens, local_opt_diff);
9754       global_stretch_amount
9755 	= bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9756 			    num_widens, opt_diff);
9757       /* If the condition below is true, then the frag couldn't
9758 	 stretch the correct amount for the global case, so we just
9759 	 optimize locally.  We'll rely on the subsequent frags to get
9760 	 the correct alignment in the global case.  */
9761       if (global_stretch_amount < local_stretch_amount)
9762 	stretch_amount = local_stretch_amount;
9763       else
9764 	stretch_amount = global_stretch_amount;
9765 
9766       if (this_frag->fr_subtype == RELAX_SLOTS
9767 	  && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9768 	gas_assert (stretch_amount <= 1);
9769       else if (this_frag->fr_subtype == RELAX_FILL_NOP)
9770 	{
9771 	  if (this_frag->tc_frag_data.is_no_density)
9772 	    gas_assert (stretch_amount == 3 || stretch_amount == 0);
9773 	  else
9774 	    gas_assert (stretch_amount <= 3);
9775 	}
9776     }
9777   return stretch_amount;
9778 }
9779 
9780 
9781 /* The idea: widen everything you can to get a target or loop aligned,
9782    then start using NOPs.
9783 
9784    wide_nops   = the number of wide NOPs available for aligning
9785    narrow_nops = the number of narrow NOPs available for aligning
9786 		 (a subset of wide_nops)
9787    widens      = the number of narrow instructions that should be widened
9788 
9789 */
9790 
9791 static long
bytes_to_stretch(fragS * this_frag,int wide_nops,int narrow_nops,int num_widens,int desired_diff)9792 bytes_to_stretch (fragS *this_frag,
9793 		  int wide_nops,
9794 		  int narrow_nops,
9795 		  int num_widens,
9796 		  int desired_diff)
9797 {
9798   int nops_needed;
9799   int nop_bytes;
9800   int extra_bytes;
9801   int bytes_short = desired_diff - num_widens;
9802 
9803   gas_assert (desired_diff >= 0
9804 	      && desired_diff < (signed) xtensa_fetch_width);
9805   if (desired_diff == 0)
9806     return 0;
9807 
9808   gas_assert (wide_nops > 0 || num_widens > 0);
9809 
9810   /* Always prefer widening to NOP-filling.  */
9811   if (bytes_short < 0)
9812     {
9813       /* There are enough RELAX_NARROW frags after this one
9814 	 to align the target without widening this frag in any way.  */
9815       return 0;
9816     }
9817 
9818   if (bytes_short == 0)
9819     {
9820       /* Widen every narrow between here and the align target
9821 	 and the align target will be properly aligned.  */
9822       if (this_frag->fr_subtype == RELAX_FILL_NOP)
9823 	return 0;
9824       else
9825 	return 1;
9826     }
9827 
9828   /* From here we will need at least one NOP to get an alignment.
9829      However, we may not be able to align at all, in which case,
9830      don't widen.  */
9831   nops_needed = desired_diff / 3;
9832 
9833   /* If there aren't enough nops, don't widen.  */
9834   if (nops_needed > wide_nops)
9835     return 0;
9836 
9837   /* First try it with all wide nops.  */
9838   nop_bytes = nops_needed * 3;
9839   extra_bytes = desired_diff - nop_bytes;
9840 
9841   if (nop_bytes + num_widens >= desired_diff)
9842     {
9843       if (this_frag->fr_subtype == RELAX_FILL_NOP)
9844 	return 3;
9845       else if (num_widens == extra_bytes)
9846 	return 1;
9847       return 0;
9848     }
9849 
9850   /* Add a narrow nop.  */
9851   nops_needed++;
9852   nop_bytes += 2;
9853   extra_bytes -= 2;
9854   if (narrow_nops == 0 || nops_needed > wide_nops)
9855     return 0;
9856 
9857   if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0)
9858     {
9859       if (this_frag->fr_subtype == RELAX_FILL_NOP)
9860 	return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
9861       else if (num_widens == extra_bytes)
9862 	return 1;
9863       return 0;
9864     }
9865 
9866   /* Replace a wide nop with a narrow nop--we can get here if
9867      extra_bytes was negative in the previous conditional.  */
9868   if (narrow_nops == 1)
9869     return 0;
9870   nop_bytes--;
9871   extra_bytes++;
9872   if (nop_bytes + num_widens >= desired_diff)
9873     {
9874       if (this_frag->fr_subtype == RELAX_FILL_NOP)
9875 	return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
9876       else if (num_widens == extra_bytes)
9877 	return 1;
9878       return 0;
9879     }
9880 
9881   /* If we can't satisfy any of the above cases, then we can't align
9882      using padding or fill nops.  */
9883   return 0;
9884 }
9885 
9886 
9887 static struct trampoline_frag *
search_trampolines(TInsn * tinsn,fragS * fragP,bfd_boolean unreachable_only)9888 search_trampolines (TInsn *tinsn, fragS *fragP, bfd_boolean unreachable_only)
9889 {
9890   struct trampoline_seg *ts = find_trampoline_seg (now_seg);
9891   struct trampoline_frag *tf = (ts) ? ts->trampoline_list.next : NULL;
9892   struct trampoline_frag *best_tf = NULL;
9893   int best_delta = 0;
9894   int best_addr = 0;
9895   symbolS *sym = tinsn->tok[0].X_add_symbol;
9896   offsetT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number;
9897   offsetT addr = fragP->fr_address;
9898   offsetT lower = (addr < target) ? addr : target;
9899   offsetT upper = (addr > target) ? addr : target;
9900   int delta = upper - lower;
9901   offsetT midpoint = lower + delta / 2;
9902   int this_delta = -1;
9903   int this_addr = -1;
9904 
9905   if (delta > 2 * J_RANGE)
9906     {
9907       /* One trampoline won't do; we need multiple.
9908 	 Choose the farthest trampoline that's still in range of the original
9909 	 and let a later pass finish the job.  */
9910       for ( ; tf; tf = tf->next)
9911 	{
9912 	  int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0;
9913 
9914 	  this_addr = tf->fragP->fr_address + tf->fragP->fr_fix;
9915 	  if (lower == addr)
9916 	    {
9917 	      /* Forward jump.  */
9918 	      if (this_addr - addr < J_RANGE)
9919 		break;
9920 	    }
9921 	  else
9922 	    {
9923 	      /* Backward jump.  */
9924 	      if (next_addr == 0 || addr - next_addr > J_RANGE)
9925 		break;
9926 	    }
9927 	}
9928       if (abs (addr - this_addr) < J_RANGE)
9929 	return tf;
9930 
9931       return NULL;
9932     }
9933   for ( ; tf; tf = tf->next)
9934     {
9935       this_addr = tf->fragP->fr_address + tf->fragP->fr_fix;
9936       this_delta = abs (this_addr - midpoint);
9937       if (unreachable_only && tf->needs_jump_around)
9938 	continue;
9939       if (!best_tf || this_delta < best_delta)
9940         {
9941 	  best_tf = tf;
9942 	  best_delta = this_delta;
9943 	  best_addr = this_addr;
9944         }
9945     }
9946 
9947   if (best_tf &&
9948       best_delta < J_RANGE &&
9949       abs(best_addr - lower) < J_RANGE &&
9950       abs(best_addr - upper) < J_RANGE)
9951     return best_tf;
9952 
9953   return NULL; /* No suitable trampoline found.  */
9954 }
9955 
9956 
9957 static struct trampoline_frag *
get_best_trampoline(TInsn * tinsn,fragS * fragP)9958 get_best_trampoline (TInsn *tinsn, fragS *fragP)
9959 {
9960   struct trampoline_frag *tf = NULL;
9961 
9962   tf = search_trampolines (tinsn, fragP, TRUE); /* Try unreachable first.  */
9963 
9964   if (tf == NULL)
9965     tf = search_trampolines (tinsn, fragP, FALSE); /* Try ones needing a jump-around, too.  */
9966 
9967   return tf;
9968 }
9969 
9970 
9971 static void
check_and_update_trampolines(void)9972 check_and_update_trampolines (void)
9973 {
9974   struct trampoline_seg *ts = find_trampoline_seg (now_seg);
9975   struct trampoline_frag *tf = ts->trampoline_list.next;
9976   struct trampoline_frag *prev = &ts->trampoline_list;
9977 
9978   for ( ; tf; prev = tf, tf = tf->next)
9979     {
9980       if (tf->fragP->fr_var < 3)
9981 	{
9982 	  frag_wane (tf->fragP);
9983 	  prev->next = tf->next;
9984 	  tf->fragP = NULL;
9985 	}
9986     }
9987 }
9988 
9989 
9990 static int
init_trampoline_frag(struct trampoline_frag * trampP)9991 init_trampoline_frag (struct trampoline_frag *trampP)
9992 {
9993   fragS *fp = trampP->fragP;
9994   int growth = 0;
9995 
9996   if (fp->fr_fix == 0)
9997     {
9998       symbolS *lsym;
9999       char label[10 + 2 * sizeof(fp)];
10000       sprintf (label, ".L0_TR_%p", fp);
10001 
10002       lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp);
10003       fp->fr_symbol = lsym;
10004       if (trampP->needs_jump_around)
10005         {
10006 	  /* Add a jump around this block of jumps, in case
10007 	     control flows into this block.  */
10008 	  fixS *fixP;
10009 	  TInsn insn;
10010 	  xtensa_format fmt;
10011 	  xtensa_isa isa = xtensa_default_isa;
10012 
10013 	  fp->tc_frag_data.is_insn = 1;
10014 	  /* Assemble a jump insn.  */
10015 	  tinsn_init (&insn);
10016 	  insn.insn_type = ITYPE_INSN;
10017 	  insn.opcode = xtensa_j_opcode;
10018 	  insn.ntok = 1;
10019 	  set_expr_symbol_offset (&insn.tok[0], lsym, 3);
10020 	  fmt = xg_get_single_format (xtensa_j_opcode);
10021 	  tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf);
10022 	  xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
10023 	  xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)fp->fr_literal, 3);
10024 	  fp->fr_fix += 3;
10025 	  fp->fr_var -= 3;
10026 	  growth = 3;
10027 	  fixP = fix_new (fp, 0, 3, lsym, 3, TRUE, BFD_RELOC_XTENSA_SLOT0_OP);
10028 	  trampP->fixP = fixP;
10029         }
10030     }
10031   return growth;
10032 }
10033 
10034 
10035 static int
add_jump_to_trampoline(struct trampoline_frag * trampP,fragS * origfrag)10036 add_jump_to_trampoline (struct trampoline_frag *trampP, fragS *origfrag)
10037 {
10038   fragS *tramp = trampP->fragP;
10039   fixS *fixP;
10040   int offset = tramp->fr_fix; /* Where to assemble the j insn.  */
10041   TInsn insn;
10042   symbolS *lsym;
10043   symbolS *tsym;
10044   int toffset;
10045   xtensa_format fmt;
10046   xtensa_isa isa = xtensa_default_isa;
10047   int growth = 0;
10048 
10049   lsym = tramp->fr_symbol;
10050   /* Assemble a jump to the target label in the trampoline frag.  */
10051   tsym = origfrag->tc_frag_data.slot_symbols[0];
10052   toffset = origfrag-> tc_frag_data.slot_offsets[0];
10053   tinsn_init (&insn);
10054   insn.insn_type = ITYPE_INSN;
10055   insn.opcode = xtensa_j_opcode;
10056   insn.ntok = 1;
10057   set_expr_symbol_offset (&insn.tok[0], tsym, toffset);
10058   fmt = xg_get_single_format (xtensa_j_opcode);
10059   tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf);
10060   xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
10061   xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)tramp->fr_literal + offset, 3);
10062   tramp->fr_fix += 3;
10063   tramp->fr_var -= 3;
10064   growth = 3;
10065   /* add a fix-up for the trampoline jump.  */
10066   fixP = fix_new (tramp, tramp->fr_fix - 3, 3, tsym, toffset, TRUE, BFD_RELOC_XTENSA_SLOT0_OP);
10067   /* Modify the jump at the start of this trampoline to point past the newly-added jump.  */
10068   fixP = trampP->fixP;
10069   if (fixP)
10070     fixP->fx_offset += 3;
10071   /* Modify the original j to point here.  */
10072   origfrag->tc_frag_data.slot_symbols[0] = lsym;
10073   origfrag->tc_frag_data.slot_offsets[0] = tramp->fr_fix - 3;
10074   /* If trampoline is full, remove it from the list.  */
10075   check_and_update_trampolines ();
10076 
10077   return growth;
10078 }
10079 
10080 
10081 static long
relax_frag_immed(segT segP,fragS * fragP,long stretch,int min_steps,xtensa_format fmt,int slot,int * stretched_p,bfd_boolean estimate_only)10082 relax_frag_immed (segT segP,
10083 		  fragS *fragP,
10084 		  long stretch,
10085 		  int min_steps,
10086 		  xtensa_format fmt,
10087 		  int slot,
10088 		  int *stretched_p,
10089 		  bfd_boolean estimate_only)
10090 {
10091   TInsn tinsn;
10092   int old_size;
10093   bfd_boolean negatable_branch = FALSE;
10094   bfd_boolean branch_jmp_to_next = FALSE;
10095   bfd_boolean from_wide_insn = FALSE;
10096   xtensa_isa isa = xtensa_default_isa;
10097   IStack istack;
10098   offsetT frag_offset;
10099   int num_steps;
10100   int num_text_bytes, num_literal_bytes;
10101   int literal_diff, total_text_diff, this_text_diff;
10102 
10103   gas_assert (fragP->fr_opcode != NULL);
10104 
10105   xg_clear_vinsn (&cur_vinsn);
10106   vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
10107   if (cur_vinsn.num_slots > 1)
10108     from_wide_insn = TRUE;
10109 
10110   tinsn = cur_vinsn.slots[slot];
10111   tinsn_immed_from_frag (&tinsn, fragP, slot);
10112 
10113   if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
10114     return 0;
10115 
10116   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10117     branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
10118 
10119   negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
10120 
10121   old_size = xtensa_format_length (isa, fmt);
10122 
10123   /* Special case: replace a branch to the next instruction with a NOP.
10124      This is required to work around a hardware bug in T1040.0 and also
10125      serves as an optimization.  */
10126 
10127   if (branch_jmp_to_next
10128       && ((old_size == 2) || (old_size == 3))
10129       && !next_frag_is_loop_target (fragP))
10130     return 0;
10131 
10132   /* Here is the fun stuff: Get the immediate field from this
10133      instruction.  If it fits, we are done.  If not, find the next
10134      instruction sequence that fits.  */
10135 
10136   frag_offset = fragP->fr_opcode - fragP->fr_literal;
10137   istack_init (&istack);
10138   num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
10139 				 min_steps, stretch);
10140   gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10141 
10142   fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
10143 
10144   /* Figure out the number of bytes needed.  */
10145   num_literal_bytes = get_num_stack_literal_bytes (&istack);
10146   literal_diff
10147     = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10148   num_text_bytes = get_num_stack_text_bytes (&istack);
10149 
10150   if (from_wide_insn)
10151     {
10152       int first = 0;
10153       while (istack.insn[first].opcode == XTENSA_UNDEFINED)
10154 	first++;
10155 
10156       num_text_bytes += old_size;
10157       if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
10158 	num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
10159       else
10160 	{
10161 	  /* The first instruction in the relaxed sequence will go after
10162 	     the current wide instruction, and thus its symbolic immediates
10163 	     might not fit.  */
10164 
10165 	  istack_init (&istack);
10166 	  num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
10167 					 frag_offset + old_size,
10168 					 min_steps, stretch + old_size);
10169 	  gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10170 
10171 	  fragP->tc_frag_data.slot_subtypes[slot]
10172 	    = (int) RELAX_IMMED + num_steps;
10173 
10174 	  num_literal_bytes = get_num_stack_literal_bytes (&istack);
10175 	  literal_diff
10176 	    = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10177 
10178 	  num_text_bytes = get_num_stack_text_bytes (&istack) + old_size;
10179 	}
10180     }
10181 
10182   total_text_diff = num_text_bytes - old_size;
10183   this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
10184 
10185   /* It MUST get larger.  If not, we could get an infinite loop.  */
10186   gas_assert (num_text_bytes >= 0);
10187   gas_assert (literal_diff >= 0);
10188   gas_assert (total_text_diff >= 0);
10189 
10190   fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
10191   fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
10192   gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
10193   gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
10194 
10195   /* Find the associated expandable literal for this.  */
10196   if (literal_diff != 0)
10197     {
10198       fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot];
10199       if (lit_fragP)
10200 	{
10201 	  gas_assert (literal_diff == 4);
10202 	  lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
10203 
10204 	  /* We expect that the literal section state has NOT been
10205 	     modified yet.  */
10206 	  gas_assert (lit_fragP->fr_type == rs_machine_dependent
10207 		  && lit_fragP->fr_subtype == RELAX_LITERAL);
10208 	  lit_fragP->fr_subtype = RELAX_LITERAL_NR;
10209 
10210 	  /* We need to mark this section for another iteration
10211 	     of relaxation.  */
10212 	  (*stretched_p)++;
10213 	}
10214     }
10215 
10216   if (negatable_branch && istack.ninsn > 1)
10217     update_next_frag_state (fragP);
10218 
10219   /* If last insn is a jump, and it cannot reach its target, try to find a trampoline.  */
10220   if (istack.ninsn > 2 &&
10221       istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL &&
10222       istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN &&
10223       istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode)
10224     {
10225       TInsn *jinsn = &istack.insn[istack.ninsn - 2];
10226 
10227       if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, total_text_diff))
10228 	{
10229 	  struct trampoline_frag *tf = get_best_trampoline (jinsn, fragP);
10230 
10231 	  if (tf)
10232 	    {
10233 	      this_text_diff += init_trampoline_frag (tf);
10234 	      this_text_diff += add_jump_to_trampoline (tf, fragP);
10235 	    }
10236 	  else
10237 	    {
10238 	      /* If target symbol is undefined, assume it will reach once linked.  */
10239 	      expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0];
10240 
10241 	      if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol))
10242 		{
10243 		  as_bad_where (fragP->fr_file, fragP->fr_line,
10244 		    _("jump target out of range; no usable trampoline found"));
10245 		}
10246 	    }
10247 	}
10248     }
10249 
10250   return this_text_diff;
10251 }
10252 
10253 
10254 /* md_convert_frag Hook and Helper Functions.  */
10255 
10256 static void convert_frag_align_next_opcode (fragS *);
10257 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
10258 static void convert_frag_fill_nop (fragS *);
10259 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
10260 
10261 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec,fragS * fragp)10262 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
10263 {
10264   static xtensa_insnbuf vbuf = NULL;
10265   xtensa_isa isa = xtensa_default_isa;
10266   int slot;
10267   int num_slots;
10268   xtensa_format fmt;
10269   const char *file_name;
10270   unsigned line;
10271 
10272   file_name = as_where (&line);
10273   new_logical_line (fragp->fr_file, fragp->fr_line);
10274 
10275   switch (fragp->fr_subtype)
10276     {
10277     case RELAX_ALIGN_NEXT_OPCODE:
10278       /* Always convert.  */
10279       convert_frag_align_next_opcode (fragp);
10280       break;
10281 
10282     case RELAX_DESIRE_ALIGN:
10283       /* Do nothing.  If not aligned already, too bad.  */
10284       break;
10285 
10286     case RELAX_LITERAL:
10287     case RELAX_LITERAL_FINAL:
10288       break;
10289 
10290     case RELAX_SLOTS:
10291       if (vbuf == NULL)
10292 	vbuf = xtensa_insnbuf_alloc (isa);
10293 
10294       xtensa_insnbuf_from_chars
10295 	(isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
10296       fmt = xtensa_format_decode (isa, vbuf);
10297       num_slots = xtensa_format_num_slots (isa, fmt);
10298 
10299       for (slot = 0; slot < num_slots; slot++)
10300 	{
10301 	  switch (fragp->tc_frag_data.slot_subtypes[slot])
10302 	    {
10303 	    case RELAX_NARROW:
10304 	      convert_frag_narrow (sec, fragp, fmt, slot);
10305 	      break;
10306 
10307 	    case RELAX_IMMED:
10308 	    case RELAX_IMMED_STEP1:
10309 	    case RELAX_IMMED_STEP2:
10310 	    case RELAX_IMMED_STEP3:
10311 	      /* Place the immediate.  */
10312 	      convert_frag_immed
10313 		(sec, fragp,
10314 		 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
10315 		 fmt, slot);
10316 	      break;
10317 
10318 	    default:
10319 	      /* This is OK because some slots could have
10320 		 relaxations and others have none.  */
10321 	      break;
10322 	    }
10323 	}
10324       break;
10325 
10326     case RELAX_UNREACHABLE:
10327       memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
10328       fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
10329       fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
10330       frag_wane (fragp);
10331       break;
10332 
10333     case RELAX_MAYBE_UNREACHABLE:
10334     case RELAX_MAYBE_DESIRE_ALIGN:
10335       frag_wane (fragp);
10336       break;
10337 
10338     case RELAX_FILL_NOP:
10339       convert_frag_fill_nop (fragp);
10340       break;
10341 
10342     case RELAX_LITERAL_NR:
10343       if (use_literal_section)
10344 	{
10345 	  /* This should have been handled during relaxation.  When
10346 	     relaxing a code segment, literals sometimes need to be
10347 	     added to the corresponding literal segment.  If that
10348 	     literal segment has already been relaxed, then we end up
10349 	     in this situation.  Marking the literal segments as data
10350 	     would make this happen less often (since GAS always relaxes
10351 	     code before data), but we could still get into trouble if
10352 	     there are instructions in a segment that is not marked as
10353 	     containing code.  Until we can implement a better solution,
10354 	     cheat and adjust the addresses of all the following frags.
10355 	     This could break subsequent alignments, but the linker's
10356 	     literal coalescing will do that anyway.  */
10357 
10358 	  fragS *f;
10359 	  fragp->fr_subtype = RELAX_LITERAL_FINAL;
10360 	  gas_assert (fragp->tc_frag_data.unreported_expansion == 4);
10361 	  memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
10362 	  fragp->fr_var -= 4;
10363 	  fragp->fr_fix += 4;
10364 	  for (f = fragp->fr_next; f; f = f->fr_next)
10365 	    f->fr_address += 4;
10366 	}
10367       else
10368 	as_bad (_("invalid relaxation fragment result"));
10369       break;
10370 
10371     case RELAX_TRAMPOLINE:
10372       break;
10373     }
10374 
10375   fragp->fr_var = 0;
10376   new_logical_line (file_name, line);
10377 }
10378 
10379 
10380 static void
convert_frag_align_next_opcode(fragS * fragp)10381 convert_frag_align_next_opcode (fragS *fragp)
10382 {
10383   char *nop_buf;		/* Location for Writing.  */
10384   bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
10385   addressT aligned_address;
10386   offsetT fill_size;
10387   int nop, nop_count;
10388 
10389   aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
10390 					      fragp->fr_fix);
10391   fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
10392   nop_count = get_text_align_nop_count (fill_size, use_no_density);
10393   nop_buf = fragp->fr_literal + fragp->fr_fix;
10394 
10395   for (nop = 0; nop < nop_count; nop++)
10396     {
10397       int nop_size;
10398       nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
10399 
10400       assemble_nop (nop_size, nop_buf);
10401       nop_buf += nop_size;
10402     }
10403 
10404   fragp->fr_fix += fill_size;
10405   fragp->fr_var -= fill_size;
10406 }
10407 
10408 
10409 static void
convert_frag_narrow(segT segP,fragS * fragP,xtensa_format fmt,int slot)10410 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
10411 {
10412   TInsn tinsn, single_target;
10413   int size, old_size, diff;
10414   offsetT frag_offset;
10415 
10416   gas_assert (slot == 0);
10417   tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
10418 
10419   if (fragP->tc_frag_data.is_aligning_branch == 1)
10420     {
10421       gas_assert (fragP->tc_frag_data.text_expansion[0] == 1
10422 	      || fragP->tc_frag_data.text_expansion[0] == 0);
10423       convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
10424 			  fmt, slot);
10425       return;
10426     }
10427 
10428   if (fragP->tc_frag_data.text_expansion[0] == 0)
10429     {
10430       /* No conversion.  */
10431       fragP->fr_var = 0;
10432       return;
10433     }
10434 
10435   gas_assert (fragP->fr_opcode != NULL);
10436 
10437   /* Frags in this relaxation state should only contain
10438      single instruction bundles.  */
10439   tinsn_immed_from_frag (&tinsn, fragP, 0);
10440 
10441   /* Just convert it to a wide form....  */
10442   size = 0;
10443   old_size = xg_get_single_size (tinsn.opcode);
10444 
10445   tinsn_init (&single_target);
10446   frag_offset = fragP->fr_opcode - fragP->fr_literal;
10447 
10448   if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
10449     {
10450       as_bad (_("unable to widen instruction"));
10451       return;
10452     }
10453 
10454   size = xg_get_single_size (single_target.opcode);
10455   xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
10456 		       frag_offset, TRUE);
10457 
10458   diff = size - old_size;
10459   gas_assert (diff >= 0);
10460   gas_assert (diff <= fragP->fr_var);
10461   fragP->fr_var -= diff;
10462   fragP->fr_fix += diff;
10463 
10464   /* clean it up */
10465   fragP->fr_var = 0;
10466 }
10467 
10468 
10469 static void
convert_frag_fill_nop(fragS * fragP)10470 convert_frag_fill_nop (fragS *fragP)
10471 {
10472   char *loc = &fragP->fr_literal[fragP->fr_fix];
10473   int size = fragP->tc_frag_data.text_expansion[0];
10474   gas_assert ((unsigned) size == (fragP->fr_next->fr_address
10475 			      - fragP->fr_address - fragP->fr_fix));
10476   if (size == 0)
10477     {
10478       /* No conversion.  */
10479       fragP->fr_var = 0;
10480       return;
10481     }
10482   assemble_nop (size, loc);
10483   fragP->tc_frag_data.is_insn = TRUE;
10484   fragP->fr_var -= size;
10485   fragP->fr_fix += size;
10486   frag_wane (fragP);
10487 }
10488 
10489 
10490 static fixS *fix_new_exp_in_seg
10491   (segT, subsegT, fragS *, int, int, expressionS *, int,
10492    bfd_reloc_code_real_type);
10493 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
10494 
10495 static void
convert_frag_immed(segT segP,fragS * fragP,int min_steps,xtensa_format fmt,int slot)10496 convert_frag_immed (segT segP,
10497 		    fragS *fragP,
10498 		    int min_steps,
10499 		    xtensa_format fmt,
10500 		    int slot)
10501 {
10502   char *immed_instr = fragP->fr_opcode;
10503   TInsn orig_tinsn;
10504   bfd_boolean expanded = FALSE;
10505   bfd_boolean branch_jmp_to_next = FALSE;
10506   char *fr_opcode = fragP->fr_opcode;
10507   xtensa_isa isa = xtensa_default_isa;
10508   bfd_boolean from_wide_insn = FALSE;
10509   int bytes;
10510   bfd_boolean is_loop;
10511 
10512   gas_assert (fr_opcode != NULL);
10513 
10514   xg_clear_vinsn (&cur_vinsn);
10515 
10516   vinsn_from_chars (&cur_vinsn, fr_opcode);
10517   if (cur_vinsn.num_slots > 1)
10518     from_wide_insn = TRUE;
10519 
10520   orig_tinsn = cur_vinsn.slots[slot];
10521   tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
10522 
10523   is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
10524 
10525   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10526     branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
10527 
10528   if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
10529     {
10530       /* Conversion just inserts a NOP and marks the fix as completed.  */
10531       bytes = xtensa_format_length (isa, fmt);
10532       if (bytes >= 4)
10533 	{
10534 	  cur_vinsn.slots[slot].opcode =
10535 	    xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
10536 	  cur_vinsn.slots[slot].ntok = 0;
10537 	}
10538       else
10539 	{
10540 	  bytes += fragP->tc_frag_data.text_expansion[0];
10541 	  gas_assert (bytes == 2 || bytes == 3);
10542 	  build_nop (&cur_vinsn.slots[0], bytes);
10543 	  fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
10544 	}
10545       vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
10546       xtensa_insnbuf_to_chars
10547 	(isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
10548       fragP->fr_var = 0;
10549     }
10550   else
10551     {
10552       /* Here is the fun stuff:  Get the immediate field from this
10553 	 instruction.  If it fits, we're done.  If not, find the next
10554 	 instruction sequence that fits.  */
10555 
10556       IStack istack;
10557       int i;
10558       symbolS *lit_sym = NULL;
10559       int total_size = 0;
10560       int target_offset = 0;
10561       int old_size;
10562       int diff;
10563       symbolS *gen_label = NULL;
10564       offsetT frag_offset;
10565       bfd_boolean first = TRUE;
10566 
10567       /* It does not fit.  Find something that does and
10568          convert immediately.  */
10569       frag_offset = fr_opcode - fragP->fr_literal;
10570       istack_init (&istack);
10571       xg_assembly_relax (&istack, &orig_tinsn,
10572 			 segP, fragP, frag_offset, min_steps, 0);
10573 
10574       old_size = xtensa_format_length (isa, fmt);
10575 
10576       /* Assemble this right inline.  */
10577 
10578       /* First, create the mapping from a label name to the REAL label.  */
10579       target_offset = 0;
10580       for (i = 0; i < istack.ninsn; i++)
10581 	{
10582 	  TInsn *tinsn = &istack.insn[i];
10583 	  fragS *lit_frag;
10584 
10585 	  switch (tinsn->insn_type)
10586 	    {
10587 	    case ITYPE_LITERAL:
10588 	      if (lit_sym != NULL)
10589 		as_bad (_("multiple literals in expansion"));
10590 	      /* First find the appropriate space in the literal pool.  */
10591 	      lit_frag = fragP->tc_frag_data.literal_frags[slot];
10592 	      if (lit_frag == NULL)
10593 		as_bad (_("no registered fragment for literal"));
10594 	      if (tinsn->ntok != 1)
10595 		as_bad (_("number of literal tokens != 1"));
10596 
10597 	      /* Set the literal symbol and add a fixup.  */
10598 	      lit_sym = lit_frag->fr_symbol;
10599 	      break;
10600 
10601 	    case ITYPE_LABEL:
10602 	      if (align_targets && !is_loop)
10603 		{
10604 		  fragS *unreach = fragP->fr_next;
10605 		  while (!(unreach->fr_type == rs_machine_dependent
10606 			   && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10607 			       || unreach->fr_subtype == RELAX_UNREACHABLE)))
10608 		    {
10609 		      unreach = unreach->fr_next;
10610 		    }
10611 
10612 		  gas_assert (unreach->fr_type == rs_machine_dependent
10613 			  && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10614 			      || unreach->fr_subtype == RELAX_UNREACHABLE));
10615 
10616 		  target_offset += unreach->tc_frag_data.text_expansion[0];
10617 		}
10618 	      gas_assert (gen_label == NULL);
10619 	      gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
10620 				      fr_opcode - fragP->fr_literal
10621 				      + target_offset, fragP);
10622 	      break;
10623 
10624 	    case ITYPE_INSN:
10625 	      if (first && from_wide_insn)
10626 		{
10627 		  target_offset += xtensa_format_length (isa, fmt);
10628 		  first = FALSE;
10629 		  if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10630 		    target_offset += xg_get_single_size (tinsn->opcode);
10631 		}
10632 	      else
10633 		target_offset += xg_get_single_size (tinsn->opcode);
10634 	      break;
10635 	    }
10636 	}
10637 
10638       total_size = 0;
10639       first = TRUE;
10640       for (i = 0; i < istack.ninsn; i++)
10641 	{
10642 	  TInsn *tinsn = &istack.insn[i];
10643 	  fragS *lit_frag;
10644 	  int size;
10645 	  segT target_seg;
10646 	  bfd_reloc_code_real_type reloc_type;
10647 
10648 	  switch (tinsn->insn_type)
10649 	    {
10650 	    case ITYPE_LITERAL:
10651 	      lit_frag = fragP->tc_frag_data.literal_frags[slot];
10652 	      /* Already checked.  */
10653 	      gas_assert (lit_frag != NULL);
10654 	      gas_assert (lit_sym != NULL);
10655 	      gas_assert (tinsn->ntok == 1);
10656 	      /* Add a fixup.  */
10657 	      target_seg = S_GET_SEGMENT (lit_sym);
10658 	      gas_assert (target_seg);
10659 	      reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE);
10660 	      fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
10661 				  &tinsn->tok[0], FALSE, reloc_type);
10662 	      break;
10663 
10664 	    case ITYPE_LABEL:
10665 	      break;
10666 
10667 	    case ITYPE_INSN:
10668 	      xg_resolve_labels (tinsn, gen_label);
10669 	      xg_resolve_literals (tinsn, lit_sym);
10670 	      if (from_wide_insn && first)
10671 		{
10672 		  first = FALSE;
10673 		  if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10674 		    {
10675 		      cur_vinsn.slots[slot] = *tinsn;
10676 		    }
10677 		  else
10678 		    {
10679 		      cur_vinsn.slots[slot].opcode =
10680 			xtensa_format_slot_nop_opcode (isa, fmt, slot);
10681 		      cur_vinsn.slots[slot].ntok = 0;
10682 		    }
10683 		  vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
10684 		  xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
10685 					   (unsigned char *) immed_instr, 0);
10686 		  fragP->tc_frag_data.is_insn = TRUE;
10687 		  size = xtensa_format_length (isa, fmt);
10688 		  if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10689 		    {
10690 		      xg_emit_insn_to_buf
10691 			(tinsn, immed_instr + size, fragP,
10692 			 immed_instr - fragP->fr_literal + size, TRUE);
10693 		      size += xg_get_single_size (tinsn->opcode);
10694 		    }
10695 		}
10696 	      else
10697 		{
10698 		  size = xg_get_single_size (tinsn->opcode);
10699 		  xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
10700 				       immed_instr - fragP->fr_literal, TRUE);
10701 		}
10702 	      immed_instr += size;
10703 	      total_size += size;
10704 	      break;
10705 	    }
10706 	}
10707 
10708       diff = total_size - old_size;
10709       gas_assert (diff >= 0);
10710       if (diff != 0)
10711 	expanded = TRUE;
10712       gas_assert (diff <= fragP->fr_var);
10713       fragP->fr_var -= diff;
10714       fragP->fr_fix += diff;
10715     }
10716 
10717   /* Check for undefined immediates in LOOP instructions.  */
10718   if (is_loop)
10719     {
10720       symbolS *sym;
10721       sym = orig_tinsn.tok[1].X_add_symbol;
10722       if (sym != NULL && !S_IS_DEFINED (sym))
10723 	{
10724 	  as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10725 	  return;
10726 	}
10727       sym = orig_tinsn.tok[1].X_op_symbol;
10728       if (sym != NULL && !S_IS_DEFINED (sym))
10729 	{
10730 	  as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10731 	  return;
10732 	}
10733     }
10734 
10735   if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
10736     convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
10737 
10738   if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
10739     {
10740       /* Add an expansion note on the expanded instruction.  */
10741       fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
10742 			  &orig_tinsn.tok[0], TRUE,
10743 			  BFD_RELOC_XTENSA_ASM_EXPAND);
10744     }
10745 }
10746 
10747 
10748 /* Add a new fix expression into the desired segment.  We have to
10749    switch to that segment to do this.  */
10750 
10751 static fixS *
fix_new_exp_in_seg(segT new_seg,subsegT new_subseg,fragS * frag,int where,int size,expressionS * exp,int pcrel,bfd_reloc_code_real_type r_type)10752 fix_new_exp_in_seg (segT new_seg,
10753 		    subsegT new_subseg,
10754 		    fragS *frag,
10755 		    int where,
10756 		    int size,
10757 		    expressionS *exp,
10758 		    int pcrel,
10759 		    bfd_reloc_code_real_type r_type)
10760 {
10761   fixS *new_fix;
10762   segT seg = now_seg;
10763   subsegT subseg = now_subseg;
10764 
10765   gas_assert (new_seg != 0);
10766   subseg_set (new_seg, new_subseg);
10767 
10768   new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
10769   subseg_set (seg, subseg);
10770   return new_fix;
10771 }
10772 
10773 
10774 /* Relax a loop instruction so that it can span loop >256 bytes.
10775 
10776                   loop    as, .L1
10777           .L0:
10778                   rsr     as, LEND
10779                   wsr     as, LBEG
10780                   addi    as, as, lo8 (label-.L1)
10781                   addmi   as, as, mid8 (label-.L1)
10782                   wsr     as, LEND
10783                   isync
10784                   rsr     as, LCOUNT
10785                   addi    as, as, 1
10786           .L1:
10787                   <<body>>
10788           label:
10789 */
10790 
10791 static void
convert_frag_immed_finish_loop(segT segP,fragS * fragP,TInsn * tinsn)10792 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
10793 {
10794   TInsn loop_insn;
10795   TInsn addi_insn;
10796   TInsn addmi_insn;
10797   unsigned long target;
10798   static xtensa_insnbuf insnbuf = NULL;
10799   unsigned int loop_length, loop_length_hi, loop_length_lo;
10800   xtensa_isa isa = xtensa_default_isa;
10801   addressT loop_offset;
10802   addressT addi_offset = 9;
10803   addressT addmi_offset = 12;
10804   fragS *next_fragP;
10805   int target_count;
10806 
10807   if (!insnbuf)
10808     insnbuf = xtensa_insnbuf_alloc (isa);
10809 
10810   /* Get the loop offset.  */
10811   loop_offset = get_expanded_loop_offset (tinsn->opcode);
10812 
10813   /* Validate that there really is a LOOP at the loop_offset.  Because
10814      loops are not bundleable, we can assume that the instruction will be
10815      in slot 0.  */
10816   tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
10817   tinsn_immed_from_frag (&loop_insn, fragP, 0);
10818 
10819   gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
10820   addi_offset += loop_offset;
10821   addmi_offset += loop_offset;
10822 
10823   gas_assert (tinsn->ntok == 2);
10824   if (tinsn->tok[1].X_op == O_constant)
10825     target = tinsn->tok[1].X_add_number;
10826   else if (tinsn->tok[1].X_op == O_symbol)
10827     {
10828       /* Find the fragment.  */
10829       symbolS *sym = tinsn->tok[1].X_add_symbol;
10830       gas_assert (S_GET_SEGMENT (sym) == segP
10831 	      || S_GET_SEGMENT (sym) == absolute_section);
10832       target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
10833     }
10834   else
10835     {
10836       as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
10837       target = 0;
10838     }
10839 
10840   loop_length = target - (fragP->fr_address + fragP->fr_fix);
10841   loop_length_hi = loop_length & ~0x0ff;
10842   loop_length_lo = loop_length & 0x0ff;
10843   if (loop_length_lo >= 128)
10844     {
10845       loop_length_lo -= 256;
10846       loop_length_hi += 256;
10847     }
10848 
10849   /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10850      32512.  If the loop is larger than that, then we just fail.  */
10851   if (loop_length_hi > 32512)
10852     as_bad_where (fragP->fr_file, fragP->fr_line,
10853 		  _("loop too long for LOOP instruction"));
10854 
10855   tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
10856   gas_assert (addi_insn.opcode == xtensa_addi_opcode);
10857 
10858   tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
10859   gas_assert (addmi_insn.opcode == xtensa_addmi_opcode);
10860 
10861   set_expr_const (&addi_insn.tok[2], loop_length_lo);
10862   tinsn_to_insnbuf (&addi_insn, insnbuf);
10863 
10864   fragP->tc_frag_data.is_insn = TRUE;
10865   xtensa_insnbuf_to_chars
10866     (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0);
10867 
10868   set_expr_const (&addmi_insn.tok[2], loop_length_hi);
10869   tinsn_to_insnbuf (&addmi_insn, insnbuf);
10870   xtensa_insnbuf_to_chars
10871     (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0);
10872 
10873   /* Walk through all of the frags from here to the loop end
10874      and mark them as no_transform to keep them from being modified
10875      by the linker.  If we ever have a relocation for the
10876      addi/addmi of the difference of two symbols we can remove this.  */
10877 
10878   target_count = 0;
10879   for (next_fragP = fragP; next_fragP != NULL;
10880        next_fragP = next_fragP->fr_next)
10881     {
10882       next_fragP->tc_frag_data.is_no_transform = TRUE;
10883       if (next_fragP->tc_frag_data.is_loop_target)
10884 	target_count++;
10885       if (target_count == 2)
10886 	break;
10887     }
10888 }
10889 
10890 
10891 /* A map that keeps information on a per-subsegment basis.  This is
10892    maintained during initial assembly, but is invalid once the
10893    subsegments are smashed together.  I.E., it cannot be used during
10894    the relaxation.  */
10895 
10896 typedef struct subseg_map_struct
10897 {
10898   /* the key */
10899   segT seg;
10900   subsegT subseg;
10901 
10902   /* the data */
10903   unsigned flags;
10904   float total_freq;	/* fall-through + branch target frequency */
10905   float target_freq;	/* branch target frequency alone */
10906 
10907   struct subseg_map_struct *next;
10908 } subseg_map;
10909 
10910 
10911 static subseg_map *sseg_map = NULL;
10912 
10913 static subseg_map *
get_subseg_info(segT seg,subsegT subseg)10914 get_subseg_info (segT seg, subsegT subseg)
10915 {
10916   subseg_map *subseg_e;
10917 
10918   for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
10919     {
10920       if (seg == subseg_e->seg && subseg == subseg_e->subseg)
10921 	break;
10922     }
10923   return subseg_e;
10924 }
10925 
10926 
10927 static subseg_map *
add_subseg_info(segT seg,subsegT subseg)10928 add_subseg_info (segT seg, subsegT subseg)
10929 {
10930   subseg_map *subseg_e = XNEW (subseg_map);
10931   memset (subseg_e, 0, sizeof (subseg_map));
10932   subseg_e->seg = seg;
10933   subseg_e->subseg = subseg;
10934   subseg_e->flags = 0;
10935   /* Start off considering every branch target very important.  */
10936   subseg_e->target_freq = 1.0;
10937   subseg_e->total_freq = 1.0;
10938   subseg_e->next = sseg_map;
10939   sseg_map = subseg_e;
10940   return subseg_e;
10941 }
10942 
10943 
10944 static unsigned
get_last_insn_flags(segT seg,subsegT subseg)10945 get_last_insn_flags (segT seg, subsegT subseg)
10946 {
10947   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10948   if (subseg_e)
10949     return subseg_e->flags;
10950   return 0;
10951 }
10952 
10953 
10954 static void
set_last_insn_flags(segT seg,subsegT subseg,unsigned fl,bfd_boolean val)10955 set_last_insn_flags (segT seg,
10956 		     subsegT subseg,
10957 		     unsigned fl,
10958 		     bfd_boolean val)
10959 {
10960   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10961   if (! subseg_e)
10962     subseg_e = add_subseg_info (seg, subseg);
10963   if (val)
10964     subseg_e->flags |= fl;
10965   else
10966     subseg_e->flags &= ~fl;
10967 }
10968 
10969 
10970 static float
get_subseg_total_freq(segT seg,subsegT subseg)10971 get_subseg_total_freq (segT seg, subsegT subseg)
10972 {
10973   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10974   if (subseg_e)
10975     return subseg_e->total_freq;
10976   return 1.0;
10977 }
10978 
10979 
10980 static float
get_subseg_target_freq(segT seg,subsegT subseg)10981 get_subseg_target_freq (segT seg, subsegT subseg)
10982 {
10983   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10984   if (subseg_e)
10985     return subseg_e->target_freq;
10986   return 1.0;
10987 }
10988 
10989 
10990 static void
set_subseg_freq(segT seg,subsegT subseg,float total_f,float target_f)10991 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
10992 {
10993   subseg_map *subseg_e = get_subseg_info (seg, subseg);
10994   if (! subseg_e)
10995     subseg_e = add_subseg_info (seg, subseg);
10996   subseg_e->total_freq = total_f;
10997   subseg_e->target_freq = target_f;
10998 }
10999 
11000 
11001 /* Segment Lists and emit_state Stuff.  */
11002 
11003 static void
xtensa_move_seg_list_to_beginning(seg_list * head)11004 xtensa_move_seg_list_to_beginning (seg_list *head)
11005 {
11006   head = head->next;
11007   while (head)
11008     {
11009       segT literal_section = head->seg;
11010 
11011       /* Move the literal section to the front of the section list.  */
11012       gas_assert (literal_section);
11013       if (literal_section != stdoutput->sections)
11014 	{
11015 	  bfd_section_list_remove (stdoutput, literal_section);
11016 	  bfd_section_list_prepend (stdoutput, literal_section);
11017 	}
11018       head = head->next;
11019     }
11020 }
11021 
11022 
11023 static void mark_literal_frags (seg_list *);
11024 
11025 static void
xtensa_move_literals(void)11026 xtensa_move_literals (void)
11027 {
11028   seg_list *segment;
11029   frchainS *frchain_from, *frchain_to;
11030   fragS *search_frag, *next_frag, *literal_pool, *insert_after;
11031   fragS **frag_splice;
11032   emit_state state;
11033   segT dest_seg;
11034   fixS *fix, *next_fix, **fix_splice;
11035   sym_list *lit;
11036   struct litpool_seg *lps;
11037   const char *init_name = INIT_SECTION_NAME;
11038   const char *fini_name = FINI_SECTION_NAME;
11039   int init_name_len = strlen(init_name);
11040   int fini_name_len = strlen(fini_name);
11041 
11042   mark_literal_frags (literal_head->next);
11043 
11044   if (use_literal_section)
11045     return;
11046 
11047   /* Assign addresses (rough estimates) to the potential literal pool locations
11048      and create new ones if the gaps are too large.  */
11049 
11050   for (lps = litpool_seg_list.next; lps; lps = lps->next)
11051     {
11052       frchainS *frchP = seg_info (lps->seg)->frchainP;
11053       struct litpool_frag *lpf = lps->frag_list.next;
11054       addressT addr = 0;
11055 
11056       for ( ; frchP; frchP = frchP->frch_next)
11057 	{
11058 	  fragS *fragP;
11059 	  for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
11060 	    {
11061 	      if (lpf && fragP == lpf->fragP)
11062 		{
11063 		  gas_assert(fragP->fr_type == rs_machine_dependent &&
11064 			     (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN ||
11065 			      fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN));
11066 		  /* Found a litpool location.  */
11067 		  lpf->addr = addr;
11068 		  lpf = lpf->next;
11069 		}
11070 	      if (fragP->fr_type == rs_machine_dependent &&
11071 		  fragP->fr_subtype == RELAX_SLOTS)
11072 		{
11073 		  int slot;
11074 		  for (slot = 0; slot < MAX_SLOTS; slot++)
11075 		    {
11076 		      if (fragP->tc_frag_data.literal_frags[slot])
11077 			{
11078 			  /* L32R; point its literal to the nearest litpool
11079 			     preferring non-"candidate" positions to avoid
11080 			     the jump-around.  */
11081 			  fragS *litfrag = fragP->tc_frag_data.literal_frags[slot];
11082 			  struct litpool_frag *lp = lpf->prev;
11083 			  if (!lp->fragP)
11084 			    {
11085 			      break;
11086 			    }
11087 			  while (lp->fragP->fr_subtype ==
11088 				 RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11089 			    {
11090 			      lp = lp->prev;
11091 			      if (lp->fragP == NULL)
11092 				{
11093 				  /* End of list; have to bite the bullet.
11094 				     Take the nearest.  */
11095 				  lp = lpf->prev;
11096 				  break;
11097 				}
11098 			      /* Does it (conservatively) reach?  */
11099 			      if (addr - lp->addr <= 128 * 1024)
11100 				{
11101 				  if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN)
11102 				    {
11103 				      /* Found a good one.  */
11104 				      break;
11105 				    }
11106 				  else if (lp->prev->fragP &&
11107 					   addr - lp->prev->addr > 128 * 1024)
11108 				    {
11109 				      /* This is still a "candidate" but the next one
11110 				         will be too far away, so revert to the nearest
11111 					 one, convert it and add the jump around.  */
11112 				      fragS *poolbeg;
11113 				      fragS *poolend;
11114 				      symbolS *lsym;
11115 				      char label[10 + 2 * sizeof (fragS *)];
11116 				      lp = lpf->prev;
11117 				      poolbeg = lp->fragP;
11118 				      lp->priority = 1;
11119 				      poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN;
11120 				      poolend = poolbeg->fr_next;
11121 				      gas_assert (poolend->fr_type == rs_machine_dependent &&
11122 						  poolend->fr_subtype == RELAX_LITERAL_POOL_END);
11123 				      /* Create a local symbol pointing to the
11124 				         end of the pool.  */
11125 				      sprintf (label, ".L0_LT_%p", poolbeg);
11126 				      lsym = (symbolS *)local_symbol_make (label, lps->seg,
11127 									   0, poolend);
11128 				      poolbeg->fr_symbol = lsym;
11129 				      /* Rest is done in xtensa_relax_frag.  */
11130 				    }
11131 				}
11132 			    }
11133 			  if (! litfrag->tc_frag_data.literal_frag)
11134 			    {
11135 			      /* Take earliest use of this literal to avoid
11136 				 forward refs.  */
11137 			      litfrag->tc_frag_data.literal_frag = lp->fragP;
11138 			    }
11139 			}
11140 		    }
11141 		}
11142 	      addr += fragP->fr_fix;
11143 	      if (fragP->fr_type == rs_fill)
11144 		addr += fragP->fr_offset;
11145 	    }
11146 	}
11147     }
11148 
11149   for (segment = literal_head->next; segment; segment = segment->next)
11150     {
11151       const char *seg_name = segment_name (segment->seg);
11152 
11153       /* Keep the literals for .init and .fini in separate sections.  */
11154       if ((!memcmp (seg_name, init_name, init_name_len) &&
11155 	   !strcmp (seg_name + init_name_len, ".literal")) ||
11156 	  (!memcmp (seg_name, fini_name, fini_name_len) &&
11157 	   !strcmp (seg_name + fini_name_len, ".literal")))
11158 	continue;
11159 
11160       frchain_from = seg_info (segment->seg)->frchainP;
11161       search_frag = frchain_from->frch_root;
11162       literal_pool = NULL;
11163       frchain_to = NULL;
11164       frag_splice = &(frchain_from->frch_root);
11165 
11166       while (search_frag && !search_frag->tc_frag_data.literal_frag)
11167 	{
11168 	  gas_assert (search_frag->fr_fix == 0
11169 		  || search_frag->fr_type == rs_align);
11170 	  search_frag = search_frag->fr_next;
11171 	}
11172 
11173       if (!search_frag)
11174 	{
11175 	  search_frag = frchain_from->frch_root;
11176 	  as_bad_where (search_frag->fr_file, search_frag->fr_line,
11177 			_("literal pool location required for text-section-literals; specify with .literal_position"));
11178 	  continue;
11179 	}
11180 
11181       gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype
11182 	      == RELAX_LITERAL_POOL_BEGIN);
11183       xtensa_switch_section_emit_state (&state, segment->seg, 0);
11184 
11185       /* Make sure that all the frags in this series are closed, and
11186 	 that there is at least one left over of zero-size.  This
11187 	 prevents us from making a segment with an frchain without any
11188 	 frags in it.  */
11189       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11190       xtensa_set_frag_assembly_state (frag_now);
11191       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11192       xtensa_set_frag_assembly_state (frag_now);
11193 
11194       while (search_frag != frag_now)
11195 	{
11196 	  next_frag = search_frag->fr_next;
11197 	  if (search_frag->tc_frag_data.literal_frag)
11198 	    {
11199 	      literal_pool = search_frag->tc_frag_data.literal_frag;
11200 	      gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
11201 	      frchain_to = literal_pool->tc_frag_data.lit_frchain;
11202 	      gas_assert (frchain_to);
11203 	    }
11204 
11205 	  if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0)
11206 	    {
11207 	      /* Skip empty fill frags.  */
11208 	      *frag_splice = next_frag;
11209 	      search_frag = next_frag;
11210 	      continue;
11211 	    }
11212 
11213 	  if (search_frag->fr_type == rs_align)
11214 	    {
11215 	      /* Skip alignment frags, because the pool as a whole will be
11216 	         aligned if used, and we don't want to force alignment if the
11217 		 pool is unused.  */
11218 	      *frag_splice = next_frag;
11219 	      search_frag = next_frag;
11220 	      continue;
11221 	    }
11222 
11223 	  /* First, move the frag out of the literal section and
11224 	     to the appropriate place.  */
11225 
11226 	  /* Insert an aligmnent frag at start of pool.  */
11227 	  if (literal_pool->fr_next->fr_type == rs_machine_dependent &&
11228 	      literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END)
11229 	    {
11230 	      segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg;
11231 	      emit_state prev_state;
11232 	      fragS *prev_frag;
11233 	      fragS *align_frag;
11234 	      xtensa_switch_section_emit_state (&prev_state, pool_seg, 0);
11235 	      prev_frag = frag_now;
11236 	      frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11237 	      align_frag = frag_now;
11238 	      frag_align (2, 0, 0);
11239 	      /* Splice it into the right place.  */
11240 	      prev_frag->fr_next = align_frag->fr_next;
11241 	      align_frag->fr_next = literal_pool->fr_next;
11242 	      literal_pool->fr_next = align_frag;
11243 	      /* Insert after this one.  */
11244 	      literal_pool->tc_frag_data.literal_frag = align_frag;
11245 	      xtensa_restore_emit_state (&prev_state);
11246 	    }
11247 	  insert_after = literal_pool->tc_frag_data.literal_frag;
11248 	  dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
11249 	  /* Skip align frag.  */
11250 	  if (insert_after->fr_next->fr_type == rs_align)
11251 	    {
11252 	      insert_after = insert_after->fr_next;
11253 	    }
11254 
11255 	  *frag_splice = next_frag;
11256 	  search_frag->fr_next = insert_after->fr_next;
11257 	  insert_after->fr_next = search_frag;
11258 	  search_frag->tc_frag_data.lit_seg = dest_seg;
11259 	  literal_pool->tc_frag_data.literal_frag = search_frag;
11260 
11261 	  /* Now move any fixups associated with this frag to the
11262 	     right section.  */
11263 	  fix = frchain_from->fix_root;
11264 	  fix_splice = &(frchain_from->fix_root);
11265 	  while (fix)
11266 	    {
11267 	      next_fix = fix->fx_next;
11268 	      if (fix->fx_frag == search_frag)
11269 		{
11270 		  *fix_splice = next_fix;
11271 		  fix->fx_next = frchain_to->fix_root;
11272 		  frchain_to->fix_root = fix;
11273 		  if (frchain_to->fix_tail == NULL)
11274 		    frchain_to->fix_tail = fix;
11275 		}
11276 	      else
11277 		fix_splice = &(fix->fx_next);
11278 	      fix = next_fix;
11279 	    }
11280 	  search_frag = next_frag;
11281 	}
11282 
11283       if (frchain_from->fix_root != NULL)
11284 	{
11285 	  frchain_from = seg_info (segment->seg)->frchainP;
11286 	  as_warn (_("fixes not all moved from %s"), segment->seg->name);
11287 
11288 	  gas_assert (frchain_from->fix_root == NULL);
11289 	}
11290       frchain_from->fix_tail = NULL;
11291       xtensa_restore_emit_state (&state);
11292     }
11293 
11294   /* Now fix up the SEGMENT value for all the literal symbols.  */
11295   for (lit = literal_syms; lit; lit = lit->next)
11296     {
11297       symbolS *lit_sym = lit->sym;
11298       segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
11299       if (dseg)
11300 	S_SET_SEGMENT (lit_sym, dseg);
11301     }
11302 }
11303 
11304 
11305 /* Walk over all the frags for segments in a list and mark them as
11306    containing literals.  As clunky as this is, we can't rely on frag_var
11307    and frag_variant to get called in all situations.  */
11308 
11309 static void
mark_literal_frags(seg_list * segment)11310 mark_literal_frags (seg_list *segment)
11311 {
11312   frchainS *frchain_from;
11313   fragS *search_frag;
11314 
11315   while (segment)
11316     {
11317       frchain_from = seg_info (segment->seg)->frchainP;
11318       search_frag = frchain_from->frch_root;
11319       while (search_frag)
11320 	{
11321 	  search_frag->tc_frag_data.is_literal = TRUE;
11322 	  search_frag = search_frag->fr_next;
11323 	}
11324       segment = segment->next;
11325     }
11326 }
11327 
11328 
11329 static void
xtensa_reorder_seg_list(seg_list * head,segT after)11330 xtensa_reorder_seg_list (seg_list *head, segT after)
11331 {
11332   /* Move all of the sections in the section list to come
11333      after "after" in the gnu segment list.  */
11334 
11335   head = head->next;
11336   while (head)
11337     {
11338       segT literal_section = head->seg;
11339 
11340       /* Move the literal section after "after".  */
11341       gas_assert (literal_section);
11342       if (literal_section != after)
11343 	{
11344 	  bfd_section_list_remove (stdoutput, literal_section);
11345 	  bfd_section_list_insert_after (stdoutput, after, literal_section);
11346 	}
11347 
11348       head = head->next;
11349     }
11350 }
11351 
11352 
11353 /* Push all the literal segments to the end of the gnu list.  */
11354 
11355 static void
xtensa_reorder_segments(void)11356 xtensa_reorder_segments (void)
11357 {
11358   segT sec;
11359   segT last_sec = 0;
11360   int old_count = 0;
11361   int new_count = 0;
11362 
11363   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11364     {
11365       last_sec = sec;
11366       old_count++;
11367     }
11368 
11369   /* Now that we have the last section, push all the literal
11370      sections to the end.  */
11371   xtensa_reorder_seg_list (literal_head, last_sec);
11372 
11373   /* Now perform the final error check.  */
11374   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11375     new_count++;
11376   gas_assert (new_count == old_count);
11377 }
11378 
11379 
11380 /* Change the emit state (seg, subseg, and frag related stuff) to the
11381    correct location.  Return a emit_state which can be passed to
11382    xtensa_restore_emit_state to return to current fragment.  */
11383 
11384 static void
xtensa_switch_to_literal_fragment(emit_state * result)11385 xtensa_switch_to_literal_fragment (emit_state *result)
11386 {
11387   if (directive_state[directive_absolute_literals])
11388     {
11389       segT lit4_seg = cache_literal_section (TRUE);
11390       xtensa_switch_section_emit_state (result, lit4_seg, 0);
11391     }
11392   else
11393     xtensa_switch_to_non_abs_literal_fragment (result);
11394 
11395   /* Do a 4-byte align here.  */
11396   frag_align (2, 0, 0);
11397   record_alignment (now_seg, 2);
11398 }
11399 
11400 
11401 static void
xtensa_switch_to_non_abs_literal_fragment(emit_state * result)11402 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
11403 {
11404   static bfd_boolean recursive = FALSE;
11405   fragS *pool_location = get_literal_pool_location (now_seg);
11406   segT lit_seg;
11407   bfd_boolean is_init =
11408     (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
11409   bfd_boolean is_fini =
11410     (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
11411 
11412   if (pool_location == NULL
11413       && !use_literal_section
11414       && !recursive
11415       && !is_init && ! is_fini)
11416     {
11417       if (!auto_litpools)
11418 	{
11419 	  as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11420 	}
11421 
11422       /* When we mark a literal pool location, we want to put a frag in
11423 	 the literal pool that points to it.  But to do that, we want to
11424 	 switch_to_literal_fragment.  But literal sections don't have
11425 	 literal pools, so their location is always null, so we would
11426 	 recurse forever.  This is kind of hacky, but it works.  */
11427 
11428       recursive = TRUE;
11429       xtensa_mark_literal_pool_location ();
11430       recursive = FALSE;
11431     }
11432 
11433   lit_seg = cache_literal_section (FALSE);
11434   xtensa_switch_section_emit_state (result, lit_seg, 0);
11435 
11436   if (!use_literal_section
11437       && !is_init && !is_fini
11438       && get_literal_pool_location (now_seg) != pool_location)
11439     {
11440       /* Close whatever frag is there.  */
11441       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11442       xtensa_set_frag_assembly_state (frag_now);
11443       frag_now->tc_frag_data.literal_frag = pool_location;
11444       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11445       xtensa_set_frag_assembly_state (frag_now);
11446     }
11447 }
11448 
11449 
11450 /* Call this function before emitting data into the literal section.
11451    This is a helper function for xtensa_switch_to_literal_fragment.
11452    This is similar to a .section new_now_seg subseg. */
11453 
11454 static void
xtensa_switch_section_emit_state(emit_state * state,segT new_now_seg,subsegT new_now_subseg)11455 xtensa_switch_section_emit_state (emit_state *state,
11456 				  segT new_now_seg,
11457 				  subsegT new_now_subseg)
11458 {
11459   state->name = now_seg->name;
11460   state->now_seg = now_seg;
11461   state->now_subseg = now_subseg;
11462   state->generating_literals = generating_literals;
11463   generating_literals++;
11464   subseg_set (new_now_seg, new_now_subseg);
11465 }
11466 
11467 
11468 /* Use to restore the emitting into the normal place.  */
11469 
11470 static void
xtensa_restore_emit_state(emit_state * state)11471 xtensa_restore_emit_state (emit_state *state)
11472 {
11473   generating_literals = state->generating_literals;
11474   subseg_set (state->now_seg, state->now_subseg);
11475 }
11476 
11477 
11478 /* Predicate function used to look up a section in a particular group.  */
11479 
11480 static bfd_boolean
match_section_group(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * inf)11481 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
11482 {
11483   const char *gname = inf;
11484   const char *group_name = elf_group_name (sec);
11485 
11486   return (group_name == gname
11487 	  || (group_name != NULL
11488 	      && gname != NULL
11489 	      && strcmp (group_name, gname) == 0));
11490 }
11491 
11492 
11493 /* Get the literal section to be used for the current text section.
11494    The result may be cached in the default_lit_sections structure.  */
11495 
11496 static segT
cache_literal_section(bfd_boolean use_abs_literals)11497 cache_literal_section (bfd_boolean use_abs_literals)
11498 {
11499   const char *text_name, *group_name = 0;
11500   const char *base_name, *suffix;
11501   char *name;
11502   segT *pcached;
11503   segT seg, current_section;
11504   int current_subsec;
11505   bfd_boolean linkonce = FALSE;
11506 
11507   /* Save the current section/subsection.  */
11508   current_section = now_seg;
11509   current_subsec = now_subseg;
11510 
11511   /* Clear the cached values if they are no longer valid.  */
11512   if (now_seg != default_lit_sections.current_text_seg)
11513     {
11514       default_lit_sections.current_text_seg = now_seg;
11515       default_lit_sections.lit_seg = NULL;
11516       default_lit_sections.lit4_seg = NULL;
11517     }
11518 
11519   /* Check if the literal section is already cached.  */
11520   if (use_abs_literals)
11521     pcached = &default_lit_sections.lit4_seg;
11522   else
11523     pcached = &default_lit_sections.lit_seg;
11524 
11525   if (*pcached)
11526     return *pcached;
11527 
11528   text_name = default_lit_sections.lit_prefix;
11529   if (! text_name || ! *text_name)
11530     {
11531       text_name = segment_name (current_section);
11532       group_name = elf_group_name (current_section);
11533       linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
11534     }
11535 
11536   base_name = use_abs_literals ? ".lit4" : ".literal";
11537   if (group_name)
11538     {
11539       name = concat (base_name, ".", group_name, (char *) NULL);
11540     }
11541   else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
11542     {
11543       suffix = strchr (text_name + linkonce_len, '.');
11544 
11545       name = concat (".gnu.linkonce", base_name, suffix ? suffix : "",
11546 		     (char *) NULL);
11547       linkonce = TRUE;
11548     }
11549   else
11550     {
11551       /* If the section name begins or ends with ".text", then replace
11552 	 that portion instead of appending an additional suffix.  */
11553       size_t len = strlen (text_name);
11554       if (len >= 5
11555 	  && (strcmp (text_name + len - 5, ".text") == 0
11556 	      || strncmp (text_name, ".text", 5) == 0))
11557 	len -= 5;
11558 
11559       name = XNEWVEC (char, len + strlen (base_name) + 1);
11560       if (strncmp (text_name, ".text", 5) == 0)
11561 	{
11562 	  strcpy (name, base_name);
11563 	  strcat (name, text_name + 5);
11564 	}
11565       else
11566 	{
11567 	  strcpy (name, text_name);
11568 	  strcpy (name + len, base_name);
11569 	}
11570     }
11571 
11572   /* Canonicalize section names to allow renaming literal sections.
11573      The group name, if any, came from the current text section and
11574      has already been canonicalized.  */
11575   name = tc_canonicalize_symbol_name (name);
11576 
11577   seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
11578 				    (void *) group_name);
11579   if (! seg)
11580     {
11581       flagword flags;
11582 
11583       seg = subseg_force_new (name, 0);
11584 
11585       if (! use_abs_literals)
11586 	{
11587 	  /* Add the newly created literal segment to the list.  */
11588 	  seg_list *n = XNEW (seg_list);
11589 	  n->seg = seg;
11590 	  n->next = literal_head->next;
11591 	  literal_head->next = n;
11592 	}
11593 
11594       flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
11595 	       | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
11596 	       | (use_abs_literals ? SEC_DATA : SEC_CODE));
11597 
11598       elf_group_name (seg) = group_name;
11599 
11600       bfd_set_section_flags (stdoutput, seg, flags);
11601       bfd_set_section_alignment (stdoutput, seg, 2);
11602     }
11603 
11604   *pcached = seg;
11605   subseg_set (current_section, current_subsec);
11606   return seg;
11607 }
11608 
11609 
11610 /* Property Tables Stuff.  */
11611 
11612 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11613 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11614 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11615 
11616 typedef bfd_boolean (*frag_predicate) (const fragS *);
11617 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
11618 
11619 static bfd_boolean get_frag_is_literal (const fragS *);
11620 static void xtensa_create_property_segments
11621   (frag_predicate, frag_predicate, const char *, xt_section_type);
11622 static void xtensa_create_xproperty_segments
11623   (frag_flags_fn, const char *, xt_section_type);
11624 static bfd_boolean exclude_section_from_property_tables (segT);
11625 static bfd_boolean section_has_property (segT, frag_predicate);
11626 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
11627 static void add_xt_block_frags
11628   (segT, xtensa_block_info **, frag_predicate, frag_predicate);
11629 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
11630 static void xtensa_frag_flags_init (frag_flags *);
11631 static void get_frag_property_flags (const fragS *, frag_flags *);
11632 static flagword frag_flags_to_number (const frag_flags *);
11633 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn);
11634 
11635 /* Set up property tables after relaxation.  */
11636 
11637 void
xtensa_post_relax_hook(void)11638 xtensa_post_relax_hook (void)
11639 {
11640   xtensa_move_seg_list_to_beginning (literal_head);
11641 
11642   xtensa_find_unmarked_state_frags ();
11643   xtensa_mark_frags_for_org ();
11644   xtensa_mark_difference_of_two_symbols ();
11645 
11646   xtensa_create_property_segments (get_frag_is_literal,
11647 				   NULL,
11648 				   XTENSA_LIT_SEC_NAME,
11649 				   xt_literal_sec);
11650   xtensa_create_xproperty_segments (get_frag_property_flags,
11651 				    XTENSA_PROP_SEC_NAME,
11652 				    xt_prop_sec);
11653 
11654   if (warn_unaligned_branch_targets)
11655     bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
11656   bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
11657 }
11658 
11659 
11660 /* This function is only meaningful after xtensa_move_literals.  */
11661 
11662 static bfd_boolean
get_frag_is_literal(const fragS * fragP)11663 get_frag_is_literal (const fragS *fragP)
11664 {
11665   gas_assert (fragP != NULL);
11666   return fragP->tc_frag_data.is_literal;
11667 }
11668 
11669 
11670 static void
xtensa_create_property_segments(frag_predicate property_function,frag_predicate end_property_function,const char * section_name_base,xt_section_type sec_type)11671 xtensa_create_property_segments (frag_predicate property_function,
11672 				 frag_predicate end_property_function,
11673 				 const char *section_name_base,
11674 				 xt_section_type sec_type)
11675 {
11676   segT *seclist;
11677 
11678   /* Walk over all of the current segments.
11679      Walk over each fragment
11680      For each non-empty fragment,
11681      Build a property record (append where possible).  */
11682 
11683   for (seclist = &stdoutput->sections;
11684        seclist && *seclist;
11685        seclist = &(*seclist)->next)
11686     {
11687       segT sec = *seclist;
11688 
11689       if (exclude_section_from_property_tables (sec))
11690 	continue;
11691 
11692       if (section_has_property (sec, property_function))
11693 	{
11694 	  segment_info_type *xt_seg_info;
11695 	  xtensa_block_info **xt_blocks;
11696 	  segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11697 
11698 	  prop_sec->output_section = prop_sec;
11699 	  subseg_set (prop_sec, 0);
11700 	  xt_seg_info = seg_info (prop_sec);
11701 	  xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11702 
11703 	  /* Walk over all of the frchains here and add new sections.  */
11704 	  add_xt_block_frags (sec, xt_blocks, property_function,
11705 			      end_property_function);
11706 	}
11707     }
11708 
11709   /* Now we fill them out....  */
11710 
11711   for (seclist = &stdoutput->sections;
11712        seclist && *seclist;
11713        seclist = &(*seclist)->next)
11714     {
11715       segment_info_type *seginfo;
11716       xtensa_block_info *block;
11717       segT sec = *seclist;
11718 
11719       seginfo = seg_info (sec);
11720       block = seginfo->tc_segment_info_data.blocks[sec_type];
11721 
11722       if (block)
11723 	{
11724 	  xtensa_block_info *cur_block;
11725 	  int num_recs = 0;
11726 	  bfd_size_type rec_size;
11727 
11728 	  for (cur_block = block; cur_block; cur_block = cur_block->next)
11729 	    num_recs++;
11730 
11731 	  rec_size = num_recs * 8;
11732 	  bfd_set_section_size (stdoutput, sec, rec_size);
11733 
11734 	  if (num_recs)
11735 	    {
11736 	      char *frag_data;
11737 	      int i;
11738 
11739 	      subseg_set (sec, 0);
11740 	      frag_data = frag_more (rec_size);
11741 	      cur_block = block;
11742 	      for (i = 0; i < num_recs; i++)
11743 		{
11744 		  fixS *fix;
11745 
11746 		  /* Write the fixup.  */
11747 		  gas_assert (cur_block);
11748 		  fix = fix_new (frag_now, i * 8, 4,
11749 				 section_symbol (cur_block->sec),
11750 				 cur_block->offset,
11751 				 FALSE, BFD_RELOC_32);
11752 		  fix->fx_file = "<internal>";
11753 		  fix->fx_line = 0;
11754 
11755 		  /* Write the length.  */
11756 		  md_number_to_chars (&frag_data[4 + i * 8],
11757 				      cur_block->size, 4);
11758 		  cur_block = cur_block->next;
11759 		}
11760 	      frag_wane (frag_now);
11761 	      frag_new (0);
11762 	      frag_wane (frag_now);
11763 	    }
11764 	}
11765     }
11766 }
11767 
11768 
11769 static void
xtensa_create_xproperty_segments(frag_flags_fn flag_fn,const char * section_name_base,xt_section_type sec_type)11770 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
11771 				  const char *section_name_base,
11772 				  xt_section_type sec_type)
11773 {
11774   segT *seclist;
11775 
11776   /* Walk over all of the current segments.
11777      Walk over each fragment.
11778      For each fragment that has instructions,
11779      build an instruction record (append where possible).  */
11780 
11781   for (seclist = &stdoutput->sections;
11782        seclist && *seclist;
11783        seclist = &(*seclist)->next)
11784     {
11785       segT sec = *seclist;
11786 
11787       if (exclude_section_from_property_tables (sec))
11788 	continue;
11789 
11790       if (section_has_xproperty (sec, flag_fn))
11791 	{
11792 	  segment_info_type *xt_seg_info;
11793 	  xtensa_block_info **xt_blocks;
11794 	  segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11795 
11796 	  prop_sec->output_section = prop_sec;
11797 	  subseg_set (prop_sec, 0);
11798 	  xt_seg_info = seg_info (prop_sec);
11799 	  xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11800 
11801 	  /* Walk over all of the frchains here and add new sections.  */
11802 	  add_xt_prop_frags (sec, xt_blocks, flag_fn);
11803 	}
11804     }
11805 
11806   /* Now we fill them out....  */
11807 
11808   for (seclist = &stdoutput->sections;
11809        seclist && *seclist;
11810        seclist = &(*seclist)->next)
11811     {
11812       segment_info_type *seginfo;
11813       xtensa_block_info *block;
11814       segT sec = *seclist;
11815 
11816       seginfo = seg_info (sec);
11817       block = seginfo->tc_segment_info_data.blocks[sec_type];
11818 
11819       if (block)
11820 	{
11821 	  xtensa_block_info *cur_block;
11822 	  int num_recs = 0;
11823 	  bfd_size_type rec_size;
11824 
11825 	  for (cur_block = block; cur_block; cur_block = cur_block->next)
11826 	    num_recs++;
11827 
11828 	  rec_size = num_recs * (8 + 4);
11829 	  bfd_set_section_size (stdoutput, sec, rec_size);
11830 	  /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11831 
11832 	  if (num_recs)
11833 	    {
11834 	      char *frag_data;
11835 	      int i;
11836 
11837 	      subseg_set (sec, 0);
11838 	      frag_data = frag_more (rec_size);
11839 	      cur_block = block;
11840 	      for (i = 0; i < num_recs; i++)
11841 		{
11842 		  fixS *fix;
11843 
11844 		  /* Write the fixup.  */
11845 		  gas_assert (cur_block);
11846 		  fix = fix_new (frag_now, i * 12, 4,
11847 				 section_symbol (cur_block->sec),
11848 				 cur_block->offset,
11849 				 FALSE, BFD_RELOC_32);
11850 		  fix->fx_file = "<internal>";
11851 		  fix->fx_line = 0;
11852 
11853 		  /* Write the length.  */
11854 		  md_number_to_chars (&frag_data[4 + i * 12],
11855 				      cur_block->size, 4);
11856 		  md_number_to_chars (&frag_data[8 + i * 12],
11857 				      frag_flags_to_number (&cur_block->flags),
11858 				      sizeof (flagword));
11859 		  cur_block = cur_block->next;
11860 		}
11861 	      frag_wane (frag_now);
11862 	      frag_new (0);
11863 	      frag_wane (frag_now);
11864 	    }
11865 	}
11866     }
11867 }
11868 
11869 
11870 static bfd_boolean
exclude_section_from_property_tables(segT sec)11871 exclude_section_from_property_tables (segT sec)
11872 {
11873   flagword flags = bfd_get_section_flags (stdoutput, sec);
11874 
11875   /* Sections that don't contribute to the memory footprint are excluded.  */
11876   if ((flags & SEC_DEBUGGING)
11877       || !(flags & SEC_ALLOC)
11878       || (flags & SEC_MERGE))
11879     return TRUE;
11880 
11881   /* Linker cie and fde optimizations mess up property entries for
11882      eh_frame sections, but there is nothing inside them relevant to
11883      property tables anyway.  */
11884   if (strcmp (sec->name, ".eh_frame") == 0)
11885     return TRUE;
11886 
11887   return FALSE;
11888 }
11889 
11890 
11891 static bfd_boolean
section_has_property(segT sec,frag_predicate property_function)11892 section_has_property (segT sec, frag_predicate property_function)
11893 {
11894   segment_info_type *seginfo = seg_info (sec);
11895   fragS *fragP;
11896 
11897   if (seginfo && seginfo->frchainP)
11898     {
11899       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
11900 	{
11901 	  if (property_function (fragP)
11902 	      && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
11903 	    return TRUE;
11904 	}
11905     }
11906   return FALSE;
11907 }
11908 
11909 
11910 static bfd_boolean
section_has_xproperty(segT sec,frag_flags_fn property_function)11911 section_has_xproperty (segT sec, frag_flags_fn property_function)
11912 {
11913   segment_info_type *seginfo = seg_info (sec);
11914   fragS *fragP;
11915 
11916   if (seginfo && seginfo->frchainP)
11917     {
11918       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
11919 	{
11920 	  frag_flags prop_flags;
11921 	  property_function (fragP, &prop_flags);
11922 	  if (!xtensa_frag_flags_is_empty (&prop_flags))
11923 	    return TRUE;
11924 	}
11925     }
11926   return FALSE;
11927 }
11928 
11929 
11930 /* Two types of block sections exist right now: literal and insns.  */
11931 
11932 static void
add_xt_block_frags(segT sec,xtensa_block_info ** xt_block,frag_predicate property_function,frag_predicate end_property_function)11933 add_xt_block_frags (segT sec,
11934 		    xtensa_block_info **xt_block,
11935 		    frag_predicate property_function,
11936 		    frag_predicate end_property_function)
11937 {
11938   fragS *fragP;
11939 
11940   /* Build it if needed.  */
11941   while (*xt_block != NULL)
11942     xt_block = &(*xt_block)->next;
11943   /* We are either at NULL at the beginning or at the end.  */
11944 
11945   /* Walk through the frags.  */
11946   if (seg_info (sec)->frchainP)
11947     {
11948       for (fragP = seg_info (sec)->frchainP->frch_root;
11949 	   fragP;
11950 	   fragP = fragP->fr_next)
11951 	{
11952 	  if (property_function (fragP)
11953 	      && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
11954 	    {
11955 	      if (*xt_block != NULL)
11956 		{
11957 		  if ((*xt_block)->offset + (*xt_block)->size
11958 		      == fragP->fr_address)
11959 		    (*xt_block)->size += fragP->fr_fix;
11960 		  else
11961 		    xt_block = &((*xt_block)->next);
11962 		}
11963 	      if (*xt_block == NULL)
11964 		{
11965 		  xtensa_block_info *new_block = XNEW (xtensa_block_info);
11966 		  new_block->sec = sec;
11967 		  new_block->offset = fragP->fr_address;
11968 		  new_block->size = fragP->fr_fix;
11969 		  new_block->next = NULL;
11970 		  xtensa_frag_flags_init (&new_block->flags);
11971 		  *xt_block = new_block;
11972 		}
11973 	      if (end_property_function
11974 		  && end_property_function (fragP))
11975 		{
11976 		  xt_block = &((*xt_block)->next);
11977 		}
11978 	    }
11979 	}
11980     }
11981 }
11982 
11983 
11984 /* Break the encapsulation of add_xt_prop_frags here.  */
11985 
11986 static bfd_boolean
xtensa_frag_flags_is_empty(const frag_flags * prop_flags)11987 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
11988 {
11989   if (prop_flags->is_literal
11990       || prop_flags->is_insn
11991       || prop_flags->is_data
11992       || prop_flags->is_unreachable)
11993     return FALSE;
11994   return TRUE;
11995 }
11996 
11997 
11998 static void
xtensa_frag_flags_init(frag_flags * prop_flags)11999 xtensa_frag_flags_init (frag_flags *prop_flags)
12000 {
12001   memset (prop_flags, 0, sizeof (frag_flags));
12002 }
12003 
12004 
12005 static void
get_frag_property_flags(const fragS * fragP,frag_flags * prop_flags)12006 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
12007 {
12008   xtensa_frag_flags_init (prop_flags);
12009   if (fragP->tc_frag_data.is_literal)
12010     prop_flags->is_literal = TRUE;
12011   if (fragP->tc_frag_data.is_specific_opcode
12012       || fragP->tc_frag_data.is_no_transform)
12013     {
12014       prop_flags->is_no_transform = TRUE;
12015       if (xtensa_frag_flags_is_empty (prop_flags))
12016 	prop_flags->is_data = TRUE;
12017     }
12018   if (fragP->tc_frag_data.is_unreachable)
12019     prop_flags->is_unreachable = TRUE;
12020   else if (fragP->tc_frag_data.is_insn)
12021     {
12022       prop_flags->is_insn = TRUE;
12023       if (fragP->tc_frag_data.is_loop_target)
12024 	prop_flags->insn.is_loop_target = TRUE;
12025       if (fragP->tc_frag_data.is_branch_target)
12026 	prop_flags->insn.is_branch_target = TRUE;
12027       if (fragP->tc_frag_data.is_no_density)
12028 	prop_flags->insn.is_no_density = TRUE;
12029       if (fragP->tc_frag_data.use_absolute_literals)
12030 	prop_flags->insn.is_abslit = TRUE;
12031     }
12032   if (fragP->tc_frag_data.is_align)
12033     {
12034       prop_flags->is_align = TRUE;
12035       prop_flags->alignment = fragP->tc_frag_data.alignment;
12036       if (xtensa_frag_flags_is_empty (prop_flags))
12037 	prop_flags->is_data = TRUE;
12038     }
12039 }
12040 
12041 
12042 static flagword
frag_flags_to_number(const frag_flags * prop_flags)12043 frag_flags_to_number (const frag_flags *prop_flags)
12044 {
12045   flagword num = 0;
12046   if (prop_flags->is_literal)
12047     num |= XTENSA_PROP_LITERAL;
12048   if (prop_flags->is_insn)
12049     num |= XTENSA_PROP_INSN;
12050   if (prop_flags->is_data)
12051     num |= XTENSA_PROP_DATA;
12052   if (prop_flags->is_unreachable)
12053     num |= XTENSA_PROP_UNREACHABLE;
12054   if (prop_flags->insn.is_loop_target)
12055     num |= XTENSA_PROP_INSN_LOOP_TARGET;
12056   if (prop_flags->insn.is_branch_target)
12057     {
12058       num |= XTENSA_PROP_INSN_BRANCH_TARGET;
12059       num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
12060     }
12061 
12062   if (prop_flags->insn.is_no_density)
12063     num |= XTENSA_PROP_INSN_NO_DENSITY;
12064   if (prop_flags->is_no_transform)
12065     num |= XTENSA_PROP_NO_TRANSFORM;
12066   if (prop_flags->insn.is_no_reorder)
12067     num |= XTENSA_PROP_INSN_NO_REORDER;
12068   if (prop_flags->insn.is_abslit)
12069     num |= XTENSA_PROP_INSN_ABSLIT;
12070 
12071   if (prop_flags->is_align)
12072     {
12073       num |= XTENSA_PROP_ALIGN;
12074       num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
12075     }
12076 
12077   return num;
12078 }
12079 
12080 
12081 static bfd_boolean
xtensa_frag_flags_combinable(const frag_flags * prop_flags_1,const frag_flags * prop_flags_2)12082 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
12083 			      const frag_flags *prop_flags_2)
12084 {
12085   /* Cannot combine with an end marker.  */
12086 
12087   if (prop_flags_1->is_literal != prop_flags_2->is_literal)
12088     return FALSE;
12089   if (prop_flags_1->is_insn != prop_flags_2->is_insn)
12090     return FALSE;
12091   if (prop_flags_1->is_data != prop_flags_2->is_data)
12092     return FALSE;
12093 
12094   if (prop_flags_1->is_insn)
12095     {
12096       /* Properties of the beginning of the frag.  */
12097       if (prop_flags_2->insn.is_loop_target)
12098 	return FALSE;
12099       if (prop_flags_2->insn.is_branch_target)
12100 	return FALSE;
12101       if (prop_flags_1->insn.is_no_density !=
12102 	  prop_flags_2->insn.is_no_density)
12103 	return FALSE;
12104       if (prop_flags_1->is_no_transform !=
12105 	  prop_flags_2->is_no_transform)
12106 	return FALSE;
12107       if (prop_flags_1->insn.is_no_reorder !=
12108 	  prop_flags_2->insn.is_no_reorder)
12109 	return FALSE;
12110       if (prop_flags_1->insn.is_abslit !=
12111 	  prop_flags_2->insn.is_abslit)
12112 	return FALSE;
12113     }
12114 
12115   if (prop_flags_1->is_align)
12116     return FALSE;
12117 
12118   return TRUE;
12119 }
12120 
12121 
12122 static bfd_vma
xt_block_aligned_size(const xtensa_block_info * xt_block)12123 xt_block_aligned_size (const xtensa_block_info *xt_block)
12124 {
12125   bfd_vma end_addr;
12126   unsigned align_bits;
12127 
12128   if (!xt_block->flags.is_align)
12129     return xt_block->size;
12130 
12131   end_addr = xt_block->offset + xt_block->size;
12132   align_bits = xt_block->flags.alignment;
12133   end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
12134   return end_addr - xt_block->offset;
12135 }
12136 
12137 
12138 static bfd_boolean
xtensa_xt_block_combine(xtensa_block_info * xt_block,const xtensa_block_info * xt_block_2)12139 xtensa_xt_block_combine (xtensa_block_info *xt_block,
12140 			 const xtensa_block_info *xt_block_2)
12141 {
12142   if (xt_block->sec != xt_block_2->sec)
12143     return FALSE;
12144   if (xt_block->offset + xt_block_aligned_size (xt_block)
12145       != xt_block_2->offset)
12146     return FALSE;
12147 
12148   if (xt_block_2->size == 0
12149       && (!xt_block_2->flags.is_unreachable
12150 	  || xt_block->flags.is_unreachable))
12151     {
12152       if (xt_block_2->flags.is_align
12153 	  && xt_block->flags.is_align)
12154 	{
12155 	  /* Nothing needed.  */
12156 	  if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
12157 	    return TRUE;
12158 	}
12159       else
12160 	{
12161 	  if (xt_block_2->flags.is_align)
12162 	    {
12163 	      /* Push alignment to previous entry.  */
12164 	      xt_block->flags.is_align = xt_block_2->flags.is_align;
12165 	      xt_block->flags.alignment = xt_block_2->flags.alignment;
12166 	    }
12167 	  return TRUE;
12168 	}
12169     }
12170   if (!xtensa_frag_flags_combinable (&xt_block->flags,
12171 				     &xt_block_2->flags))
12172     return FALSE;
12173 
12174   xt_block->size += xt_block_2->size;
12175 
12176   if (xt_block_2->flags.is_align)
12177     {
12178       xt_block->flags.is_align = TRUE;
12179       xt_block->flags.alignment = xt_block_2->flags.alignment;
12180     }
12181 
12182   return TRUE;
12183 }
12184 
12185 
12186 static void
add_xt_prop_frags(segT sec,xtensa_block_info ** xt_block,frag_flags_fn property_function)12187 add_xt_prop_frags (segT sec,
12188 		   xtensa_block_info **xt_block,
12189 		   frag_flags_fn property_function)
12190 {
12191   fragS *fragP;
12192 
12193   /* Build it if needed.  */
12194   while (*xt_block != NULL)
12195     {
12196       xt_block = &(*xt_block)->next;
12197     }
12198   /* We are either at NULL at the beginning or at the end.  */
12199 
12200   /* Walk through the frags.  */
12201   if (seg_info (sec)->frchainP)
12202     {
12203       for (fragP = seg_info (sec)->frchainP->frch_root; fragP;
12204 	   fragP = fragP->fr_next)
12205 	{
12206 	  xtensa_block_info tmp_block;
12207 	  tmp_block.sec = sec;
12208 	  tmp_block.offset = fragP->fr_address;
12209 	  tmp_block.size = fragP->fr_fix;
12210 	  tmp_block.next = NULL;
12211 	  property_function (fragP, &tmp_block.flags);
12212 
12213 	  if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
12214 	    /* && fragP->fr_fix != 0) */
12215 	    {
12216 	      if ((*xt_block) == NULL
12217 		  || !xtensa_xt_block_combine (*xt_block, &tmp_block))
12218 		{
12219 		  xtensa_block_info *new_block;
12220 		  if ((*xt_block) != NULL)
12221 		    xt_block = &(*xt_block)->next;
12222 		  new_block = XNEW (xtensa_block_info);
12223 		  *new_block = tmp_block;
12224 		  *xt_block = new_block;
12225 		}
12226 	    }
12227 	}
12228     }
12229 }
12230 
12231 
12232 /* op_placement_info_table */
12233 
12234 /* op_placement_info makes it easier to determine which
12235    ops can go in which slots.  */
12236 
12237 static void
init_op_placement_info_table(void)12238 init_op_placement_info_table (void)
12239 {
12240   xtensa_isa isa = xtensa_default_isa;
12241   xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
12242   xtensa_opcode opcode;
12243   xtensa_format fmt;
12244   int slot;
12245   int num_opcodes = xtensa_isa_num_opcodes (isa);
12246 
12247   op_placement_table = XNEWVEC (op_placement_info, num_opcodes);
12248   gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
12249 
12250   for (opcode = 0; opcode < num_opcodes; opcode++)
12251     {
12252       op_placement_info *opi = &op_placement_table[opcode];
12253       /* FIXME: Make tinsn allocation dynamic.  */
12254       if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS)
12255 	as_fatal (_("too many operands in instruction"));
12256       opi->narrowest = XTENSA_UNDEFINED;
12257       opi->narrowest_size = 0x7F;
12258       opi->narrowest_slot = 0;
12259       opi->formats = 0;
12260       opi->num_formats = 0;
12261       opi->issuef = 0;
12262       for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
12263 	{
12264 	  opi->slots[fmt] = 0;
12265 	  for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
12266 	    {
12267 	      if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
12268 		{
12269 		  int fmt_length = xtensa_format_length (isa, fmt);
12270 		  opi->issuef++;
12271 		  set_bit (fmt, opi->formats);
12272 		  set_bit (slot, opi->slots[fmt]);
12273 		  if (fmt_length < opi->narrowest_size
12274 		      || (fmt_length == opi->narrowest_size
12275 			  && (xtensa_format_num_slots (isa, fmt)
12276 			      < xtensa_format_num_slots (isa,
12277 							 opi->narrowest))))
12278 		    {
12279 		      opi->narrowest = fmt;
12280 		      opi->narrowest_size = fmt_length;
12281 		      opi->narrowest_slot = slot;
12282 		    }
12283 		}
12284 	    }
12285 	  if (opi->formats)
12286 	    opi->num_formats++;
12287 	}
12288     }
12289   xtensa_insnbuf_free (isa, ibuf);
12290 }
12291 
12292 
12293 bfd_boolean
opcode_fits_format_slot(xtensa_opcode opcode,xtensa_format fmt,int slot)12294 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
12295 {
12296   return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
12297 }
12298 
12299 
12300 /* If the opcode is available in a single slot format, return its size.  */
12301 
12302 static int
xg_get_single_size(xtensa_opcode opcode)12303 xg_get_single_size (xtensa_opcode opcode)
12304 {
12305   return op_placement_table[opcode].narrowest_size;
12306 }
12307 
12308 
12309 static xtensa_format
xg_get_single_format(xtensa_opcode opcode)12310 xg_get_single_format (xtensa_opcode opcode)
12311 {
12312   return op_placement_table[opcode].narrowest;
12313 }
12314 
12315 
12316 static int
xg_get_single_slot(xtensa_opcode opcode)12317 xg_get_single_slot (xtensa_opcode opcode)
12318 {
12319   return op_placement_table[opcode].narrowest_slot;
12320 }
12321 
12322 
12323 /* Instruction Stack Functions (from "xtensa-istack.h").  */
12324 
12325 void
istack_init(IStack * stack)12326 istack_init (IStack *stack)
12327 {
12328   stack->ninsn = 0;
12329 }
12330 
12331 
12332 bfd_boolean
istack_empty(IStack * stack)12333 istack_empty (IStack *stack)
12334 {
12335   return (stack->ninsn == 0);
12336 }
12337 
12338 
12339 bfd_boolean
istack_full(IStack * stack)12340 istack_full (IStack *stack)
12341 {
12342   return (stack->ninsn == MAX_ISTACK);
12343 }
12344 
12345 
12346 /* Return a pointer to the top IStack entry.
12347    It is an error to call this if istack_empty () is TRUE. */
12348 
12349 TInsn *
istack_top(IStack * stack)12350 istack_top (IStack *stack)
12351 {
12352   int rec = stack->ninsn - 1;
12353   gas_assert (!istack_empty (stack));
12354   return &stack->insn[rec];
12355 }
12356 
12357 
12358 /* Add a new TInsn to an IStack.
12359    It is an error to call this if istack_full () is TRUE.  */
12360 
12361 void
istack_push(IStack * stack,TInsn * insn)12362 istack_push (IStack *stack, TInsn *insn)
12363 {
12364   int rec = stack->ninsn;
12365   gas_assert (!istack_full (stack));
12366   stack->insn[rec] = *insn;
12367   stack->ninsn++;
12368 }
12369 
12370 
12371 /* Clear space for the next TInsn on the IStack and return a pointer
12372    to it.  It is an error to call this if istack_full () is TRUE.  */
12373 
12374 TInsn *
istack_push_space(IStack * stack)12375 istack_push_space (IStack *stack)
12376 {
12377   int rec = stack->ninsn;
12378   TInsn *insn;
12379   gas_assert (!istack_full (stack));
12380   insn = &stack->insn[rec];
12381   tinsn_init (insn);
12382   stack->ninsn++;
12383   return insn;
12384 }
12385 
12386 
12387 /* Remove the last pushed instruction.  It is an error to call this if
12388    istack_empty () returns TRUE.  */
12389 
12390 void
istack_pop(IStack * stack)12391 istack_pop (IStack *stack)
12392 {
12393   int rec = stack->ninsn - 1;
12394   gas_assert (!istack_empty (stack));
12395   stack->ninsn--;
12396   tinsn_init (&stack->insn[rec]);
12397 }
12398 
12399 
12400 /* TInsn functions.  */
12401 
12402 void
tinsn_init(TInsn * dst)12403 tinsn_init (TInsn *dst)
12404 {
12405   memset (dst, 0, sizeof (TInsn));
12406 }
12407 
12408 
12409 /* Return TRUE if ANY of the operands in the insn are symbolic.  */
12410 
12411 static bfd_boolean
tinsn_has_symbolic_operands(const TInsn * insn)12412 tinsn_has_symbolic_operands (const TInsn *insn)
12413 {
12414   int i;
12415   int n = insn->ntok;
12416 
12417   gas_assert (insn->insn_type == ITYPE_INSN);
12418 
12419   for (i = 0; i < n; ++i)
12420     {
12421       switch (insn->tok[i].X_op)
12422 	{
12423 	case O_register:
12424 	case O_constant:
12425 	  break;
12426 	default:
12427 	  return TRUE;
12428 	}
12429     }
12430   return FALSE;
12431 }
12432 
12433 
12434 bfd_boolean
tinsn_has_invalid_symbolic_operands(const TInsn * insn)12435 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
12436 {
12437   xtensa_isa isa = xtensa_default_isa;
12438   int i;
12439   int n = insn->ntok;
12440 
12441   gas_assert (insn->insn_type == ITYPE_INSN);
12442 
12443   for (i = 0; i < n; ++i)
12444     {
12445       switch (insn->tok[i].X_op)
12446 	{
12447 	case O_register:
12448 	case O_constant:
12449 	  break;
12450 	case O_big:
12451 	case O_illegal:
12452 	case O_absent:
12453 	  /* Errors for these types are caught later.  */
12454 	  break;
12455 	case O_hi16:
12456 	case O_lo16:
12457 	default:
12458 	  /* Symbolic immediates are only allowed on the last immediate
12459 	     operand.  At this time, CONST16 is the only opcode where we
12460 	     support non-PC-relative relocations.  */
12461 	  if (i != get_relaxable_immed (insn->opcode)
12462 	      || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
12463 		  && insn->opcode != xtensa_const16_opcode))
12464 	    {
12465 	      as_bad (_("invalid symbolic operand"));
12466 	      return TRUE;
12467 	    }
12468 	}
12469     }
12470   return FALSE;
12471 }
12472 
12473 
12474 /* For assembly code with complex expressions (e.g. subtraction),
12475    we have to build them in the literal pool so that
12476    their results are calculated correctly after relaxation.
12477    The relaxation only handles expressions that
12478    boil down to SYMBOL + OFFSET.  */
12479 
12480 static bfd_boolean
tinsn_has_complex_operands(const TInsn * insn)12481 tinsn_has_complex_operands (const TInsn *insn)
12482 {
12483   int i;
12484   int n = insn->ntok;
12485   gas_assert (insn->insn_type == ITYPE_INSN);
12486   for (i = 0; i < n; ++i)
12487     {
12488       switch (insn->tok[i].X_op)
12489 	{
12490 	case O_register:
12491 	case O_constant:
12492 	case O_symbol:
12493 	case O_lo16:
12494 	case O_hi16:
12495 	  break;
12496 	default:
12497 	  return TRUE;
12498 	}
12499     }
12500   return FALSE;
12501 }
12502 
12503 
12504 /* Encode a TInsn opcode and its constant operands into slotbuf.
12505    Return TRUE if there is a symbol in the immediate field.  This
12506    function assumes that:
12507    1) The number of operands are correct.
12508    2) The insn_type is ITYPE_INSN.
12509    3) The opcode can be encoded in the specified format and slot.
12510    4) Operands are either O_constant or O_symbol, and all constants fit.  */
12511 
12512 static bfd_boolean
tinsn_to_slotbuf(xtensa_format fmt,int slot,TInsn * tinsn,xtensa_insnbuf slotbuf)12513 tinsn_to_slotbuf (xtensa_format fmt,
12514 		  int slot,
12515 		  TInsn *tinsn,
12516 		  xtensa_insnbuf slotbuf)
12517 {
12518   xtensa_isa isa = xtensa_default_isa;
12519   xtensa_opcode opcode = tinsn->opcode;
12520   bfd_boolean has_fixup = FALSE;
12521   int noperands = xtensa_opcode_num_operands (isa, opcode);
12522   int i;
12523 
12524   gas_assert (tinsn->insn_type == ITYPE_INSN);
12525   if (noperands != tinsn->ntok)
12526     as_fatal (_("operand number mismatch"));
12527 
12528   if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
12529     {
12530       as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12531 	      xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
12532       return FALSE;
12533     }
12534 
12535   for (i = 0; i < noperands; i++)
12536     {
12537       expressionS *exp = &tinsn->tok[i];
12538       int rc;
12539       unsigned line;
12540       const char *file_name;
12541       uint32 opnd_value;
12542 
12543       switch (exp->X_op)
12544 	{
12545 	case O_register:
12546 	  if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12547 	    break;
12548 	  /* The register number has already been checked in
12549 	     expression_maybe_register, so we don't need to check here.  */
12550 	  opnd_value = exp->X_add_number;
12551 	  (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
12552 	  rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
12553 					 opnd_value);
12554 	  if (rc != 0)
12555 	    as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
12556 	  break;
12557 
12558 	case O_constant:
12559 	  if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12560 	    break;
12561 	  file_name = as_where (&line);
12562 	  /* It is a constant and we called this function
12563 	     then we have to try to fit it.  */
12564 	  xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
12565 				      exp->X_add_number, file_name, line);
12566 	  break;
12567 
12568 	default:
12569 	  has_fixup = TRUE;
12570 	  break;
12571 	}
12572     }
12573 
12574   return has_fixup;
12575 }
12576 
12577 
12578 /* Encode a single TInsn into an insnbuf.  If the opcode can only be encoded
12579    into a multi-slot instruction, fill the other slots with NOPs.
12580    Return TRUE if there is a symbol in the immediate field.  See also the
12581    assumptions listed for tinsn_to_slotbuf.  */
12582 
12583 static bfd_boolean
tinsn_to_insnbuf(TInsn * tinsn,xtensa_insnbuf insnbuf)12584 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
12585 {
12586   static xtensa_insnbuf slotbuf = 0;
12587   static vliw_insn vinsn;
12588   xtensa_isa isa = xtensa_default_isa;
12589   bfd_boolean has_fixup = FALSE;
12590   int i;
12591 
12592   if (!slotbuf)
12593     {
12594       slotbuf = xtensa_insnbuf_alloc (isa);
12595       xg_init_vinsn (&vinsn);
12596     }
12597 
12598   xg_clear_vinsn (&vinsn);
12599 
12600   bundle_tinsn (tinsn, &vinsn);
12601 
12602   xtensa_format_encode (isa, vinsn.format, insnbuf);
12603 
12604   for (i = 0; i < vinsn.num_slots; i++)
12605     {
12606       /* Only one slot may have a fix-up because the rest contains NOPs.  */
12607       has_fixup |=
12608 	tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
12609       xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
12610     }
12611 
12612   return has_fixup;
12613 }
12614 
12615 
12616 /* Check the instruction arguments.  Return TRUE on failure.  */
12617 
12618 static bfd_boolean
tinsn_check_arguments(const TInsn * insn)12619 tinsn_check_arguments (const TInsn *insn)
12620 {
12621   xtensa_isa isa = xtensa_default_isa;
12622   xtensa_opcode opcode = insn->opcode;
12623   xtensa_regfile t1_regfile, t2_regfile;
12624   int t1_reg, t2_reg;
12625   int t1_base_reg, t1_last_reg;
12626   int t2_base_reg, t2_last_reg;
12627   char t1_inout, t2_inout;
12628   int i, j;
12629 
12630   if (opcode == XTENSA_UNDEFINED)
12631     {
12632       as_bad (_("invalid opcode"));
12633       return TRUE;
12634     }
12635 
12636   if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
12637     {
12638       as_bad (_("too few operands"));
12639       return TRUE;
12640     }
12641 
12642   if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
12643     {
12644       as_bad (_("too many operands"));
12645       return TRUE;
12646     }
12647 
12648   /* Check registers.  */
12649   for (j = 0; j < insn->ntok; j++)
12650     {
12651       if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
12652 	continue;
12653 
12654       t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
12655       t2_base_reg = insn->tok[j].X_add_number;
12656       t2_last_reg
12657 	= t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
12658 
12659       for (i = 0; i < insn->ntok; i++)
12660 	{
12661 	  if (i == j)
12662 	    continue;
12663 
12664 	  if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
12665 	    continue;
12666 
12667 	  t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
12668 
12669 	  if (t1_regfile != t2_regfile)
12670 	    continue;
12671 
12672 	  t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
12673 	  t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
12674 
12675 	  t1_base_reg = insn->tok[i].X_add_number;
12676 	  t1_last_reg = (t1_base_reg
12677 			 + xtensa_operand_num_regs (isa, insn->opcode, i));
12678 
12679 	  for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
12680 	    {
12681 	      for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
12682 		{
12683 		  if (t1_reg != t2_reg)
12684 		    continue;
12685 
12686 		  if (t1_inout != 'i' && t2_inout != 'i')
12687 		    {
12688 		      as_bad (_("multiple writes to the same register"));
12689 		      return TRUE;
12690 		    }
12691 		}
12692 	    }
12693 	}
12694     }
12695   return FALSE;
12696 }
12697 
12698 
12699 /* Load an instruction from its encoded form.  */
12700 
12701 static void
tinsn_from_chars(TInsn * tinsn,char * f,int slot)12702 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
12703 {
12704   vliw_insn vinsn;
12705 
12706   xg_init_vinsn (&vinsn);
12707   vinsn_from_chars (&vinsn, f);
12708 
12709   *tinsn = vinsn.slots[slot];
12710   xg_free_vinsn (&vinsn);
12711 }
12712 
12713 
12714 static void
tinsn_from_insnbuf(TInsn * tinsn,xtensa_insnbuf slotbuf,xtensa_format fmt,int slot)12715 tinsn_from_insnbuf (TInsn *tinsn,
12716 		    xtensa_insnbuf slotbuf,
12717 		    xtensa_format fmt,
12718 		    int slot)
12719 {
12720   int i;
12721   xtensa_isa isa = xtensa_default_isa;
12722 
12723   /* Find the immed.  */
12724   tinsn_init (tinsn);
12725   tinsn->insn_type = ITYPE_INSN;
12726   tinsn->is_specific_opcode = FALSE;	/* must not be specific */
12727   tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
12728   tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
12729   for (i = 0; i < tinsn->ntok; i++)
12730     {
12731       set_expr_const (&tinsn->tok[i],
12732 		      xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
12733 						  tinsn->opcode, i));
12734     }
12735 }
12736 
12737 
12738 /* Read the value of the relaxable immed from the fr_symbol and fr_offset.  */
12739 
12740 static void
tinsn_immed_from_frag(TInsn * tinsn,fragS * fragP,int slot)12741 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
12742 {
12743   xtensa_opcode opcode = tinsn->opcode;
12744   int opnum;
12745 
12746   if (fragP->tc_frag_data.slot_symbols[slot])
12747     {
12748       opnum = get_relaxable_immed (opcode);
12749       gas_assert (opnum >= 0);
12750       set_expr_symbol_offset (&tinsn->tok[opnum],
12751 			      fragP->tc_frag_data.slot_symbols[slot],
12752 			      fragP->tc_frag_data.slot_offsets[slot]);
12753     }
12754   tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot];
12755 }
12756 
12757 
12758 static int
get_num_stack_text_bytes(IStack * istack)12759 get_num_stack_text_bytes (IStack *istack)
12760 {
12761   int i;
12762   int text_bytes = 0;
12763 
12764   for (i = 0; i < istack->ninsn; i++)
12765     {
12766       TInsn *tinsn = &istack->insn[i];
12767       if (tinsn->insn_type == ITYPE_INSN)
12768 	text_bytes += xg_get_single_size (tinsn->opcode);
12769     }
12770   return text_bytes;
12771 }
12772 
12773 
12774 static int
get_num_stack_literal_bytes(IStack * istack)12775 get_num_stack_literal_bytes (IStack *istack)
12776 {
12777   int i;
12778   int lit_bytes = 0;
12779 
12780   for (i = 0; i < istack->ninsn; i++)
12781     {
12782       TInsn *tinsn = &istack->insn[i];
12783       if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
12784 	lit_bytes += 4;
12785     }
12786   return lit_bytes;
12787 }
12788 
12789 
12790 /* vliw_insn functions.  */
12791 
12792 static void
xg_init_vinsn(vliw_insn * v)12793 xg_init_vinsn (vliw_insn *v)
12794 {
12795   int i;
12796   xtensa_isa isa = xtensa_default_isa;
12797 
12798   xg_clear_vinsn (v);
12799 
12800   v->insnbuf = xtensa_insnbuf_alloc (isa);
12801   if (v->insnbuf == NULL)
12802     as_fatal (_("out of memory"));
12803 
12804   for (i = 0; i < config_max_slots; i++)
12805     {
12806       v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
12807       if (v->slotbuf[i] == NULL)
12808 	as_fatal (_("out of memory"));
12809     }
12810 }
12811 
12812 
12813 static void
xg_clear_vinsn(vliw_insn * v)12814 xg_clear_vinsn (vliw_insn *v)
12815 {
12816   int i;
12817 
12818   memset (v, 0, offsetof (vliw_insn, slots)
12819                 + sizeof(TInsn) * config_max_slots);
12820 
12821   v->format = XTENSA_UNDEFINED;
12822   v->num_slots = 0;
12823   v->inside_bundle = FALSE;
12824 
12825   if (xt_saved_debug_type != DEBUG_NONE)
12826     debug_type = xt_saved_debug_type;
12827 
12828   for (i = 0; i < config_max_slots; i++)
12829     v->slots[i].opcode = XTENSA_UNDEFINED;
12830 }
12831 
12832 
12833 static void
xg_copy_vinsn(vliw_insn * dst,vliw_insn * src)12834 xg_copy_vinsn (vliw_insn *dst, vliw_insn *src)
12835 {
12836   memcpy (dst, src,
12837 	  offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn));
12838   dst->insnbuf = src->insnbuf;
12839   memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf));
12840 }
12841 
12842 
12843 static bfd_boolean
vinsn_has_specific_opcodes(vliw_insn * v)12844 vinsn_has_specific_opcodes (vliw_insn *v)
12845 {
12846   int i;
12847 
12848   for (i = 0; i < v->num_slots; i++)
12849     {
12850       if (v->slots[i].is_specific_opcode)
12851 	return TRUE;
12852     }
12853   return FALSE;
12854 }
12855 
12856 
12857 static void
xg_free_vinsn(vliw_insn * v)12858 xg_free_vinsn (vliw_insn *v)
12859 {
12860   int i;
12861   xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
12862   for (i = 0; i < config_max_slots; i++)
12863     xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
12864 }
12865 
12866 
12867 /* Encode a vliw_insn into an insnbuf.  Return TRUE if there are any symbolic
12868    operands.  See also the assumptions listed for tinsn_to_slotbuf.  */
12869 
12870 static bfd_boolean
vinsn_to_insnbuf(vliw_insn * vinsn,char * frag_offset,fragS * fragP,bfd_boolean record_fixup)12871 vinsn_to_insnbuf (vliw_insn *vinsn,
12872 		  char *frag_offset,
12873 		  fragS *fragP,
12874 		  bfd_boolean record_fixup)
12875 {
12876   xtensa_isa isa = xtensa_default_isa;
12877   xtensa_format fmt = vinsn->format;
12878   xtensa_insnbuf insnbuf = vinsn->insnbuf;
12879   int slot;
12880   bfd_boolean has_fixup = FALSE;
12881 
12882   xtensa_format_encode (isa, fmt, insnbuf);
12883 
12884   for (slot = 0; slot < vinsn->num_slots; slot++)
12885     {
12886       TInsn *tinsn = &vinsn->slots[slot];
12887       expressionS *extra_arg = &tinsn->extra_arg;
12888       bfd_boolean tinsn_has_fixup =
12889 	tinsn_to_slotbuf (vinsn->format, slot, tinsn,
12890 			  vinsn->slotbuf[slot]);
12891 
12892       xtensa_format_set_slot (isa, fmt, slot,
12893 			      insnbuf, vinsn->slotbuf[slot]);
12894       if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register)
12895 	{
12896 	  if (vinsn->num_slots != 1)
12897 	    as_bad (_("TLS relocation not allowed in FLIX bundle"));
12898 	  else if (record_fixup)
12899 	    /* Instructions that generate TLS relocations should always be
12900 	       relaxed in the front-end.  If "record_fixup" is set, then this
12901 	       function is being called during back-end relaxation, so flag
12902 	       the unexpected behavior as an error.  */
12903 	    as_bad (_("unexpected TLS relocation"));
12904 	  else
12905 	    fix_new (fragP, frag_offset - fragP->fr_literal,
12906 		     xtensa_format_length (isa, fmt),
12907 		     extra_arg->X_add_symbol, extra_arg->X_add_number,
12908 		     FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE));
12909 	}
12910       if (tinsn_has_fixup)
12911 	{
12912 	  int i;
12913 	  xtensa_opcode opcode = tinsn->opcode;
12914 	  int noperands = xtensa_opcode_num_operands (isa, opcode);
12915 	  has_fixup = TRUE;
12916 
12917 	  for (i = 0; i < noperands; i++)
12918 	    {
12919 	      expressionS* exp = &tinsn->tok[i];
12920 	      switch (exp->X_op)
12921 		{
12922 		case O_symbol:
12923 		case O_lo16:
12924 		case O_hi16:
12925 		  if (get_relaxable_immed (opcode) == i)
12926 		    {
12927 		      /* Add a fix record for the instruction, except if this
12928 			 function is being called prior to relaxation, i.e.,
12929 			 if record_fixup is false, and the instruction might
12930 			 be relaxed later.  */
12931 		      if (record_fixup
12932 			  || tinsn->is_specific_opcode
12933 			  || !xg_is_relaxable_insn (tinsn, 0))
12934 			{
12935 			  xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP,
12936 					     frag_offset - fragP->fr_literal);
12937 			}
12938 		      else
12939 			{
12940 			  if (exp->X_op != O_symbol)
12941 			    as_bad (_("invalid operand"));
12942 			  tinsn->symbol = exp->X_add_symbol;
12943 			  tinsn->offset = exp->X_add_number;
12944 			}
12945 		    }
12946 		  else
12947 		    as_bad (_("symbolic operand not allowed"));
12948 		  break;
12949 
12950 		case O_constant:
12951 		case O_register:
12952 		  break;
12953 
12954 		default:
12955 		  as_bad (_("expression too complex"));
12956 		  break;
12957 		}
12958 	    }
12959 	}
12960     }
12961 
12962   return has_fixup;
12963 }
12964 
12965 
12966 static void
vinsn_from_chars(vliw_insn * vinsn,char * f)12967 vinsn_from_chars (vliw_insn *vinsn, char *f)
12968 {
12969   static xtensa_insnbuf insnbuf = NULL;
12970   static xtensa_insnbuf slotbuf = NULL;
12971   int i;
12972   xtensa_format fmt;
12973   xtensa_isa isa = xtensa_default_isa;
12974 
12975   if (!insnbuf)
12976     {
12977       insnbuf = xtensa_insnbuf_alloc (isa);
12978       slotbuf = xtensa_insnbuf_alloc (isa);
12979     }
12980 
12981   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
12982   fmt = xtensa_format_decode (isa, insnbuf);
12983   if (fmt == XTENSA_UNDEFINED)
12984     as_fatal (_("cannot decode instruction format"));
12985   vinsn->format = fmt;
12986   vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
12987 
12988   for (i = 0; i < vinsn->num_slots; i++)
12989     {
12990       TInsn *tinsn = &vinsn->slots[i];
12991       xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
12992       tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
12993     }
12994 }
12995 
12996 
12997 /* Expression utilities.  */
12998 
12999 /* Return TRUE if the expression is an integer constant.  */
13000 
13001 bfd_boolean
expr_is_const(const expressionS * s)13002 expr_is_const (const expressionS *s)
13003 {
13004   return (s->X_op == O_constant);
13005 }
13006 
13007 
13008 /* Get the expression constant.
13009    Calling this is illegal if expr_is_const () returns TRUE.  */
13010 
13011 offsetT
get_expr_const(const expressionS * s)13012 get_expr_const (const expressionS *s)
13013 {
13014   gas_assert (expr_is_const (s));
13015   return s->X_add_number;
13016 }
13017 
13018 
13019 /* Set the expression to a constant value.  */
13020 
13021 void
set_expr_const(expressionS * s,offsetT val)13022 set_expr_const (expressionS *s, offsetT val)
13023 {
13024   s->X_op = O_constant;
13025   s->X_add_number = val;
13026   s->X_add_symbol = NULL;
13027   s->X_op_symbol = NULL;
13028 }
13029 
13030 
13031 bfd_boolean
expr_is_register(const expressionS * s)13032 expr_is_register (const expressionS *s)
13033 {
13034   return (s->X_op == O_register);
13035 }
13036 
13037 
13038 /* Get the expression constant.
13039    Calling this is illegal if expr_is_const () returns TRUE.  */
13040 
13041 offsetT
get_expr_register(const expressionS * s)13042 get_expr_register (const expressionS *s)
13043 {
13044   gas_assert (expr_is_register (s));
13045   return s->X_add_number;
13046 }
13047 
13048 
13049 /* Set the expression to a symbol + constant offset.  */
13050 
13051 void
set_expr_symbol_offset(expressionS * s,symbolS * sym,offsetT offset)13052 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
13053 {
13054   s->X_op = O_symbol;
13055   s->X_add_symbol = sym;
13056   s->X_op_symbol = NULL;	/* unused */
13057   s->X_add_number = offset;
13058 }
13059 
13060 
13061 /* Return TRUE if the two expressions are equal.  */
13062 
13063 bfd_boolean
expr_is_equal(expressionS * s1,expressionS * s2)13064 expr_is_equal (expressionS *s1, expressionS *s2)
13065 {
13066   if (s1->X_op != s2->X_op)
13067     return FALSE;
13068   if (s1->X_add_symbol != s2->X_add_symbol)
13069     return FALSE;
13070   if (s1->X_op_symbol != s2->X_op_symbol)
13071     return FALSE;
13072   if (s1->X_add_number != s2->X_add_number)
13073     return FALSE;
13074   return TRUE;
13075 }
13076 
13077 
13078 static void
copy_expr(expressionS * dst,const expressionS * src)13079 copy_expr (expressionS *dst, const expressionS *src)
13080 {
13081   memcpy (dst, src, sizeof (expressionS));
13082 }
13083 
13084 
13085 /* Support for the "--rename-section" option.  */
13086 
13087 struct rename_section_struct
13088 {
13089   const char *old_name;
13090   char *new_name;
13091   struct rename_section_struct *next;
13092 };
13093 
13094 static struct rename_section_struct *section_rename;
13095 
13096 
13097 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13098    entries to the section_rename list.  Note: Specifying multiple
13099    renamings separated by colons is not documented and is retained only
13100    for backward compatibility.  */
13101 
13102 static void
build_section_rename(const char * arg)13103 build_section_rename (const char *arg)
13104 {
13105   struct rename_section_struct *r;
13106   char *this_arg = NULL;
13107   char *next_arg = NULL;
13108 
13109   for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
13110     {
13111       char *old_name, *new_name;
13112 
13113       if (this_arg)
13114 	{
13115 	  next_arg = strchr (this_arg, ':');
13116 	  if (next_arg)
13117 	    {
13118 	      *next_arg = '\0';
13119 	      next_arg++;
13120 	    }
13121 	}
13122 
13123       old_name = this_arg;
13124       new_name = strchr (this_arg, '=');
13125 
13126       if (*old_name == '\0')
13127 	{
13128 	  as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13129 	  continue;
13130 	}
13131       if (!new_name || new_name[1] == '\0')
13132 	{
13133 	  as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13134 		   old_name);
13135 	  continue;
13136 	}
13137       *new_name = '\0';
13138       new_name++;
13139 
13140       /* Check for invalid section renaming.  */
13141       for (r = section_rename; r != NULL; r = r->next)
13142 	{
13143 	  if (strcmp (r->old_name, old_name) == 0)
13144 	    as_bad (_("section %s renamed multiple times"), old_name);
13145 	  if (strcmp (r->new_name, new_name) == 0)
13146 	    as_bad (_("multiple sections remapped to output section %s"),
13147 		    new_name);
13148 	}
13149 
13150       /* Now add it.  */
13151       r = XNEW (struct rename_section_struct);
13152       r->old_name = xstrdup (old_name);
13153       r->new_name = xstrdup (new_name);
13154       r->next = section_rename;
13155       section_rename = r;
13156     }
13157 }
13158 
13159 
13160 char *
xtensa_section_rename(const char * name)13161 xtensa_section_rename (const char *name)
13162 {
13163   struct rename_section_struct *r = section_rename;
13164 
13165   for (r = section_rename; r != NULL; r = r->next)
13166     {
13167       if (strcmp (r->old_name, name) == 0)
13168 	return r->new_name;
13169     }
13170 
13171   return (char *) name;
13172 }
13173