| /art/test/427-bitwise/src/ |
| D | Main.java | 45 expectEquals(1, $opt$And(5, 3)); in andInt()
46 expectEquals(0, $opt$And(0, 0)); in andInt()
47 expectEquals(0, $opt$And(0, 3)); in andInt()
48 expectEquals(0, $opt$And(3, 0)); in andInt()
49 expectEquals(1, $opt$And(1, -3)); in andInt()
50 expectEquals(-12, $opt$And(-12, -3)); in andInt()
66 expectEquals(1L, $opt$And(5L, 3L)); in andLong()
67 expectEquals(0L, $opt$And(0L, 0L)); in andLong()
68 expectEquals(0L, $opt$And(0L, 3L)); in andLong()
69 expectEquals(0L, $opt$And(3L, 0L)); in andLong()
[all …]
|
| /art/test/565-checker-doublenegbitwise/smali/ |
| D | SmaliTests.smali | 19 # Test transformation of Not/Not/And into Or/Not.
27 ## CHECK-DAG: <<And:i\d+>> And [<<Not1>>,<<Not2>>]
28 ## CHECK-DAG: Return [<<And>>]
42 ## CHECK-NOT: And
64 # Test transformation of Not/Not/And into Or/Not for boolean negations.
76 ## CHECK-DAG: <<And:i\d+>> And [<<NotP1>>,<<NotP2>>]
77 ## CHECK-DAG: Return [<<And>>]
91 ## CHECK-NOT: And
112 # Test transformation of Not/Not/Or into And/Not.
125 ## CHECK-DAG: <<And:j\d+>> And [<<P1>>,<<P2>>]
[all …]
|
| /art/test/593-checker-shift-and-simplifier/smali/ |
| D | SmaliTests.smali | 25 ## CHECK-DAG: And [<<Not>>,<<Shl>>]
30 ## CHECK-DAG: DataProcWithShifterOp [<<Not>>,<<Get>>] kind:And+LSL shift:2
36 ## CHECK-DAG: And [<<Not>>,<<Shl>>]
41 ## CHECK-DAG: DataProcWithShifterOp [<<Not>>,<<Get>>] kind:And+LSL shift:2
|
| /art/test/020-string/ |
| D | expected.txt | 13 llo And
|
| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 286 __ And(TMP, out, AT); in GenReverse() local
289 __ And(out, out, AT); in GenReverse() local
297 __ And(TMP, out, AT); in GenReverse() local
300 __ And(out, out, AT); in GenReverse() local
303 __ And(TMP, out, AT); in GenReverse() local
306 __ And(out, out, AT); in GenReverse() local
309 __ And(TMP, out, AT); in GenReverse() local
312 __ And(out, out, AT); in GenReverse() local
345 __ And(out_hi, TMP, AT); in GenReverse() local
348 __ And(TMP, TMP, AT); in GenReverse() local
[all …]
|
| D | scheduler_arm.h | 70 M(And , unused) \
|
| D | intrinsics_mips64.cc | 421 __ And(TMP, TMP, AT); in GenBitCount() local
424 __ And(out, TMP, AT); in GenBitCount() local
426 __ And(TMP, TMP, AT); in GenBitCount() local
431 __ And(out, out, AT); in GenBitCount() local
438 __ And(TMP, TMP, AT); in GenBitCount() local
441 __ And(out, TMP, AT); in GenBitCount() local
443 __ And(TMP, TMP, AT); in GenBitCount() local
448 __ And(out, out, AT); in GenBitCount() local
2265 __ And(out, AT, in); in GenHighestOneBit() local
2299 __ And(out, TMP, in); in GenLowestOneBit() local
|
| D | intrinsics_arm_vixl.cc | 557 __ And(temp1, temp1, temp2); in GenMinMaxFloat() local
1666 __ And(temp2, temp2, temp3); in GenerateStringCompareToLoop() local
1667 __ And(out, out, temp3); in GenerateStringCompareToLoop() local
3031 __ And(out_reg_hi, out_reg_hi, in_reg_hi); in GenLowestOneBit() local
3055 __ And(out, temp, in); in GenLowestOneBit() local
|
| D | code_generator_arm_vixl.cc | 1573 __ And(out, first, second); in GenerateDataProcInstruction() local
4806 __ And(shift_right, RegisterFrom(rhs), 0x1F); in HandleLongRotate() local
4936 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift() local
4972 __ And(o_l, second_reg, kMaxLongShiftDistance); in HandleShift() local
4991 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
5010 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
8122 __ And(out, first, value); in GenerateAndConst() local
8240 __ And(out_reg, first_reg, second_reg); in HandleBitwiseOperation() local
8256 __ And(out_low, first_low, second_low); in HandleBitwiseOperation() local
8257 __ And(out_high, first_high, second_high); in HandleBitwiseOperation() local
|
| D | intrinsics_arm64.cc | 513 __ And(dst, temp, src); in GenLowestOneBit() local
1675 __ And(temp1, temp, Operand(1)); // Extract compression flag. in VisitStringEquals() local
|
| D | code_generator_mips.cc | 2064 __ And(dst, lhs, rhs_reg); in HandleBinaryOp() local
2116 __ And(dst_low, lhs_low, rhs_low); in HandleBinaryOp() local
2117 __ And(dst_high, lhs_high, rhs_high); in HandleBinaryOp() local
2194 __ And(dst_low, lhs_low, TMP); in HandleBinaryOp() local
2204 __ And(dst_high, lhs_high, TMP); in HandleBinaryOp() local
3876 __ And(TMP, in_high, TMP); in DivRemByPowerOfTwo() local
|
| D | code_generator_vector_arm64.cc | 699 __ And(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecAnd() local
|
| D | code_generator_arm64.cc | 2370 __ And(dst, lhs, rhs); in HandleBinaryOp() local
2565 __ And(out, left, right_operand); in VisitDataProcWithShifterOp() local
3316 __ And(out, out, abs_imm - 1); in DivRemByPowerOfTwo() local
|
| D | nodes.h | 1342 M(And, BinaryOperation) \
5217 DECLARE_INSTRUCTION(And);
5220 DEFAULT_COPY_CONSTRUCTOR(And);
|
| /art/test/800-smali/smali/ |
| D | b_22411633_1.smali | 30 # And test whether it's initialized by calling hashCode.
|
| D | b_22881413.smali | 133 # And somewhere at the end
|
| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 91 WITH_FLAGS_DONT_CARE_RD_RN_OP(And);
|
| /art/test/953-invoke-polymorphic-compiler/src/ |
| D | Main.java | 182 private static boolean And(boolean lhs, boolean rhs) { in And() method in Main
|
| /art/tools/dexfuzz/ |
| D | README | 54 And also at least two of the following backends:
|
| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 400 TEST_F(AssemblerMIPSTest, And) { in TEST_F() argument
401 DriverStr(RepeatRRR(&mips::MipsAssembler::And, "and ${reg1}, ${reg2}, ${reg3}"), "And"); in TEST_F()
2314 __ And(mips::T0, mips::T1, mips::T2); in TEST_F() local
2460 __ And(mips::T0, mips::T1, mips::T2); in TEST_F() local
|
| D | assembler_mips.h | 321 void And(Register rd, Register rs, Register rt);
|
| D | assembler_mips.cc | 557 void MipsAssembler::And(Register rd, Register rs, Register rt) { in And() function in art::mips::MipsAssembler
|
| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1181 TEST_F(AssemblerMIPS64Test, And) { in TEST_F() argument
1182 DriverStr(RepeatRRR(&mips64::Mips64Assembler::And, "and ${reg1}, ${reg2}, ${reg3}"), "and"); in TEST_F()
|
| D | assembler_mips64.h | 466 void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
|
| D | assembler_mips64.cc | 375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And() function in art::mips64::Mips64Assembler
|