Searched refs:Bnez (Results 1 – 6 of 6) sorted by relevance
| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 2710 __ Bnez(TMP, &uncompressed_copy); in VisitStringGetCharsNoCheck() local
2720 __ Bnez(numChrs, &compressed_loop); in VisitStringGetCharsNoCheck() local
2736 __ Bnez(numChrs, &loop); in VisitStringGetCharsNoCheck() local
2996 __ Bnez(TMP, slow_path->GetEntryLabel()); in EnoughItems() local
3037 __ Bnez(pos_reg, slow_path->GetEntryLabel()); in CheckPosition() local
3134 __ Bnez(count, &loop); in VisitSystemArrayCopyChar() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 2189 TEST_F(AssemblerMIPSTest, Bnez) { in TEST_F() argument
2190 BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez"); in TEST_F()
2254 BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare */ true); in TEST_F()
2346 __ Bnez(mips::T0, &label2); // No preceding instruction for the delay slot. in TEST_F() local
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| D | assembler_mips32r6_test.cc | 1154 TEST_F(AssemblerMIPS32r6Test, Bnez) { in TEST_F() argument
1155 BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnezc"); in TEST_F()
1275 BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare */ true); in TEST_F()
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| D | assembler_mips.h | 399 void Bnez(Register rt, uint16_t imm16);
799 void Bnez(Register rt, MipsLabel* label, bool is_bare = false);
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.h | 574 void Bnez(GpuRegister rt, uint16_t imm16); // R2
1029 void Bnez(GpuRegister rs, Mips64Label* label, bool is_bare = false); // R2
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| D | assembler_mips64.cc | 841 void Mips64Assembler::Bnez(GpuRegister rt, uint16_t imm16) { in Bnez() function in art::mips64::Mips64Assembler
961 Bnez(rs, imm16); in EmitBcondR2()
3351 void Mips64Assembler::Bnez(GpuRegister rs, Mips64Label* label, bool is_bare) { in Bnez() function in art::mips64::Mips64Assembler
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