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/art/runtime/interpreter/mterp/out/
Dmterp_mips64.S28 #define a0 $4 /* argument registers */ macro
407 move rSELF, a0
420 ld a0, OFF_FP_METHOD(rFP)
455 GET_VREG a0, a3 # a0 <- vB
458 SET_VREG_OBJECT a0, a2 # vA <- vB
460 SET_VREG a0, a2 # vA <- vB
473 GET_VREG a0, a3 # a0 <- vBBBB
476 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB
478 SET_VREG a0, a2 # vAA <- vBBBB
491 GET_VREG a0, a3 # a0 <- vBBBB
[all …]
/art/runtime/interpreter/mterp/mips/
Dop_aget_wide.S7 FETCH(a0, 1) # a0 <- CCBB
9 and a2, a0, 255 # a2 <- BB
10 srl a3, a0, 8 # a3 <- CC
11 GET_VREG(a0, a2) # a0 <- vBB (array object)
14 beqz a0, common_errNullObject # yes, bail
15 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
16 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width
20 LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET)
Dop_shl_long.S8 FETCH(a0, 1) # a0 <- CCBB
10 and a3, a0, 255 # a3 <- BB
11 srl a0, a0, 8 # a0 <- CC
13 GET_VREG(a2, a0) # a2 <- vCC
14 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
20 sll v0, a0, a2 # rlo<- alo << (shift&31)
23 srl a0, 1
24 srl a0, v1 # alo<- alo >> (32-(shift&31))
26 or v1, a0 # rhi<- rhi | alo
Dop_aput_wide.S5 FETCH(a0, 1) # a0 <- CCBB
7 and a2, a0, 255 # a2 <- BB
8 srl a3, a0, 8 # a3 <- CC
9 GET_VREG(a0, a2) # a0 <- vBB (array object)
12 beqz a0, common_errNullObject # yes, bail
13 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
14 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width
23 STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC]
Dop_mul_long.S13 FETCH(a0, 1) # a0 <- CCBB
14 and t0, a0, 255 # a2 <- BB
15 srl t1, a0, 8 # a3 <- CC
17 LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1
22 mul v1, a3, a0 # v1= a3a0
24 mulu v0, a2, a0 # v0= a2a0
25 muhu t1, a2, a0
27 multu a2, a0
35 GET_OPA(a0) # a0 <- AA
42 SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high)
Dop_packed_switch.S12 FETCH(a0, 1) # a0 <- bbbb (lo)
15 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb
17 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
18 JAL($func) # a0 <- code-unit branch offset
Dop_move_result.S6 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
7 lw a0, 0(a0) # a0 <- result.i
10 SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0
12 SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0
Dop_ushr_long.S8 FETCH(a0, 1) # a0 <- CCBB
10 and a3, a0, 255 # a3 <- BB
11 srl a0, a0, 8 # a0 <- CC
13 GET_VREG(a2, a0) # a2 <- vCC
14 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
22 srl v0, a0, a2 # rlo<- alo >> (shift&31)
23 not a0, a2 # alo<- 31-n (shift is 5b)
25 sll a1, a0 # ahi<- ahi << (32-(shift&31))
Dop_const_high16.S2 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended)
4 sll a0, a0, 16 # a0 <- BBBB0000
7 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
Dop_shr_long.S8 FETCH(a0, 1) # a0 <- CCBB
10 and a3, a0, 255 # a3 <- BB
11 srl a0, a0, 8 # a0 <- CC
13 GET_VREG(a2, a0) # a2 <- vCC
14 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
21 srl v0, a0, a2 # rlo<- alo >> (shift&31)
22 not a0, a2 # alo<- 31-shift (shift is 5b)
24 sll a1, a0 # ahi<- ahi << (32-(shift&31))
Dop_const_wide_32.S2 FETCH(a0, 1) # a0 <- 0000bbbb (low)
6 INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb
7 sra a1, a0, 31 # a1 <- ssssssss
9 SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1
Dop_const.S3 FETCH(a0, 1) # a0 <- bbbb (low)
6 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb
8 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
Dbinop.S17 FETCH(a0, 1) # a0 <- CCBB
19 srl a3, a0, 8 # a3 <- CC
20 and a2, a0, 255 # a2 <- BB
22 GET_VREG(a0, a2) # a0 <- vBB
30 $instr # $result <- op, a0-a3 changed
Dop_aput.S15 GET_VREG(a0, a2) # a0 <- vBB (array object)
18 beqz a0, common_errNullObject # yes, bail
19 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
20 EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width
26 $store a2, $data_offset(a0) # vBB[vCC] <- a2
Dop_iput_wide_quick.S2 GET_OPA4(a0) # a0 <- A(+)
7 EAS2(a3, rFP, a0) # a3 <- &fp[A]
8 LOAD64(a0, a1, a3) # a0/a1 <- fp[A]
11 addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1
14 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1
Dop_aget.S17 GET_VREG(a0, a2) # a0 <- vBB (array object)
20 beqz a0, common_errNullObject # yes, bail
21 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
22 EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width
26 $load a2, $data_offset(a0) # a2 <- vBB[vCC]
/art/runtime/interpreter/mterp/mips64/
Dop_aget.S14 GET_VREG_U a0, a2 # a0 <- vBB (array object)
16 beqz a0, common_errNullObject # bail if null array object
17 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
20 dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width
22 daddu a0, a1, a0 # a0 <- arrayObj + index*width
26 $load a2, $data_offset(a0) # a2 <- vBB[vCC]
Dop_aput.S14 GET_VREG_U a0, a2 # a0 <- vBB (array object)
16 beqz a0, common_errNullObject # bail if null array object
17 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
20 dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width
22 daddu a0, a1, a0 # a0 <- arrayObj + index*width
28 $store a2, $data_offset(a0) # vBB[vCC] <- a2
Dop_iput_wide_quick.S5 ext a0, rINST, 8, 4 # a0 <- A
7 GET_VREG_WIDE a0, a0 # a0 <- fp[A]
10 sw a0, 0(a1)
11 dsrl32 a0, a0, 0
12 sw a0, 4(a1)
Dop_cmp_long.S5 GET_VREG_WIDE a0, a2 # a0 <- vBB
8 slt a2, a0, a1
9 slt a0, a1, a0
10 subu a0, a0, a2
12 SET_VREG a0, a4 # vAA <- result
Dop_packed_switch.S13 lh a0, 2(rPC) # a0 <- bbbb (lo)
16 ins a0, a1, 16, 16 # a0 <- BBBBbbbb
18 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2
Dop_aput_wide.S9 GET_VREG_U a0, a2 # a0 <- vBB (array object)
11 beqz a0, common_errNullObject # bail if null array object
12 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
13 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width
18 sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0)
20 sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2
Dop_aget_wide.S9 GET_VREG_U a0, a2 # a0 <- vBB (array object)
11 beqz a0, common_errNullObject # bail if null array object
12 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
13 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width
16 lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0)
17 lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0)
Dop_const_wide_high16.S3 lh a0, 2(rPC) # a0 <- BBBB
5 dsll32 a0, a0, 16 # a0 <- BBBB000000000000
7 SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000
Dop_const_high16.S3 lh a0, 2(rPC) # a0 <- BBBB
5 sll a0, a0, 16 # a0 <- BBBB0000
7 SET_VREG a0, a2 # vAA <- +BBBB0000

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