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Searched refs:gpr_index (Results 1 – 5 of 5) sorted by relevance

/art/runtime/arch/arm/
Dquick_entrypoints_cc_arm.cc33 uint32_t gpr_index = 1; // Index into core registers. Reserve r0 for ArtMethod*. in quick_invoke_reg_setup() local
41 core_reg_args[gpr_index++] = args[arg_index++]; in quick_invoke_reg_setup()
73 if (gpr_index == 1) { in quick_invoke_reg_setup()
75 gpr_index++; in quick_invoke_reg_setup()
77 if (gpr_index < arraysize(core_reg_args)) { in quick_invoke_reg_setup()
81 core_reg_args[gpr_index++] = args[arg_index]; in quick_invoke_reg_setup()
86 if (gpr_index < arraysize(core_reg_args)) { in quick_invoke_reg_setup()
87 core_reg_args[gpr_index++] = args[arg_index]; in quick_invoke_reg_setup()
/art/compiler/jni/quick/mips/
Dcalling_convention_mips.cc143 uint32_t gpr_index = 1; // Skip A0, it is used for ArtMethod*. in EntrySpills() local
165 if (gpr_index == 1 || gpr_index == 3) { in EntrySpills()
167 gpr_index++; in EntrySpills()
169 if (gpr_index < arraysize(kManagedCoreArgumentRegisters) - 1) { in EntrySpills()
171 MipsManagedRegister::FromCoreRegister(kManagedCoreArgumentRegisters[gpr_index++])); in EntrySpills()
172 } else if (gpr_index == arraysize(kManagedCoreArgumentRegisters) - 1) { in EntrySpills()
173 gpr_index++; in EntrySpills()
180 if (gpr_index < arraysize(kManagedCoreArgumentRegisters)) { in EntrySpills()
182 MipsManagedRegister::FromCoreRegister(kManagedCoreArgumentRegisters[gpr_index++])); in EntrySpills()
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc192 uint32_t gpr_index = 1; // R0 ~ R3. Reserve r0 for ArtMethod*. in EntrySpills() local
223 if (gpr_index < arraysize(kHFCoreArgumentRegisters) - 1) { in EntrySpills()
225 if (gpr_index == 1) { in EntrySpills()
226 gpr_index++; in EntrySpills()
231 if (gpr_index < arraysize(kHFCoreArgumentRegisters) - 1) { in EntrySpills()
233 ArmManagedRegister::FromCoreRegister(kHFCoreArgumentRegisters[gpr_index++])); in EntrySpills()
234 } else if (gpr_index == arraysize(kHFCoreArgumentRegisters) - 1) { in EntrySpills()
235 gpr_index++; in EntrySpills()
242 if (gpr_index < arraysize(kHFCoreArgumentRegisters)) { in EntrySpills()
244 ArmManagedRegister::FromCoreRegister(kHFCoreArgumentRegisters[gpr_index++])); in EntrySpills()
/art/runtime/entrypoints/quick/
Dquick_trampoline_entrypoints.cc96 static size_t GprIndexToGprOffset(uint32_t gpr_index) { in GprIndexToGprOffset() argument
97 return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); in GprIndexToGprOffset()
137 static size_t GprIndexToGprOffset(uint32_t gpr_index) { in GprIndexToGprOffset() argument
138 return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); in GprIndexToGprOffset()
183 static size_t GprIndexToGprOffset(uint32_t gpr_index) { in GprIndexToGprOffset() argument
184 return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); in GprIndexToGprOffset()
227 static size_t GprIndexToGprOffset(uint32_t gpr_index) { in GprIndexToGprOffset() argument
228 return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); in GprIndexToGprOffset()
260 static size_t GprIndexToGprOffset(uint32_t gpr_index) { in GprIndexToGprOffset() argument
261 return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); in GprIndexToGprOffset()
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/art/runtime/arch/mips/
Dquick_entrypoints_mips.S998 li $t6, 0 # t6 = gpr_index = 0 (corresponds to A2; A0 and A1 are skipped)
1249 LOAD_WORD_TO_REG a1, t8, t6, loopS # a1 = current argument, gpr_index += 16
1250 LOAD_WORD_TO_REG a2, t8, t6, loopS # a2 = current argument, gpr_index += 16
1251 LOAD_WORD_TO_REG a3, t8, t6, loopS # a3 = current argument, gpr_index += 16
1252 LOAD_WORD_TO_REG t0, t8, t6, loopS # t0 = current argument, gpr_index += 16
1253 LOAD_WORD_TO_REG t1, t8, t6, loopS # t1 = current argument, gpr_index += 16
1254 LOAD_END t6, 5*16, loopS # no more GPR args, gpr_index = 5*16
1256 LOAD_LONG_TO_REG a2, a3, t8, t6, 3*16, loopS # a2_a3 = curr_arg, gpr_index = 3*16
1257 LOAD_LONG_TO_REG a2, a3, t8, t6, 3*16, loopS # a2_a3 = curr_arg, gpr_index = 3*16
1258 LOAD_LONG_TO_REG t0, t1, t8, t6, 5*16, loopS # t0_t1 = curr_arg, gpr_index = 5*16
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