| /art/runtime/interpreter/mterp/arm64/ |
| D | header.S | 302 .macro SAVE_TWO_REGS reg1, reg2, offset
303 stp \reg1, \reg2, [sp, #(\offset)]
304 .cfi_rel_offset \reg1, (\offset)
311 .macro RESTORE_TWO_REGS reg1, reg2, offset
312 ldp \reg1, \reg2, [sp, #(\offset)]
313 .cfi_restore \reg1
320 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
321 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
323 .cfi_rel_offset \reg1, 0
330 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment
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| /art/compiler/utils/ |
| D | assembler_test.h | 193 for (auto reg1 : reg1_registers) { variable
198 (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias);
202 std::string reg1_string = (this->*GetName1)(*reg1);
248 for (auto reg1 : reg1_registers) { in RepeatTemplatedRegistersImmBits() local
254 (assembler_.get()->*f)(*reg1, *reg2, *reg3, new_imm + bias); in RepeatTemplatedRegistersImmBits()
258 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRegistersImmBits()
310 for (auto reg1 : reg1_registers) { in RepeatTemplatedImmBitsRegisters() local
315 (assembler_.get()->*f)(new_imm, *reg1, *reg2); in RepeatTemplatedImmBitsRegisters()
319 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedImmBitsRegisters()
1318 for (auto reg1 : reg1_registers) { in RepeatTemplatedRegisters() local
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| /art/runtime/arch/arm64/ |
| D | quick_entrypoints_arm64.S | 55 .macro SAVE_TWO_REGS reg1, reg2, offset
56 stp \reg1, \reg2, [sp, #(\offset)]
57 .cfi_rel_offset \reg1, (\offset)
61 .macro RESTORE_TWO_REGS reg1, reg2, offset
62 ldp \reg1, \reg2, [sp, #(\offset)]
63 .cfi_restore \reg1
67 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
68 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
70 .cfi_rel_offset \reg1, 0
74 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 650 void cmpl(CpuRegister reg0, CpuRegister reg1);
655 void cmpq(CpuRegister reg0, CpuRegister reg1);
660 void testl(CpuRegister reg1, CpuRegister reg2);
664 void testq(CpuRegister reg1, CpuRegister reg2);
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| D | assembler_x86_64.cc | 2214 void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) { in cmpl() argument
2216 EmitOptionalRex32(reg0, reg1); in cmpl()
2218 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpl()
2246 void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) { in cmpq() argument
2248 EmitRex64(reg0, reg1); in cmpq()
2250 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpq()
2294 void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) { in testl() argument
2296 EmitOptionalRex32(reg1, reg2); in testl()
2298 EmitRegisterOperand(reg1.LowBits(), reg2.LowBits()); in testl()
2336 void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) { in testq() argument
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| /art/compiler/utils/x86/ |
| D | assembler_x86.h | 606 void cmpl(Register reg0, Register reg1);
612 void testl(Register reg1, Register reg2);
614 void testl(Register reg1, const Address& address);
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 480 for (mips::Register* reg1 : regs) { in TEST_F()
484 __ Ins(*reg1, *reg2, pos, size); in TEST_F()
486 instr << "ins $" << *reg1 << ", $" << *reg2 << ", " << pos << ", " << size << "\n"; in TEST_F()
499 for (mips::Register* reg1 : regs) { in TEST_F()
503 __ Ext(*reg1, *reg2, pos, size); in TEST_F()
505 instr << "ext $" << *reg1 << ", $" << *reg2 << ", " << pos << ", " << size << "\n"; in TEST_F()
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| /art/runtime/arch/mips/ |
| D | quick_entrypoints_mips.S | 915 .macro LOAD_LONG_TO_REG reg1, reg2, next_arg, index_reg, next_index, label
916 lw $\reg1, -8($\next_arg) # next_arg points to argument after the current one (offset is 8)
932 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
934 LDu $\reg1, $\reg2, -8, $\next_arg, $\tmp # next_arg points to argument after the current one
942 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
943 LDu $\reg1, $\reg2, -8, $\next_arg, $\tmp # next_arg points to argument after the current one
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| /art/runtime/interpreter/mterp/out/ |
| D | mterp_arm64.S | 309 .macro SAVE_TWO_REGS reg1, reg2, offset
310 stp \reg1, \reg2, [sp, #(\offset)]
311 .cfi_rel_offset \reg1, (\offset)
318 .macro RESTORE_TWO_REGS reg1, reg2, offset
319 ldp \reg1, \reg2, [sp, #(\offset)]
320 .cfi_restore \reg1
327 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
328 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
330 .cfi_rel_offset \reg1, 0
337 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment
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| /art/compiler/optimizing/ |
| D | code_generator_x86_64.h | 142 void Exchange64(CpuRegister reg1, CpuRegister reg2);
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| D | code_generator_arm_vixl.cc | 4646 vixl32::Register reg1 = InputRegisterAt(rem, 0); in VisitRem() local
4656 __ Sdiv(temp, reg1, reg2); in VisitRem()
4657 __ Mls(out_reg, temp, reg2, reg1); in VisitRem()
4660 DCHECK(reg1.Is(calling_convention.GetRegisterAt(0))); in VisitRem()
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| D | code_generator_x86_64.cc | 5333 void ParallelMoveResolverX86_64::Exchange64(CpuRegister reg1, CpuRegister reg2) { in Exchange64() argument
5334 __ movq(CpuRegister(TMP), reg1); in Exchange64()
5335 __ movq(reg1, reg2); in Exchange64()
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