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Searched refs:shamt (Results 1 – 3 of 3) sorted by relevance

/art/compiler/utils/mips64/
Dassembler_mips64.cc100 int shamt, int funct) { in EmitR() argument
108 shamt << kShamtShift | in EmitR()
114 int shamt, int funct) { in EmitRsd() argument
121 shamt << kShamtShift | in EmitRsd()
127 int shamt, int funct) { in EmitRtd() argument
134 shamt << kShamtShift | in EmitRtd()
507 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll() argument
508 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00); in Sll()
511 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl() argument
512 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02); in Srl()
[all …]
Dassembler_mips64.h494 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
495 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
496 void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
497 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
502 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
503 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
504 void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
505 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
506 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
507 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
[all …]
/art/compiler/utils/mips/
Dassembler_mips.h343 void Sll(Register rd, Register rt, int shamt);
344 void Srl(Register rd, Register rt, int shamt);
345 void Rotr(Register rd, Register rt, int shamt); // R2+
346 void Sra(Register rd, Register rt, int shamt);
354 void ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp = AT);
1680 uint32_t EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);