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Searched refs:temp_reg (Results 1 – 9 of 9) sorted by relevance

/art/runtime/arch/x86/
Dquick_entrypoints_x86.S28 MACRO2(SETUP_SAVE_ALL_CALLEE_SAVES_FRAME, got_reg, temp_reg)
36 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg)), REG_VAR(temp_reg)
37 movl (REG_VAR(temp_reg)), REG_VAR(temp_reg)
39 pushl RUNTIME_SAVE_ALL_CALLEE_SAVES_METHOD_OFFSET(REG_VAR(temp_reg))
54 MACRO2(SETUP_SAVE_REFS_ONLY_FRAME, got_reg, temp_reg)
62 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg)), REG_VAR(temp_reg)
63 movl (REG_VAR(temp_reg)), REG_VAR(temp_reg)
65 pushl RUNTIME_SAVE_REFS_ONLY_METHOD_OFFSET(REG_VAR(temp_reg))
82 MACRO2(SETUP_SAVE_REFS_ONLY_FRAME_PRESERVE_GOT_REG, got_reg, temp_reg)
92 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg)), REG_VAR(temp_reg)
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/art/compiler/trampolines/
Dtrampoline_compiler.cc72 const vixl::aarch32::Register temp_reg = temps.Acquire(); in CreateTrampoline() local
76 ___ Ldr(temp_reg, MemOperand(r0, JNIEnvExt::SelfOffset(4).Int32Value())); in CreateTrampoline()
77 ___ Ldr(pc, MemOperand(temp_reg, offset.Int32Value())); in CreateTrampoline()
/art/compiler/optimizing/
Dintrinsics_arm_vixl.cc1007 const vixl32::Register temp_reg = temps.Acquire(); in GenUnsafeGet() local
1008 __ Add(temp_reg, base, offset); in GenUnsafeGet()
1009 __ Ldrexd(trg_lo, trg_hi, MemOperand(temp_reg)); in GenUnsafeGet()
1175 const vixl32::Register temp_reg = temps.Acquire(); in GenUnsafePut() local
1177 __ Add(temp_reg, base, offset); in GenUnsafePut()
1180 __ Ldrexd(temp_lo, temp_hi, MemOperand(temp_reg)); in GenUnsafePut()
1181 __ Strexd(temp_lo, value_lo, value_hi, MemOperand(temp_reg)); in GenUnsafePut()
1605 vixl32::Register temp_reg = temps.Acquire(); in GenerateStringCompareToLoop() local
1606 __ Ldr(temp_reg, MemOperand(str, temp1)); in GenerateStringCompareToLoop()
1608 __ Cmp(temp_reg, temp2); in GenerateStringCompareToLoop()
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Dcode_generator_x86.cc4115 Register temp_reg = locations->GetTemp(0).AsRegister<Register>(); in VisitRor() local
4119 __ movl(temp_reg, first_reg_hi); in VisitRor()
4121 __ shrd(first_reg_lo, temp_reg, second_reg); in VisitRor()
4122 __ movl(temp_reg, first_reg_hi); in VisitRor()
4125 __ cmovl(kNotEqual, first_reg_lo, temp_reg); in VisitRor()
4134 __ movl(temp_reg, first_reg_lo); in VisitRor()
4136 __ movl(first_reg_hi, temp_reg); in VisitRor()
4142 __ movl(temp_reg, first_reg_lo); in VisitRor()
4148 __ shrd(first_reg_hi, temp_reg, imm); in VisitRor()
4152 __ movl(temp_reg, first_reg_lo); in VisitRor()
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Dcode_generator_mips64.cc5363 GpuRegister temp_reg = temp.AsRegister<GpuRegister>(); in GenerateReferenceLoadWithBakerReadBarrier() local
5367 __ LoadFromOffset(kLoadWord, temp_reg, obj, monitor_offset); in GenerateReferenceLoadWithBakerReadBarrier()
5418 temp_reg); in GenerateReferenceLoadWithBakerReadBarrier()
5432 __ Sll(temp_reg, temp_reg, 31 - LockWord::kReadBarrierStateShift); in GenerateReferenceLoadWithBakerReadBarrier()
5433 __ Bltzc(temp_reg, slow_path->GetEntryLabel()); in GenerateReferenceLoadWithBakerReadBarrier()
7108 GpuRegister temp_reg = TMP; in GenPackedSwitchWithCompares() local
7109 __ Addiu32(temp_reg, value_reg, -lower_bound); in GenPackedSwitchWithCompares()
7113 __ Bltzc(temp_reg, codegen_->GetLabelOf(default_block)); in GenPackedSwitchWithCompares()
7117 __ Beqzc(temp_reg, codegen_->GetLabelOf(successors[0])); in GenPackedSwitchWithCompares()
7120 __ Addiu(temp_reg, temp_reg, -2); in GenPackedSwitchWithCompares()
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Dcode_generator_mips.cc7246 Register temp_reg = temp.AsRegister<Register>(); in GenerateReferenceLoadWithBakerReadBarrier() local
7250 __ LoadFromOffset(kLoadWord, temp_reg, obj, monitor_offset); in GenerateReferenceLoadWithBakerReadBarrier()
7304 temp_reg); in GenerateReferenceLoadWithBakerReadBarrier()
7318 __ Sll(temp_reg, temp_reg, 31 - LockWord::kReadBarrierStateShift); in GenerateReferenceLoadWithBakerReadBarrier()
7319 __ Bltz(temp_reg, slow_path->GetEntryLabel()); in GenerateReferenceLoadWithBakerReadBarrier()
7830 Register temp_reg = temp.AsRegister<Register>(); in GenerateStaticOrDirectCall() local
7832 __ Addiu(temp_reg, TMP, /* placeholder */ 0x5678, &info_low->label); in GenerateStaticOrDirectCall()
7843 Register temp_reg = temp.AsRegister<Register>(); in GenerateStaticOrDirectCall() local
7845 __ Lw(temp_reg, TMP, /* placeholder */ 0x5678, &info_low->label); in GenerateStaticOrDirectCall()
9353 Register temp_reg = TMP; in GenPackedSwitchWithCompares() local
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Dcode_generator_arm_vixl.cc8641 vixl32::Register temp_reg = RegisterFrom(temp); in GenerateReferenceLoadWithBakerReadBarrier() local
8647 instruction, ref, obj, offset, index, scale_factor, needs_null_check, temp_reg); in GenerateReferenceLoadWithBakerReadBarrier()
8688 vixl32::Register temp_reg = RegisterFrom(temp); in UpdateReferenceFieldWithBakerReadBarrier() local
8701 temp_reg, in UpdateReferenceFieldWithBakerReadBarrier()
8897 vixl32::Register temp_reg = RegisterFrom(temp); in GenerateStaticOrDirectCall() local
8898 EmitMovwMovtPlaceholder(labels, temp_reg); in GenerateStaticOrDirectCall()
8907 vixl32::Register temp_reg = RegisterFrom(temp); in GenerateStaticOrDirectCall() local
8908 EmitMovwMovtPlaceholder(labels, temp_reg); in GenerateStaticOrDirectCall()
8909 GetAssembler()->LoadFromOffset(kLoadWord, temp_reg, temp_reg, /* offset*/ 0); in GenerateStaticOrDirectCall()
9201 vixl32::Register temp_reg = temps.Acquire(); in VisitPackedSwitch() local
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Dcode_generator_x86_64.cc6794 CpuRegister temp_reg = locations->GetTemp(0).AsRegister<CpuRegister>(); in VisitPackedSwitch() local
6847 __ leal(temp_reg, Address(value_reg_in, -lower_bound)); in VisitPackedSwitch()
6848 value_reg_out = temp_reg.AsRegister(); in VisitPackedSwitch()
6861 __ movsxd(temp_reg, Address(base_reg, value_reg, TIMES_4, 0)); in VisitPackedSwitch()
6864 __ addq(temp_reg, base_reg); in VisitPackedSwitch()
6867 __ jmp(temp_reg); in VisitPackedSwitch()
Dcode_generator_arm64.cc5858 Register temp_reg = RegisterFrom(maybe_temp, type); in GenerateReferenceLoadOneRegister() local
5859 __ Mov(temp_reg, out_reg); in GenerateReferenceLoadOneRegister()