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/external/clang/test/CodeGenCXX/
Dglobal-block-literal-helpers.cpp5 typedef void (^BL)(); typedef
6 int func(BL, BL, BL);
11 BL ArrBlock [] = { ^{}, ^{}, ^{} };
22 BL field = ^{};
/external/clang/test/CodeGenOpenCL/
Dcl20-device-side-enqueue.cl24 …// CHECK: [[BL:%[0-9]+]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32{{.*}}, …
25 // CHECK: [[BL_I8:%[0-9]+]] = bitcast void ()* [[BL]] to i8*
35 …// CHECK: [[BL:%[0-9]+]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32{{.*}}, …
36 // CHECK: [[BL_I8:%[0-9]+]] = bitcast void ()* [[BL]] to i8*
94 // CHECK: [[BL:%[0-9]+]] = load void ()*, void ()** %block_A
95 // CHECK: [[BL_I8:%[0-9]+]] = bitcast void ()* [[BL]] to i8*
98 // CHECK: [[BL:%[0-9]+]] = load void (i8 addrspace(2)*)*, void (i8 addrspace(2)*)** %block_B
99 // CHECK: [[BL_I8:%[0-9]+]] = bitcast void (i8 addrspace(2)*)* [[BL]] to i8*
102 // CHECK: [[BL:%[0-9]+]] = load void ()*, void ()** %block_A
103 // CHECK: [[BL_I8:%[0-9]+]] = bitcast void ()* [[BL]] to i8*
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
9 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
28 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
9 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
28 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Daddsub-i128.ll6 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
12 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
25 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
31 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/MIR/AArch64/
Dmachine-dead-copy.mir22 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
37 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
52 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
68 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
/external/clang/test/Rewriter/
Dobjc-modern-implicit-cast.mm5 typedef void(^BL)(void);
11 BL return_block(id obj) {
/external/tremolo/Tremolo/
Ddpen.s53 BL oggpack_adv @ oggpack_adv(b,1) /* Force eop */
78 BL oggpack_look
111 BL oggpack_adv @ oggpack_adv(b, i+1);
134 BL oggpack_adv @ oggpack_adv(b, i)
168 BL oggpack_adv @ oggpack_adv(b, i+1);
192 BL oggpack_adv @ oggpack_adv(b, i)
226 BL oggpack_adv @ oggpack_adv(b, i+1);
241 BL decode_packed_entry_number
245 BL oggpack_eop
426 BL decode_map
/external/skia/samplecode/
DSamplePatch.cpp86 const int BL = BR + nu; in eval_sheet() local
96 SkScalar x0 = UV * edge[TL].fX + uV * edge[TR].fX + Uv * edge[BL].fX + uv * edge[BR].fX; in eval_sheet()
97 SkScalar y0 = UV * edge[TL].fY + uV * edge[TR].fY + Uv * edge[BL].fY + uv * edge[BR].fY; in eval_sheet()
100 v * edge[BR+nu-iu].fX + (1 - u) * edge[BL+nv-iv].fX - x0; in eval_sheet()
102 v * edge[BR+nu-iu].fY + (1 - u) * edge[BL+nv-iv].fY - y0; in eval_sheet()
/external/skqp/samplecode/
DSamplePatch.cpp86 const int BL = BR + nu; in eval_sheet() local
96 SkScalar x0 = UV * edge[TL].fX + uV * edge[TR].fX + Uv * edge[BL].fX + uv * edge[BR].fX; in eval_sheet()
97 SkScalar y0 = UV * edge[TL].fY + uV * edge[TR].fY + Uv * edge[BL].fY + uv * edge[BR].fY; in eval_sheet()
100 v * edge[BR+nu-iu].fX + (1 - u) * edge[BL+nv-iv].fX - x0; in eval_sheet()
102 v * edge[BR+nu-iu].fY + (1 - u) * edge[BL+nv-iv].fY - y0; in eval_sheet()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, in initLLVMToSEHAndCVRegMapping()
299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
312 return X86::BL; in getX86SubSuperRegisterOrZero()
348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/external/autotest/client/site_tests/firmware_TouchMTB/
Dtest_conf.py327 (GV.TL, GV.TR, GV.BL, GV.BR, GV.TS, GV.BS, GV.LS, GV.RS,
335 GV.BL: ('bottom left corner',),
593 variations=(GV.TL, GV.TR, GV.BL, GV.BR, GV.TS, GV.BS, GV.LS, GV.RS,
599 GV.BL: ('bottom left corner',),
634 variations=(GV.CENTER, GV.BL, GV.BS, GV.BR),
639 GV.BL: ('bottom left corner',),
885 GV.BL: ('bottom left corner',),
Dfirmware_constants.py94 GV.BL = 'bottom_left'
102 GV.GESTURE_LOCATIONS = [GV.TL, GV.TR, GV.BL, GV.BR, GV.TS, GV.BS, GV.LS, GV.RS,
/external/llvm/test/CodeGen/Hexagon/
Dsube.ll12 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 %tmp67 = zext i64 %BL to i128
Dadde.ll17 define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
23 %tmp67 = zext i64 %BL to i128
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dbr1.ll26 ; CHECK: bgtz $[[REG2]], $BB[[BL:[0-9]+_[0-9]+]]
30 ; CHECK: $BB[[BL]]:
/external/elfutils/libdwfl/
Dlink_map.c715 #define AUXV_SCAN(NN, BL) do \ in dwfl_link_map_report() argument
721 uint##NN##_t val = BL##NN (READ_AUXV##NN (&av[i].a_un.a_val)); \ in dwfl_link_map_report()
722 if (type == BL##NN (AT_ENTRY)) \ in dwfl_link_map_report()
724 else if (type == BL##NN (AT_PHDR)) \ in dwfl_link_map_report()
726 else if (type == BL##NN (AT_PHNUM)) \ in dwfl_link_map_report()
728 else if (type == BL##NN (AT_PHENT)) \ in dwfl_link_map_report()
730 else if (type == BL##NN (AT_PAGESZ)) \ in dwfl_link_map_report()
/external/llvm/test/CodeGen/Thumb2/
Dtpsoft.ll35 ;;; BL __aeabi_read_tp is ---+
39 ;;; BL __aeabi_read_tp is ---+
/external/libxaac/decoder/armv7/
Dixheaacd_cos_sin_mod.s249 BL ixheaacd_sbr_imdct_using_fft
271 BL ixheaacd_sbr_imdct_using_fft
299 BL ixheaacd_sbr_imdct_using_fft
321 BL ixheaacd_sbr_imdct_using_fft
/external/llvm/test/CodeGen/MIR/ARM/
Dcfi-same-value.mir53 BL $__morestack, implicit-def %lr, implicit %sp
76 …BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, …
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp675 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
687 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
688 return X86::BL; in getX86SubSuperRegister()
724 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
760 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
796 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
/external/clang/test/Preprocessor/
Dmacro_paste_bad.c29 #define XX BL ## ARG
/external/icu/icu4c/source/data/region/
Den_GB.txt6 BL{"St Barthélemy"}
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dshift-coalesce.ll4 ; RUN: not grep {mov CL, BL}
/external/llvm/test/CodeGen/ARM/
Ddomain-conv-vmovs.ll104 ; + Make sure s1 is live before the BL
105 ; + Make sure s1 is clobbered by the BL

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