| /external/llvm/test/MC/ARM/ |
| D | thumb-not-mclass.s | 12 @ BLX (immediate)
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| D | basic-thumb-instructions.s | 151 @ BL/BLX
178 @ BL/BLX (immediate)
194 @ BLX (register)
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| D | basic-arm-instructions.s | 603 @ BL/BLX (immediate)
629 @ BLX (register)
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| D | v8_IT_manual.s | 309 @ BLX, encoding T1
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 130 @ BL/BLX
157 @ BL/BLX (immediate)
169 @ BLX (register)
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| D | basic-arm-instructions.s | 361 @ BL/BLX (immediate)
378 @ BLX (register)
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 83 #define BLX 0xe12fff30 macro
263 return push_inst(compiler, BLX | RM(TMP_REG1)); in emit_blx()
486 inst[1] = BLX | RM(TMP_REG1); in inline_set_jump_addr()
2322 return push_inst(compiler, BLX | RM(TMP_REG3)); in sljit_emit_fast_return()
2435 …PTR_FAIL_IF(push_inst(compiler, (((type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)) & ~COND_MASK) | … in sljit_emit_jump()
2452 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(src)); in sljit_emit_ijump()
2456 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG2)); in sljit_emit_ijump()
2472 FAIL_IF(push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1))); in sljit_emit_ijump()
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| D | sljitNativeARM_T2_32.c | 108 #define BLX 0x4780 macro
1836 return push_inst16(compiler, BLX | RN3(TMP_REG3)); in sljit_emit_fast_return()
1941 PTR_FAIL_IF(push_inst16(compiler, BLX | RN3(TMP_REG1))); in sljit_emit_jump()
1958 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(src)); in sljit_emit_ijump()
1962 return push_inst16(compiler, BLX | RN3(TMP_REG1)); in sljit_emit_ijump()
1972 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(TMP_REG1)); in sljit_emit_ijump()
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| /external/v8/src/arm/ |
| D | constants-arm.h | 165 BLX = 3 << 4, enumerator
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| D | disasm-arm.cc | 897 case BLX: in DecodeType01()
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| D | assembler-arm.cc | 521 B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;
1480 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code()); in blx()
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| D | simulator-arm.cc | 2394 case BLX: { in DecodeType01()
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 95 # BLX (register)
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| D | basic-arm-instructions.txt | 321 # BLX (register)
330 # BLX (immediate)
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 108 # BLX (register)
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| D | basic-arm-instructions.txt | 354 # BLX (register)
363 # BLX (immediate)
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| /external/capstone/ |
| D | ChangeLog | 197 - BLX instruction modifies PC & LR registers.
279 - BL & BLX do not read SP, but PC register.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 141 // Target for BLX *from* thumb mode.
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| D | ARMFastISel.cpp | 2162 return isThumb2 ? ARM::tBLXr : ARM::BLX; in ARMSelectCallOp()
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| D | ARMInstrInfo.td | 447 // Target for BLX *from* ARM mode.
2232 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2314 // BLX (immediate)
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 1872 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1924 (BLX GPR:$func)>,
1987 // BLX (immediate)
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 74 414582U, // BLX
2867 0U, // BLX
6095 // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC...
6238 // BKPT, BL, BLX, BLXi, BX, CPS1p, HLT, RFEDA, RFEDB, RFEIA, RFEIB, SRSDA...
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| D | ARMGenInstrInfo.inc | 3251 …<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo32,0,nullptr }, // Inst #57 = BLX
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| D | ARMGenDisassemblerTables.inc | 574 /* 2255 */ MCD_OPC_Decode, 57, 31, // Opcode: BLX
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| /external/valgrind/ |
| D | NEWS | 2340 277694 ARM: BLX LR instruction broken in ARM mode
|