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Searched refs:CARRY (Results 1 – 17 of 17) sorted by relevance

/external/valgrind/none/tests/s390x/
Dadd.h6 #define ADD_REG_MEM(insn, s1, s2, CARRY) \ argument
10 asm volatile( "lghi 0," #CARRY "\n" \
18 printf(#insn " " #CARRY " + %16.16lX + %16.16lX = %16.16lX (cc=%d)\n", s1, s2, tmp, cc); \
21 #define ADD_REG_REG(insn, s1, s2, CARRY) \ argument
25 asm volatile( "lghi 0," #CARRY "\n" \
33 printf(#insn " " #CARRY " + %16.16lX + %16.16lX = %16.16lX (cc=%d)\n", s1, s2, tmp, cc); \
36 #define ADD_REG_IMM(insn, s1, s2, CARRY) \ argument
40 asm volatile( "lghi 0," #CARRY "\n" \
48 …printf(#insn " " #CARRY " + %16.16lX + %16.16lX = %16.16lX (cc=%d)\n", s1, (unsigned long) s2, tmp…
51 #define ADD_MEM_IMM(insn, s1, s2, CARRY) \ argument
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/external/llvm/test/CodeGen/AArch64/
Dmadd-lohi.ll6 ; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
12 ; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
Dmul-lohi.ll7 ; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
13 ; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrInfo.td349 let Defs = [CARRY] in {
352 let Uses = [CARRY] in {
357 let Uses = [CARRY] in {
368 let Defs = [CARRY] in {
371 let Uses = [CARRY] in {
376 let Uses = [CARRY] in {
420 let Defs = [CARRY] in {
424 let Uses = [CARRY] in {
430 let Uses = [CARRY] in {
455 let Defs = [CARRY] in {
[all …]
DMBlazeInstrFSL.td127 let Defs = [CARRY] in {
166 let Defs = [CARRY] in {
197 let Defs = [CARRY] in {
220 let Defs = [CARRY] in {
DMBlazeRegisterInfo.td105 def CARRY : MBlazeSPRReg<0x0000, "rmsr[c]">;
146 def CRC : RegisterClass<"MBlaze", [i32], 32, (add CARRY)> {
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstr64Bit.td73 CR0,CR1,CR5,CR6,CR7,CARRY] in {
99 CR0,CR1,CR5,CR6,CR7,CARRY] in {
330 let Defs = [CARRY] in {
346 let Defs = [CARRY] in {
361 let Uses = [CARRY], Defs = [CARRY] in {
405 let Defs = [CARRY] in {
429 let Defs = [CARRY] in {
DPPCInstrInfo.td440 CR0,CR1,CR5,CR6,CR7,CARRY] in {
465 CR0,CR1,CR5,CR6,CR7,CARRY] in {
856 let Defs = [CARRY] in {
875 let Defs = [CARRY] in {
952 let Defs = [CARRY] in {
960 let Defs = [CARRY] in {
1163 let Defs = [CARRY] in {
1189 let Defs = [CARRY] in {
1198 let Uses = [CARRY], Defs = [CARRY] in {
DPPCRegisterInfo.td264 def CARRY: SPR<1, "ca">;
324 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
/external/llvm/lib/Target/SystemZ/
DREADME.txt60 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
360 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
DPPCInstrInfo.td818 let Defs = [CARRY] in
822 let Defs = [CARRY, CR0] in
833 let Defs = [CARRY] in
837 let Defs = [CARRY, CR0] in
893 let Defs = [CARRY] in
897 let Defs = [CARRY, CR0] in
922 let Defs = [CARRY] in
926 let Defs = [CARRY, CR0] in
979 let Defs = [CARRY] in
983 let Defs = [CARRY, CR0] in
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DPPCInstr64Bit.td502 let Defs = [CARRY] in
513 let Defs = [CARRY] in {
528 let Uses = [CARRY] in {
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h262 CARRY, enumerator
DAMDGPUInstrInfo.td135 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
DAMDGPUISelLowering.cpp2833 NODE_NAME_CASE(CARRY) in getTargetNodeName()
2933 case AMDGPUISD::CARRY: in computeKnownBitsForTargetNode()
2980 case AMDGPUISD::CARRY: in ComputeNumSignBitsForTargetNode()
DR600ISelLowering.cpp622 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()