| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenExtract.cpp | 87 ConstantInt *CSL = 0, *CSR = 0, *CM = 0; in INITIALIZE_PASS_DEPENDENCY() local
94 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
101 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
108 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in INITIALIZE_PASS_DEPENDENCY()
118 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
125 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
132 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
139 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
152 uint32_t SR = CSR->getZExtValue(); in INITIALIZE_PASS_DEPENDENCY()
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| D | HexagonInstrInfoV3.td | 27 class T_Call<bit CSR, string ExtStr>
33 let Defs = !if (CSR, VolatileV3.Regs, []);
43 class T_CallPred<bit CSR, bit IfTrue, string ExtStr>
52 let Defs = !if (CSR, VolatileV3.Regs, []);
61 multiclass T_Calls<bit CSR, string ExtStr> {
62 def NAME : T_Call<CSR, ExtStr>;
63 def t : T_CallPred<CSR, 1, ExtStr>;
64 def f : T_CallPred<CSR, 0, ExtStr>;
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| D | HexagonVLIWPacketizer.cpp | 319 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in doesModifyCalleeSavedReg() local
320 if (MI->modifiesRegister(*CSR, TRI)) in doesModifyCalleeSavedReg()
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| /external/llvm/lib/CodeGen/ |
| D | LivePhysRegs.cpp | 154 for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in addPristines() local
155 LiveRegs.addReg(*CSR); in addPristines()
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| D | RegisterClassInfo.cpp | 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction() local
52 if (Update || CSR != CalleeSaved) { in runOnMachineFunction()
57 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) in runOnMachineFunction()
62 CalleeSaved = CSR; in runOnMachineFunction()
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| D | MachineFunction.cpp | 662 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in getPristineRegs() local
663 BV.set(*CSR); in getPristineRegs()
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| D | RegAllocPBQP.cpp | 554 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); in isACalleeSavedRegister() local
555 for (unsigned i = 0; CSR[i] != 0; ++i) in isACalleeSavedRegister()
556 if (TRI.regsOverlap(reg, CSR[i])) in isACalleeSavedRegister()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 42 const unsigned *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction() local
43 if (Update || CSR != CalleeSaved) { in runOnMachineFunction()
48 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) in runOnMachineFunction()
54 CalleeSaved = CSR; in runOnMachineFunction()
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| D | MachineFunction.cpp | 467 for (const unsigned *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR) in getPristineRegs() local
468 BV.set(*CSR); in getPristineRegs()
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| D | RegAllocGreedy.cpp | 637 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) in tryEvict() local
638 if (!MRI->isPhysRegUsed(CSR)) { in tryEvict()
640 << PrintReg(CSR, TRI) << '\n'); in tryEvict()
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| /external/llvm/lib/Target/X86/ |
| D | X86MachineFunctionInfo.cpp | 23 for (const MCPhysReg *CSR = in setRestoreBasePointer() local
25 unsigned Reg = *CSR; in setRestoreBasePointer()
26 ++CSR) in setRestoreBasePointer()
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | str_pre-2.ll | 4 ; The greedy register allocator uses a single CSR here, invalidating the test.
|
| D | 2011-08-25-ldmia_ret.ll | 44 ; Fold the CSR+return into a pop
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| /external/llvm/lib/Target/BPF/ |
| D | BPFCallingConv.td | 29 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiCallingConv.td | 50 def CSR: CalleeSavedRegs<(add)>;
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| /external/llvm/test/CodeGen/X86/ |
| D | catchpad-realign-savexmm.ll | 4 ; CSR save.
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| D | x86-shrink-wrapping.ll | 79 ; Make sure we save the CSR used in the inline asm: rbx.
156 ; Make sure we save the CSR used in the inline asm: rbx.
205 ; Make sure we save the CSR used in the inline asm: rbx.
283 ; Make sure we save the CSR used in the inline asm: rbx.
367 ; Make sure we save the CSR used in the inline asm: rbx.
734 ; In this case, the RegMask does not touch a CSR so we are good to go!
777 ; Clobber a CSR so that we check something on the regmask
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| D | x86-win64-shrink-wrapping.ll | 57 ; Make sure we save the CSR used in the inline asm: rbx.
|
| /external/llvm/test/CodeGen/ARM/ |
| D | arm-shrink-wrapping.ll | 91 ; Make sure we save the CSR used in the inline asm: r4.
164 ; Make sure we save the CSR used in the inline asm: r4.
215 ; Make sure we save the CSR used in the inline asm: r4.
294 ; Make sure we save the CSR used in the inline asm: r4.
379 ; Make sure we save the CSR used in the inline asm: r4.
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| D | 2011-08-25-ldmia_ret.ll | 44 ; Fold the CSR+return into a pop
|
| /external/llvm/test/CodeGen/Thumb/ |
| D | thumb-shrink-wrapping.ll | 126 ; Make sure we save the CSR used in the inline asm: r4.
201 ; Make sure we save the CSR used in the inline asm: r4.
252 ; Make sure we save the CSR used in the inline asm: r4.
336 ; Make sure we save the CSR used in the inline asm: r4.
426 ; Make sure we save the CSR used in the inline asm: r4.
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc-shrink-wrapping.ll | 376 ; Make sure we save the CSR used in the inline asm: r14
633 ; CHECKXX: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
636 ; CHECKXX: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
639 ; CHECK-NOT: {{[a-z]+}} [[CSR]]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 121 // R9 is used to return SwiftError; remove it from CSR.
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| /external/llvm/include/llvm/ADT/ |
| D | Triple.h | 134 CSR, enumerator
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/ |
| D | Triple.h | 138 CSR, enumerator
|