| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 101 void HexagonInstrInfo::anchor() {} in anchor()
103 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) in HexagonInstrInfo() function in HexagonInstrInfo
234 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
301 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
373 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
544 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { in RemoveBranch()
564 unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB, in InsertBranch()
665 bool HexagonInstrInfo::analyzeLoop(MachineLoop &L, in analyzeLoop()
683 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB, in reduceLoopCount()
740 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, in isProfitableToIfCvt()
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| D | HexagonFrameLowering.h | 19 class HexagonInstrInfo; variable
86 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
102 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
105 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
108 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
111 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
114 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
117 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
120 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
123 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| D | HexagonBitTracker.h | 17 class HexagonInstrInfo; variable
27 const HexagonInstrInfo &tii, MachineFunction &mf);
38 const HexagonInstrInfo &TII;
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| D | HexagonSubtarget.h | 52 HexagonInstrInfo InstrInfo;
68 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
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| D | HexagonFixupHwLoops.cpp | 113 const HexagonInstrInfo *HII = in fixupLoopInstrs()
114 static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in fixupLoopInstrs()
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| D | HexagonNewValueJump.cpp | 67 const HexagonInstrInfo *QII;
112 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, in INITIALIZE_PASS_DEPENDENCY()
214 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, in canCompareBeNewValueJump()
402 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| D | Hexagon.td | 251 include "HexagonInstrInfo.td"
255 def HexagonInstrInfo : InstrInfo;
290 let InstructionSet = HexagonInstrInfo;
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| D | HexagonPeephole.cpp | 84 const HexagonInstrInfo *QII;
118 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| D | HexagonBitSimplify.cpp | 179 uint16_t Begin, const HexagonInstrInfo &HII);
575 BitVector &Bits, uint16_t Begin, const HexagonInstrInfo &HII) { in getUsedBits()
913 const HexagonInstrInfo &HII;
1001 RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii, in RedundantInstrElimination()
1015 const HexagonInstrInfo &HII;
1316 ConstGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in ConstGeneration()
1326 const HexagonInstrInfo &HII;
1459 CopyGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in CopyGeneration()
1467 const HexagonInstrInfo &HII;
1661 BitSimplification(BitTracker &bt, const HexagonInstrInfo &hii, in BitSimplification()
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| D | HexagonInstrInfo.h | 31 class HexagonInstrInfo : public HexagonGenInstrInfo {
36 explicit HexagonInstrInfo(HexagonSubtarget &ST);
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| D | HexagonVLIWPacketizer.cpp | 88 const HexagonInstrInfo *HII;
446 const HexagonInstrInfo *HII) { in getPredicateSense()
455 const HexagonInstrInfo *HII) { in getPostIncrementOperand()
827 const HexagonInstrInfo *QII) { in getPredicatedRegister()
979 const HexagonInstrInfo &HII) { in cannotCoexistAsymm()
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| D | HexagonFrameLowering.cpp | 1377 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandCopy()
1399 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandStoreInt()
1431 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandLoadInt()
1462 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandStoreVecPred()
1503 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandLoadVecPred()
1541 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandStoreVec2()
1595 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandLoadVec2()
1646 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandStoreVec()
1684 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { in expandLoadVec()
2181 const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const { in expandAlloca()
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| D | CMakeLists.txt | 34 HexagonInstrInfo.cpp
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| D | HexagonVLIWPacketizer.h | 40 const HexagonInstrInfo *HII;
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| D | HexagonBranchRelaxation.cpp | 57 const HexagonInstrInfo *HII;
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| D | HexagonCopyToCombine.cpp | 65 const HexagonInstrInfo *TII;
131 static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII, in isCombinableInstType()
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| D | HexagonRDFOpt.cpp | 206 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
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| D | HexagonGenMux.cpp | 58 const HexagonInstrInfo *HII;
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| D | HexagonExpandCondsets.cpp | 205 const HexagonInstrInfo *HII;
1253 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| D | HexagonStoreWidening.cpp | 54 const HexagonInstrInfo *TII;
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| D | HexagonGenPredicate.cpp | 82 const HexagonInstrInfo *TII;
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| D | HexagonScheduleV60.td | 33 // corresponding methods to the class HexagonInstrInfo.
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| D | HexagonOptAddrMode.cpp | 69 const HexagonInstrInfo *HII;
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | tail-dup-subreg-abort.ll | 6 ; This could lead to HexagonInstrInfo::copyPhysReg aborting on an unhandled
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| D | circ_ldd_bug.ll | 7 ; UNREACHABLE executed at llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:615!
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