Searched refs:ImpDef (Results 1 – 9 of 9) sorted by relevance
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCChecker.cpp | 87 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init() local 88 for (; *ImpDef; ++ImpDef) { in init() 89 unsigned R = *ImpDef; in init()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | ScheduleDAGFast.cpp | 428 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() local 429 if (Reg == *ImpDef) in getPhysicalRegisterVT()
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D | ScheduleDAGRRList.cpp | 1030 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() local 1031 if (Reg == *ImpDef) in getPhysicalRegisterVT() 2644 for (const unsigned *ImpDef = ImpDefs; *ImpDef; ++ImpDef) { in canClobberReachingPhysRegUse() local 2648 if (TRI->regsOverlap(*ImpDef, PI->getReg()) && in canClobberReachingPhysRegUse()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | ScheduleDAGFast.cpp | 443 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() local 444 if (Reg == *ImpDef) in getPhysicalRegisterVT()
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D | ScheduleDAGRRList.cpp | 1199 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() local 1200 if (Reg == *ImpDef) in getPhysicalRegisterVT() 2715 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef) in canClobberReachingPhysRegUse() local 2719 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
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/external/llvm/lib/CodeGen/ |
D | RenameIndependentSubregs.cpp | 321 MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos, in computeMainRangesFixFlags() local 323 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags()
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelDAGToDAG.cpp | 349 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in Select() local 352 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); in Select()
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/external/llvm/lib/Target/ARM/ |
D | ARMLoadStoreOptimizer.cpp | 911 for (unsigned ImpDef : ImpDefs) in MergeOpsUpdate() local 912 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 766 SDValue ImpDef = SDValue( in Widen() local 769 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg); in Widen()
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