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Searched refs:IsUint32 (Results 1 – 25 of 59) sorted by relevance

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/external/vixl/src/aarch64/
Dcpu-aarch64.cc68 VIXL_ASSERT(IsUint32(cache_type_register)); in GetCacheType()
Dmacro-assembler-aarch64.cc417 VIXL_ASSERT(IsUint32(imm) || IsInt32(imm) || rd.Is64Bits()); in MoveImmediateHelper()
829 VIXL_ASSERT(rd.Is64Bits() || IsUint32(immediate)); in LogicalMacro()
971 VIXL_ASSERT(IsUint32(imm)); in Movi32bitHelper()
/external/vixl/src/aarch32/
Doperands-aarch32.h143 VIXL_ASSERT(IsInt32(immediate) || IsUint32(immediate)); in From()
150 VIXL_ASSERT(IsUint32(address_as_integral)); in From()
/external/vixl/test/aarch32/
Dtest-simulator-rd-rn-rm-a32.cc492 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-rd-rn-rm-t32.cc492 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-operand-imm12-t32.cc925 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-const-a32.cc485 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-imm16-t32.cc438 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-const-t32.cc600 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-a32.cc521 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc584 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-ror-amount-t32.cc584 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-t32.cc521 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-q-a32.cc421 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-q-t32.cc421 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-sel-t32.cc414 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rdlow-rnlow-rmlow-t32.cc902 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-sel-a32.cc414 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-ge-a32.cc437 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-ge-t32.cc437 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc878 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc878 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc888 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc888 VIXL_ASSERT(IsUint32(input_stride)); in TestHelper()
/external/vixl/test/aarch32/config/
Dtemplate-simulator-aarch32.cc.in193 VIXL_ASSERT(IsUint32(input_stride));

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