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Searched refs:MI (Results 1 – 25 of 1182) sorted by relevance

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/external/capstone/arch/X86/
DX86IntelInstPrinter.c48 static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
49 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
52 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
54 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
57 MI->csh->doing_mem = status; in set_mem_access()
60 MI->flat_insn->detail->x86.op_count++; in set_mem_access()
64 static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) in printopaquemem() argument
68 switch(MI->csh->mode) { in printopaquemem()
70 if (MI->flat_insn->id == X86_INS_LJMP || MI->flat_insn->id == X86_INS_LCALL) in printopaquemem()
71 MI->x86opsize = 4; in printopaquemem()
[all …]
DX86ATTInstPrinter.c49 static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
50 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
53 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
55 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
58 MI->csh->doing_mem = status; in set_mem_access()
61 MI->flat_insn->detail->x86.op_count++; in set_mem_access()
64 static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) in printopaquemem() argument
66 switch(MI->csh->mode) { in printopaquemem()
68 MI->x86opsize = 2; in printopaquemem()
71 MI->x86opsize = 4; in printopaquemem()
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/external/capstone/arch/ARM/
DARMInstPrinter.c40 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
41 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
42 static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
43 static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
45 static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
46 static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
47 static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
48 static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
49 static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
50 static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
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/external/capstone/arch/Sparc/
DSparcGenAsmWriter.inc18 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
828 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
845 printOperand(MI, 1, O);
849 printOperand(MI, 0, O);
853 printCCOperand(MI, 1, O);
857 printMemOperand(MI, 0, O, NULL);
862 printCCOperand(MI, 3, O);
866 printGetPCX(MI, 0, O);
871 printMemOperand(MI, 1, O, NULL);
875 printMemOperand(MI, 1, O, "arith");
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DSparcInstPrinter.c42 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
43 static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
44 static void printOperand(MCInst *MI, int opNum, SStream *O);
46 static void Sparc_add_hint(MCInst *MI, unsigned int hint) in Sparc_add_hint() argument
48 if (MI->csh->detail) { in Sparc_add_hint()
49 MI->flat_insn->detail->sparc.hint = hint; in Sparc_add_hint()
53 static void Sparc_add_reg(MCInst *MI, unsigned int reg) in Sparc_add_reg() argument
55 if (MI->csh->detail) { in Sparc_add_reg()
56 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; in Sparc_add_reg()
57 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; in Sparc_add_reg()
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/external/capstone/arch/PowerPC/
DPPCInstPrinter.c36 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
37 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
38 static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
39 static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
40 static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info);
41 static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
44 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
46 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
49 MI->csh->doing_mem = status; in set_mem_access()
52 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM; in set_mem_access()
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/external/capstone/arch/AArch64/
DAArch64InstPrinter.c42 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
43 static bool printSysAlias(MCInst *MI, SStream *O);
44 static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
45 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
46 static void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
48 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
50 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
53 MI->csh->doing_mem = status; in set_mem_access()
56 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; in set_mem_access()
57 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_… in set_mem_access()
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/external/capstone/arch/Mips/
DMipsInstPrinter.c33 static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
34 static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
35 static char *printAlias(MCInst *MI, SStream *OS);
86 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
88 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
90 MI->csh->doing_mem = status; in set_mem_access()
92 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
96 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; in set_mem_access()
97 …MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INV… in set_mem_access()
98 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; in set_mem_access()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
104 unsigned getAddrModeSBit(const MachineInstr &MI,
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/external/capstone/arch/SystemZ/
DSystemZInstPrinter.c42 static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O) in printAddress() argument
62 if (MI->csh->detail) { in printAddress()
63 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; in printAddress()
64 …MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)Sys… in printAddress()
65 …MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)Sy… in printAddress()
66 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; in printAddress()
67 MI->flat_insn->detail->sysz.op_count++; in printAddress()
70 if (MI->csh->detail) { in printAddress()
71 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; in printAddress()
72 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; in printAddress()
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/external/capstone/arch/XCore/
DXCoreInstPrinter.c48 void XCore_insn_extract(MCInst *MI, const char *code) in XCore_insn_extract() argument
67 if (MI->csh->detail) { in XCore_insn_extract()
68 … MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; in XCore_insn_extract()
69 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; in XCore_insn_extract()
70 MI->flat_insn->detail->xcore.op_count++; in XCore_insn_extract()
89 if (MI->csh->detail) { in XCore_insn_extract()
90 … MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; in XCore_insn_extract()
91 …MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)i… in XCore_insn_extract()
92 …MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG… in XCore_insn_extract()
93 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; in XCore_insn_extract()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h46 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
189 bool expandPostRAPseudo(MachineInstr &MI) const override;
203 MachineBasicBlock::iterator MI) const override;
206 bool isPredicated(const MachineInstr &MI) const override;
210 bool PredicateInstruction(MachineInstr &MI,
221 bool DefinesPredicate(MachineInstr &MI,
227 bool isPredicable(MachineInstr &MI) const override;
231 bool isSchedulingBoundary(const MachineInstr &MI,
250 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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/external/llvm/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.h28 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
38 void printInstruction(const MCInst *MI, raw_ostream &OS);
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
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DX86IntelInstPrinter.h29 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
33 void printInstruction(const MCInst *MI, raw_ostream &O);
36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
38 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow() argument
32 if (MI->isCompare()) in lowerRILow()
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh() argument
46 if (MI->isCompare()) in lowerRIHigh()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
[all …]
DSystemZShortenInst.cpp44 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
45 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
48 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
49 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
67 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
69 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
70 MI.tieOperands(0, 1); in tieOpsIfNeeded()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp53 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
55 unsigned Opcode = MI->getOpcode(); in printInst()
60 const MCOperand &Dst = MI->getOperand(0); in printInst()
61 const MCOperand &MO1 = MI->getOperand(1); in printInst()
62 const MCOperand &MO2 = MI->getOperand(2); in printInst()
63 const MCOperand &MO3 = MI->getOperand(3); in printInst()
66 printSBitModifierOperand(MI, 6, O); in printInst()
67 printPredicateOperand(MI, 4, O); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
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DARMInstPrinter.h28 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
35 void printInstruction(const MCInst *MI, raw_ostream &O);
39 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
47 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
48 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
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/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitDefs(MachineInstr *MI);
68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
69 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
73 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
81 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
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/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
34 return MI.getOperand(OpNo).getReg() == R; in isReg()
79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
81 switch (MI->getOpcode()) { in printInst()
91 printSaveRestore(MI, O); in printInst()
96 printSaveRestore(MI, O); in printInst()
101 printSaveRestore(MI, O); in printInst()
106 printSaveRestore(MI, O); in printInst()
112 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) in printInst()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp34 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
37 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
38 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
39 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
40 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
50 printOperand(MI, 0, O); in printInst()
52 printOperand(MI, 1, O); in printInst()
60 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
61 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
63 printOperand(MI, 0, O); in printInst()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DExpandPostRAPseudos.cpp54 bool LowerSubregToReg(MachineInstr *MI);
55 bool LowerCopy(MachineInstr *MI);
57 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
59 void TransferImplicitDefs(MachineInstr *MI);
73 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg, in TransferDeadFlag() argument
76 prior(MachineBasicBlock::iterator(MI)); ; --MII) { in TransferDeadFlag()
79 assert(MII != MI->getParent()->begin() && in TransferDeadFlag()
88 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
89 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
92 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
[all …]
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp26 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
29 printInstruction(MI, OS); in printInst()
34 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, in printU4ImmOperand() argument
36 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
39 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, in printU8ImmOperand() argument
41 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
44 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand() argument
46 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand()
49 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, in printU32ImmOperand() argument
51 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
[all …]
DAMDGPUInstPrinter.h27 void printInstruction(const MCInst *MI, raw_ostream &O);
30 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
36 void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O,
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp67 unsigned getBinaryCodeForInstr(const MCInst &MI,
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]

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