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Searched refs:MI_FLUSH_DW (Results 1 – 7 of 7) sorted by relevance

/external/libdrm/intel/tests/
Dgen7-2d-copy.batch-ref.txt9 0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write'
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_reg.h42 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) macro
/external/mesa3d/src/gallium/drivers/ilo/core/
Dilo_builder_mi.h135 dw[0] = GEN6_MI_CMD(MI_FLUSH_DW) | (cmd_len - 2); in gen6_MI_FLUSH_DW()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c345 OUT_BATCH(MI_FLUSH_DW); in brw_emit_mi_flush()
Dintel_blit.c124 OUT_BATCH(MI_FLUSH_DW); in set_blitter_tiling()
Dbrw_defines.h3003 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) macro
/external/drm_gralloc/
Dgralloc_drm_intel.c47 #define MI_FLUSH_DW (0x26 << 23) macro