| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-shift-rs-t32.json | 41 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
42 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
43 // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
44 // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
45 // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
113 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
114 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
115 // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
116 // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
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| D | cond-rd-operand-rn-shift-amount-1to32-t32.json | 29 // MNEMONIC{<c>}.N <Rn>, <Rm>, LSL|ROR #<amount> ; Special case for MOV and MOVS
37 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
38 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
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| D | cond-rd-operand-const-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; A1
76 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; A1
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| D | cond-rd-operand-rn-shift-amount-1to31-t32.json | 36 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
37 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
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| D | cond-rd-operand-rn-t32.json | 45 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
46 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
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| D | cond-rdlow-operand-imm8-t32.json | 34 "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1
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| D | cond-rd-operand-const-t32.json | 35 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; T2
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| D | cond-rd-operand-rn-shift-amount-1to31-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-operand-rn-shift-amount-1to32-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_shiftrountine_with_round_hq.s | 36 MOVS r10, r4, ASR #0x19
43 MOVS r10, r5, ASR #0x19
51 MOVS r10, r6, ASR #0x19
59 MOVS r10, r7, ASR #0x19
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| D | ixheaacd_shiftrountine_with_round.s | 57 MOVS r10, r4, ASR #0x15
64 MOVS r10, r5, ASR #0x15
74 MOVS r10, r6, ASR #0x15
84 MOVS r10, r7, ASR #0x15
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| D | ixheaacd_shiftrountine.s | 69 MOVS r7, r12, ASR r2
75 MOVS r7, r5, ASR r2
86 MOVS r7, r12, ASR r2
92 MOVS r7, r5, ASR r2
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| D | ixheaacd_shiftrountine_with_rnd_eld.s | 43 …MOVS r10, r4, ASR #0x16 @Right shift by 22 to check the overflow ( is not AAC_ELD righ…
50 MOVS r10, r5, ASR #0x16
60 MOVS r10, r6, ASR #0x16
70 MOVS r10, r7, ASR #0x16
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| D | ixheaacd_rescale_subbandsamples.s | 30 MOVS R4, R4
47 MOVS R8, R8
51 MOVS R4, R4
108 MOVS R4, R4
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| D | ixheaacd_conv_ergtoamplitude.s | 40 MOVS R6, R6
68 MOVS R6, R6
96 MOVS R6, R6
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| D | ixheaacd_ffr_divide16.s | 29 MOVS r3, r1, ASR #1
32 MOVS r2, r0, ASR #1
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| D | ixheaacd_conv_ergtoamplitudelp.s | 39 MOVS R6, R6
65 MOVS R6, R6
93 MOVS R6, R6
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| D | ixheaacd_enery_calc_per_subband.s | 51 MOVS R8, R8
77 MOVS R11, R2
129 MOVS R6, R6
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| D | ixheaacd_calcmaxspectralline.s | 64 MOVS R2, R2
72 MOVS R0, R4
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| D | ixheaacd_tns_parcor2lpc_32x16.s | 62 MOVS R2, R10
87 MOVS R9, R9
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| D | ixheaacd_autocorr_st2.s | 81 MOVS r14, r14, LSR #1
254 MOVS r0 , r3 , LSR #2
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| D | ixheaacd_expsubbandsamples.s | 36 MOVS r3, r11
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| D | ixheaacd_harm_idx_zerotwolp.s | 55 MOVS r12, r12, LSL #16
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| D | ixheaacd_decorr_filter2.s | 531 MOVS r0, r0, LSL #16
761 MOVS r2, r2, lsl #1
804 MOVS r2, r1
812 MOVS r0, r0, lsl #16
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| /external/tremolo/Tremolo/ |
| D | dpen.s | 99 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
124 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
156 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
181 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
214 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
464 MOVS r12,r0
474 MOVS r6,r3 @ r6 = j = post
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