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Searched refs:Neon16 (Results 1 – 5 of 5) sorted by relevance

/external/v8/src/arm/
Dsimulator-arm.cc3470 size = Neon16; in DecodeTypeVFP()
3486 case Neon16: { in DecodeTypeVFP()
4054 case Neon16: in DecodeSpecialCondition()
4107 case Neon16: in DecodeSpecialCondition()
4140 case Neon16: { in DecodeSpecialCondition()
4190 case Neon16: { in DecodeSpecialCondition()
4238 case Neon16: { in DecodeSpecialCondition()
4275 case Neon16: { in DecodeSpecialCondition()
4317 case Neon16: { in DecodeSpecialCondition()
4479 case Neon16: { in DecodeSpecialCondition()
[all …]
Dcodegen-arm.cc208 __ vst1(Neon16, NeonListOperand(d0, 2), NeonMemOperand(dest, PostIndex)); in CreateMemCopyUint16Uint8Function()
218 __ vst1(Neon16, NeonListOperand(d0, 2), NeonMemOperand(dest)); in CreateMemCopyUint16Uint8Function()
Dconstants-arm.h351 Neon16 = 0x1, enumerator
Dassembler-arm.cc3990 case Neon16: in vdup()
4637 emit(EncodeNeonVREV(Neon16, size, dst, src)); in vrev16()
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc1669 __ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0)); in AssembleArchInstruction()
1683 __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
1697 __ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1707 __ vsub(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1717 __ vmul(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1732 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1738 __ vceq(Neon16, dst, i.InputSimd128Register(0), in AssembleArchInstruction()