| /external/pcre/dist2/src/ |
| D | pcre2_jit_compile.c | 557 #define OP2(op, dst, dstw, src1, src1w, src2, src2w) \ macro
2340 OP2(SLJIT_SUB | SLJIT_SET_E, COUNT_MATCH, 0, COUNT_MATCH, 0, SLJIT_IMM, 1); in count_match()
2350 OP2(SLJIT_ADD, STACK_TOP, 0, STACK_TOP, 0, SLJIT_IMM, size * sizeof(sljit_sw)); in allocate_stack()
2366 OP2(SLJIT_SUB, STACK_TOP, 0, STACK_TOP, 0, SLJIT_IMM, size * sizeof(sljit_sw)); in free_stack()
2398 OP2(SLJIT_SUB, SLJIT_R0, 0, SLJIT_MEM1(SLJIT_S0), SLJIT_OFFSETOF(jit_arguments, begin), SLJIT_IMM, … in reset_ovector()
2410 OP2(SLJIT_SUB | SLJIT_SET_E, SLJIT_R2, 0, SLJIT_R2, 0, SLJIT_IMM, 1); in reset_ovector()
2422 OP2(SLJIT_SUB, TMP1, 0, STR_PTR, 0, SLJIT_IMM, IN_UCHARS(1)); in reset_fast_fail()
2448 OP2(SLJIT_SUB | SLJIT_SET_E, STACK_TOP, 0, STACK_TOP, 0, SLJIT_IMM, 1); in do_reset_match()
2503 OP2(SLJIT_ADD, SLJIT_R2, 0, SLJIT_MEM1(SLJIT_R0), SLJIT_OFFSETOF(jit_arguments, match_data), in copy_ovector()
2510 OP2(SLJIT_SUB, SLJIT_S1, 0, SLJIT_MEM1(SLJIT_S0), 0, SLJIT_R0, 0); in copy_ovector()
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-v4-instructions.ll | 7 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
28 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
40 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
52 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
136 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
137 ; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
[all …]
|
| D | fp16-v8-instructions.ll | 289 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
290 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
301 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
303 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
341 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
342 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
353 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
355 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | hwloop4.ll | 5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]]
6 ; CHECK-NOT: add([[OP0]], #[[OP2]])
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 42 OP2 = (1 << 11), enumerator
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| D | R600InstrInfo.cpp | 135 (TargetFlags & R600_InstFlag::OP2) | in hasInstrModifiers()
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| /external/kernel-headers/original/uapi/asm-arm64/asm/ |
| D | kvm.h | 195 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 134 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
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| /external/boringssl/src/decrepit/cast/ |
| D | cast.c | 90 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \ argument
99 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \
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| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
| D | 67953778f85da1ac064d9515d31cd4f6.0001ecf4.honggfuzz.cov | 191 …��ř�e��A_�_� ���ŸtS���Dw9�}�c��V ��ց"�Cʮ�� 4i5cq�� �G2057q:�^��OP2_��X���;|��iG�0o� …
242 …��ř�e��A_�_� ���ŸtS���Dw9�}�c��V ��ց"�Cʮ�� 4i5cq�� �G2057q:�^��OP2_��X���;|��iG�0o� …
|
| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
| D | 67953778f85da1ac064d9515d31cd4f6.0001ecf4.honggfuzz.cov | 191 …��ř�e��A_�_� ���ŸtS���Dw9�}�c��V ��ց"�Cʮ�� 4i5cq�� �G2057q:�^��OP2_��X���;|��iG�0o� …
242 …��ř�e��A_�_� ���ŸtS���Dw9�}�c��V ��ց"�Cʮ�� 4i5cq�� �G2057q:�^��OP2_��X���;|��iG�0o� …
|
| /external/libevent/ |
| D | whatsnew-2.1.txt | 551 #define OP2 2
|