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Searched refs:Q5 (Results 1 – 25 of 219) sorted by relevance

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/external/libxaac/decoder/armv7/
Dia_xheaacd_mps_reoder_mulshift_acc.s61 VLD1.32 {Q4, Q5}, [R2]! @LOADING values from R2 N.real_fix
71 VMULL.S32 Q5, D7, D15
77 VSHR.S64 Q5, Q5, #31
87 VSUB.I64 Q11, Q11, Q5
105 VLD1.32 {Q4, Q5}, [R2]! @LOADING values from R2 N.real_fix
115 VMULL.S32 Q5, D7, D15
126 VSHR.S64 Q5, Q5, #31
131 VSUB.I64 Q11, Q11, Q5
149 VLD1.32 {Q4, Q5}, [R2]! @LOADING values from R2 N.real_fix
159 VMULL.S32 Q5, D7, D15
[all …]
Dixheaacd_esbr_cos_sin_mod_loop2.s76 VQSUB.S64 Q7, Q5, Q2
77 VQSUB.S64 Q8, Q2, Q5
107 VQSUB.S64 Q7, Q2, Q5
108 VQSUB.S64 Q8, Q5, Q2
Dixheaacd_esbr_cos_sin_mod_loop1.s55 VQSUB.S64 Q1, Q5, Q2
80 VADD.I64 Q0, Q5, Q2
107 VQSUB.S64 Q1, Q5, Q2
132 VADD.I64 Q0, Q5, Q2
Dia_xheaacd_mps_mulshift.s34 VQDMULL.S32 Q5, D2, D6
38 VUZP.32 Q5, Q7
Dixheaacd_mps_synt_pre_twiddle.s41 VMULL.S32 Q5, D1, D3
46 VSHRN.I64 D10, Q5, #31
Dixheaacd_mps_synt_post_twiddle.s41 VMULL.S32 Q5, D15, D3
46 VSHRN.I64 D10, Q5, #31
Dixheaacd_mps_synt_post_fft_twiddle.s44 VMULL.S32 Q5, D2, D6
49 VSHRN.S64 D10, Q5, #31
Dixheaacd_mps_synt_out_calc.s31 VMULL.S32 Q5, D1, D6
35 VSHRN.S64 D9, Q5, #31
Dixheaacd_calc_post_twid.s44 VMULL.S32 Q5, D6, D2
53 VSHRN.S64 D8, Q5, #32
Dixheaacd_overlap_add2.s195 VREV64.16 Q5, Q5
234 VREV64.16 Q5, Q5
Dixheaacd_esbr_fwd_modulation.s52 VQSUB.S32 Q5, Q1, Q3
90 VADD.I64 Q0, Q2, Q5
Dixheaacd_post_twiddle_overlap.s211 VLD2.32 {Q5, Q6}, [R6], R12
220 VREV64.16 Q5, Q5
399 VLD2.32 {Q5, Q6}, [R6], R12
408 VREV64.16 Q5, Q5
662 VLD2.32 {Q5, Q6}, [R6], R12
671 VREV64.16 Q5, Q5
1028 VREV64.16 Q5, Q5
Dixheaacd_pre_twiddle_compute.s111 VREV64.16 Q5, Q4
168 VREV64.16 Q5, Q4
237 VREV64.16 Q5, Q4
334 VREV64.16 Q5, Q4
Dixheaacd_dct3_32.s81 VSUB.I32 Q5, Q3, Q4
125 VSUB.I32 Q5, Q3, Q4
166 VSUB.I32 Q5, Q3, Q4
217 VSUB.I32 Q5, Q3, Q4
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s193 VMULL.S16 Q5,D5,D0[3] @//(U-128)*C4 FOR B
205 VQSHRN.S32 D9,Q5,#13 @//D9 = (U-128)*C4>>13 4 16-BIT VALUES
219 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
223 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
260 VADDW.U8 Q8,Q5,D28 @//Q2 - HAS Y + R
264 VADDW.U8 Q11,Q5,D29 @//Q11 - HAS Y + R
324 VMULL.S16 Q5,D5,D0[3] @//(U-128)*C4 FOR B
336 VQSHRN.S32 D9,Q5,#13 @//D9 = (U-128)*C4>>13 4 16-BIT VALUES
350 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
354 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
/external/libhevc/common/arm/
Dihevc_sao_edge_offset_class1.s142 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
145 VCLT.U8 Q7,Q5,Q4 @vcltq_u8(pu1_cur_row, pu1_top_row)
157 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
162 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
199 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
236 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
237 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
264 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
287 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
288 VCLT.U8 Q7,Q5,Q4 @vcltq_u8(pu1_cur_row, pu1_top_row)
[all …]
Dihevc_sao_edge_offset_class1_chroma.s146 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
149 VCLT.U8 Q7,Q5,Q14 @vcltq_u8(pu1_cur_row, pu1_top_row)
161 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
166 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
206 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
248 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
249 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
281 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
304 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
305 VCLT.U8 Q7,Q5,Q14 @vcltq_u8(pu1_cur_row, pu1_top_row)
[all …]
Dihevc_sao_edge_offset_class2.s257 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
261 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
302 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
306 …VSUB.U8 Q5,Q9,Q5 @I sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt…
308 VADD.I8 Q12,Q12,Q5 @I edge_idx = vaddq_s8(edge_idx, sign_down)
314 VNEG.S8 Q7,Q5 @I sign_up = vnegq_s8(sign_down)
384 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
394 …VSUB.U8 Q5,Q9,Q5 @III sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
403 VADD.I8 Q9,Q9,Q5 @III edge_idx = vaddq_s8(edge_idx, sign_down)
407 VNEG.S8 Q7,Q5 @III sign_up = vnegq_s8(sign_down)
[all …]
Dihevc_sao_edge_offset_class3.s272 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
282 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
317 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
319 …VSUB.U8 Q5,Q9,Q5 @I sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt…
322 VADD.I8 Q9,Q9,Q5 @I edge_idx = vaddq_s8(edge_idx, sign_down)
324 VNEG.S8 Q7,Q5 @I sign_up = vnegq_s8(sign_down)
419 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
428 …VSUB.U8 Q5,Q9,Q5 @III sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
432 VADD.I8 Q9,Q9,Q5 @III edge_idx = vaddq_s8(edge_idx, sign_down)
434 VNEG.S8 Q7,Q5 @III sign_up = vnegq_s8(sign_down)
[all …]
/external/fdlibm/
Ds_expm1.c127 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
187 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
/external/libavc/common/arm/
Dih264_deblk_chroma_a9.s102 vaddl.u8 q5, d7, d1 @Q4,Q5 = q0 + p1
107 vmlal.u8 q5, d3, d31 @Q5,Q4 = (X2(q1U) + q0U + p1U)
122 vrshrn.u16 d11, q14, #2 @Q5 = (X2(p1U) + p0U + q1U + 2) >> 2
185 vdup.8 q12, r3 @Q5 = beta
288 vsubl.u8 q4, d0, d4 @Q5,Q4 = (q0 - p0)
290 vshl.i16 q5, q5, #2 @Q5 = (q0 - p0)<<2
300 vadd.i16 q5, q5, q3 @Q5,Q4 = [ (q0 - p0)<<2 ] + (p1 - q1)
392 vdup.8 q12, r3 @Q5 = beta
714 vaddl.u8 q5, d7, d1 @Q4,Q5 = q0 + p1
719 vmlal.u8 q5, d3, d31 @Q5,Q4 = (X2(q1U) + q0U + p1U)
[all …]
/external/libmicrohttpd/src/testcurl/https/
Dhost2.key9 u5E0q1YdAkEA09FPcmzVvIR0+sMWca8QJ/tJUxD6qYo8vLOpO4wt4iTPhGBEU+Q5
/external/libxaac/decoder/
Dixheaacd_constants.h31 #define Q5 32 macro
/external/clang/test/CodeGen/
Dpartial-reinitialization1.c64 struct Q5 { struct

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