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Searched refs:R16 (Results 1 – 25 of 49) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Datomic.ll153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
154 ; ALL: sc $[[R16]], 0($[[R2]])
155 ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
156 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
157 ; MIPSR6: beqzc $[[R16]], $[[BB0]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
199 ; ALL: sc $[[R16]], 0($[[R2]])
200 ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
201 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
202 ; MIPSR6: beqzc $[[R16]], $[[BB0]]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll98 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
99 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
129 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
130 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
161 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
162 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
190 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
191 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
225 ; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
226 ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_formats.c169 F3(A, L16_UNORM, R16_UNORM, R, R, R, xx, UNORM, R16, TC),
170 F3(A, L16_SNORM, R16_SNORM, R, R, R, xx, SNORM, R16, TC),
171 F3(A, L16_FLOAT, R16_FLOAT, R, R, R, xx, FLOAT, R16, TB),
172 I3(A, L16_SINT, R16_SINT, R, R, R, xx, SINT, R16, TR),
173 I3(A, L16_UINT, R16_UINT, R, R, R, xx, UINT, R16, TR),
182 C4(A, I16_UNORM, R16_UNORM, R, R, R, R, UNORM, R16, TR),
183 C4(A, I16_SNORM, R16_SNORM, R, R, R, R, SNORM, R16, TR),
184 C4(A, I16_FLOAT, R16_FLOAT, R, R, R, R, FLOAT, R16, TR),
185 C4(A, I16_SINT, R16_SINT, R, R, R, R, SINT, R16, TR),
186 C4(A, I16_UINT, R16_UINT, R, R, R, R, UINT, R16, TR),
[all …]
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td61 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
98 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
141 R28, R29, R17, R16
147 add R23, R22, R21, R20, R19, R18, R17, R16
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaCallingConv.td30 CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
34 [R16, R17, R18, R19, R20, R21]>>,
DAlphaRegisterInfo.td54 def R16 : GPR<16, "$16">, DwarfRegNum<[16]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp51 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; in isCalleeSaveReg()
107 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
DHexagonFrameLowering.h63 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h121 case MBlaze::R16 : return 16; in getMBlazeRegisterNumbering()
186 case 16 : return MBlaze::R16; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
DSPURegisterInfo.cpp70 case SPU::R16: return 16; in getRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h169 {PPC::R16, -64}, in getCalleeSavedSpillSlots()
248 {PPC::R16, -124}, in getCalleeSavedSpillSlots()
DPPCRegisterInfo.td84 def R16 : GPR<16, "r16">, DwarfRegNum<[-2, 16]>;
118 def X16 : GP8<R16, "r16">, DwarfRegNum<[16, -2]>;
DPPCRegisterInfo.cpp107 PPC::R16, PPC::R17, PPC::R18, PPC::R19, in getCalleeSavedRegs()
133 PPC::R16, PPC::R17, PPC::R18, PPC::R19, in getCalleeSavedRegs()
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h10 #define R16 r16 macro
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h82 case Lanai::R16: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h47 case R16: case X16: case F16: case V16: case CR4LT: return 16; in getPPCRegisterNumbering()
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td47 (add R3, R9, R12, R13, R14, R16, R17,
/external/llvm/test/Transforms/LowerTypeTests/
Dsimple.ll80 ; CHECK: [[R16:%[^ ]*]] = phi i1 [ false, {{%[^ ]*}} ], [ [[R11]], {{%[^ ]*}} ]
86 ; CHECK: ret i1 [[R16]]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp79 Reserved.set(MBlaze::R16); in getReservedRegs()
DMBlazeRegisterInfo.td58 def R16 : MBlazeGPRReg< 16, "r16">, DwarfRegNum<[16]>;
/external/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td222 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
231 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp168 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td36 def R16 : RegisterClass;

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